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rseq/selftests: mips: use break instruction for RSEQ_SIG
Use break as guard instruction for the restartable sequence abort handler. Previously, the chosen signature was simply data, based on the assumption that it could always sit in a literal pool. However, some compilation environments favor disabling literal pool. Therefore, ensure the signature is a valid uncommon trap instruction. Suggested-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> CC: Paul Burton <paul.burton@mips.com> CC: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
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@ -7,7 +7,39 @@
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* (C) Copyright 2016-2018 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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* (C) Copyright 2016-2018 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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*/
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*/
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#define RSEQ_SIG 0x53053053
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/*
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* RSEQ_SIG uses the break instruction. The instruction pattern is:
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*
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* On MIPS:
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* 0350000d break 0x350
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*
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* On nanoMIPS:
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* 00100350 break 0x350
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*
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* On microMIPS:
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* 0000d407 break 0x350
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*
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* For nanoMIPS32 and microMIPS, the instruction stream is encoded as 16-bit
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* halfwords, so the signature halfwords need to be swapped accordingly for
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* little-endian.
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*/
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#if defined(__nanomips__)
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# ifdef __MIPSEL__
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# define RSEQ_SIG 0x03500010
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# else
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# define RSEQ_SIG 0x00100350
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# endif
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#elif defined(__mips_micromips)
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# ifdef __MIPSEL__
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# define RSEQ_SIG 0xd4070000
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# else
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# define RSEQ_SIG 0x0000d407
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# endif
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#elif defined(__mips__)
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# define RSEQ_SIG 0x0350000d
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#else
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/* Unknown MIPS architecture. */
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#endif
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#define rseq_smp_mb() __asm__ __volatile__ ("sync" ::: "memory")
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#define rseq_smp_mb() __asm__ __volatile__ ("sync" ::: "memory")
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#define rseq_smp_rmb() rseq_smp_mb()
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#define rseq_smp_rmb() rseq_smp_mb()
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