mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-27 12:57:53 +00:00
Revert "net: ethernet: qualcomm: Remove QDF24xx support"
This reverts commit a2a7f98aee.
Konrad mentioned that Qualcomm appears to use these devices, still,
internally, even tho they never made it to the broader market.
Link: https://lore.kernel.org/all/0679f568-60e7-47d8-b86e-052a9eb4c103@linaro.org/
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
parent
fa47527c71
commit
16c595a53c
5 changed files with 523 additions and 23 deletions
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@ -6,4 +6,5 @@
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obj-$(CONFIG_QCOM_EMAC) += qcom-emac.o
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qcom-emac-objs := emac.o emac-mac.o emac-phy.o emac-sgmii.o emac-ethtool.o \
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emac-sgmii-fsm9900.o
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emac-sgmii-fsm9900.o emac-sgmii-qdf2432.o \
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emac-sgmii-qdf2400.o
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215
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
Normal file
215
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
Normal file
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@ -0,0 +1,215 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*/
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/* Qualcomm Technologies, Inc. QDF2400 EMAC SGMII Controller driver.
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*/
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#include <linux/iopoll.h>
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#include "emac.h"
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/* EMAC_SGMII register offsets */
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#define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C
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#define EMAC_SGMII_PHY_LANE_CTRL1 0x0018
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#define EMAC_SGMII_PHY_CDR_CTRL0 0x0058
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#define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080
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#define EMAC_SGMII_PHY_RESET_CTRL 0x00a8
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#define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
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/* SGMII digital lane registers */
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#define EMAC_SGMII_LN_DRVR_CTRL0 0x000C
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#define EMAC_SGMII_LN_DRVR_CTRL1 0x0010
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#define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018
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#define EMAC_SGMII_LN_TX_MARGINING 0x001C
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#define EMAC_SGMII_LN_TX_PRE 0x0020
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#define EMAC_SGMII_LN_TX_POST 0x0024
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#define EMAC_SGMII_LN_TX_BAND_MODE 0x0060
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#define EMAC_SGMII_LN_LANE_MODE 0x0064
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#define EMAC_SGMII_LN_PARALLEL_RATE 0x007C
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#define EMAC_SGMII_LN_CML_CTRL_MODE0 0x00C0
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#define EMAC_SGMII_LN_MIXER_CTRL_MODE0 0x00D8
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#define EMAC_SGMII_LN_VGA_INITVAL 0x013C
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#define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0 0x0184
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#define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0 0x0190
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#define EMAC_SGMII_LN_UCDR_SO_CONFIG 0x019C
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#define EMAC_SGMII_LN_RX_BAND 0x01A4
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#define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0 0x01C0
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#define EMAC_SGMII_LN_RSM_CONFIG 0x01F8
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#define EMAC_SGMII_LN_SIGDET_ENABLES 0x0230
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#define EMAC_SGMII_LN_SIGDET_CNTRL 0x0234
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#define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL 0x0238
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#define EMAC_SGMII_LN_RX_EN_SIGNAL 0x02AC
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#define EMAC_SGMII_LN_RX_MISC_CNTRL0 0x02B8
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#define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV 0x02C8
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#define EMAC_SGMII_LN_RX_RESECODE_OFFSET 0x02CC
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/* SGMII digital lane register values */
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#define UCDR_STEP_BY_TWO_MODE0 BIT(7)
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#define UCDR_xO_GAIN_MODE(x) ((x) & 0x7f)
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#define UCDR_ENABLE BIT(6)
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#define UCDR_SO_SATURATION(x) ((x) & 0x3f)
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#define SIGDET_LP_BYP_PS4 BIT(7)
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#define SIGDET_EN_PS0_TO_PS2 BIT(6)
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#define TXVAL_VALID_INIT BIT(4)
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#define KR_PCIGEN3_MODE BIT(0)
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#define MAIN_EN BIT(0)
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#define TX_MARGINING_MUX BIT(6)
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#define TX_MARGINING(x) ((x) & 0x3f)
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#define TX_PRE_MUX BIT(6)
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#define TX_POST_MUX BIT(6)
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#define CML_GEAR_MODE(x) (((x) & 7) << 3)
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#define CML2CMOS_IBOOST_MODE(x) ((x) & 7)
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#define RESCODE_OFFSET(x) ((x) & 0x1f)
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#define MIXER_LOADB_MODE(x) (((x) & 0xf) << 2)
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#define MIXER_DATARATE_MODE(x) ((x) & 3)
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#define VGA_THRESH_DFE(x) ((x) & 0x3f)
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#define SIGDET_LP_BYP_PS0_TO_PS2 BIT(5)
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#define SIGDET_FLT_BYP BIT(0)
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#define SIGDET_LVL(x) (((x) & 0xf) << 4)
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#define SIGDET_DEGLITCH_CTRL(x) (((x) & 0xf) << 1)
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#define INVERT_PCS_RX_CLK BIT(7)
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#define DRVR_LOGIC_CLK_EN BIT(4)
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#define DRVR_LOGIC_CLK_DIV(x) ((x) & 0xf)
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#define PARALLEL_RATE_MODE0(x) ((x) & 0x3)
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#define BAND_MODE0(x) ((x) & 0x3)
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#define LANE_MODE(x) ((x) & 0x1f)
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#define CDR_PD_SEL_MODE0(x) (((x) & 0x3) << 5)
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#define EN_DLL_MODE0 BIT(4)
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#define EN_IQ_DCC_MODE0 BIT(3)
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#define EN_IQCAL_MODE0 BIT(2)
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#define BYPASS_RSM_SAMP_CAL BIT(1)
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#define BYPASS_RSM_DLL_CAL BIT(0)
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#define L0_RX_EQUALIZE_ENABLE BIT(6)
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#define PWRDN_B BIT(0)
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#define CDR_MAX_CNT(x) ((x) & 0xff)
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#define SERDES_START_WAIT_TIMES 100
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struct emac_reg_write {
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unsigned int offset;
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u32 val;
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};
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static void emac_reg_write_all(void __iomem *base,
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const struct emac_reg_write *itr, size_t size)
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{
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size_t i;
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for (i = 0; i < size; ++itr, ++i)
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writel(itr->val, base + itr->offset);
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}
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static const struct emac_reg_write sgmii_laned[] = {
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/* CDR Settings */
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{EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0,
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UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)},
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{EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
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{EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)},
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/* TX/RX Settings */
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{EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2},
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{EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE},
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{EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN},
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{EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)},
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{EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX},
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{EMAC_SGMII_LN_TX_POST, TX_POST_MUX},
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{EMAC_SGMII_LN_CML_CTRL_MODE0,
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CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)},
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{EMAC_SGMII_LN_MIXER_CTRL_MODE0,
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MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)},
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{EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)},
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{EMAC_SGMII_LN_SIGDET_ENABLES,
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SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP},
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{EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)},
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{EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)},
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{EMAC_SGMII_LN_RX_MISC_CNTRL0, INVERT_PCS_RX_CLK},
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{EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV,
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DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)},
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{EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
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{EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(1)},
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{EMAC_SGMII_LN_RX_BAND, BAND_MODE0(2)},
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{EMAC_SGMII_LN_DRVR_CTRL1, RESCODE_OFFSET(7)},
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{EMAC_SGMII_LN_RX_RESECODE_OFFSET, RESCODE_OFFSET(9)},
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{EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
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{EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(2) |
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EN_DLL_MODE0 | EN_IQ_DCC_MODE0 | EN_IQCAL_MODE0},
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{EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL},
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};
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static const struct emac_reg_write physical_coding_sublayer_programming[] = {
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{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
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{EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
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{EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
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{EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE},
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};
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int emac_sgmii_init_qdf2400(struct emac_adapter *adpt)
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{
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struct emac_sgmii *phy = &adpt->phy;
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void __iomem *phy_regs = phy->base;
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void __iomem *laned = phy->digital;
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unsigned int i;
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u32 lnstatus;
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/* PCS lane-x init */
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emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
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ARRAY_SIZE(physical_coding_sublayer_programming));
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/* SGMII lane-x init */
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emac_reg_write_all(phy->digital, sgmii_laned, ARRAY_SIZE(sgmii_laned));
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/* Power up PCS and start reset lane state machine */
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writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
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writel(1, laned + SGMII_LN_RSM_START);
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/* Wait for c_ready assertion */
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for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
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lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS);
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if (lnstatus & BIT(1))
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break;
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usleep_range(100, 200);
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}
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if (i == SERDES_START_WAIT_TIMES) {
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netdev_err(adpt->netdev, "SGMII failed to start\n");
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return -EIO;
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}
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/* Disable digital and SERDES loopback */
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writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
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writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
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writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
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/* Mask out all the SGMII Interrupt */
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writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
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return 0;
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}
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202
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
Normal file
202
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
Normal file
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@ -0,0 +1,202 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*/
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/* Qualcomm Technologies, Inc. QDF2432 EMAC SGMII Controller driver.
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*/
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#include <linux/iopoll.h>
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#include "emac.h"
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/* EMAC_SGMII register offsets */
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#define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C
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#define EMAC_SGMII_PHY_LANE_CTRL1 0x0018
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#define EMAC_SGMII_PHY_CDR_CTRL0 0x0058
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#define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080
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#define EMAC_SGMII_PHY_RESET_CTRL 0x00a8
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#define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
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/* SGMII digital lane registers */
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#define EMAC_SGMII_LN_DRVR_CTRL0 0x000C
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#define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018
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#define EMAC_SGMII_LN_TX_MARGINING 0x001C
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#define EMAC_SGMII_LN_TX_PRE 0x0020
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#define EMAC_SGMII_LN_TX_POST 0x0024
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#define EMAC_SGMII_LN_TX_BAND_MODE 0x0060
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#define EMAC_SGMII_LN_LANE_MODE 0x0064
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#define EMAC_SGMII_LN_PARALLEL_RATE 0x0078
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#define EMAC_SGMII_LN_CML_CTRL_MODE0 0x00B8
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#define EMAC_SGMII_LN_MIXER_CTRL_MODE0 0x00D0
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#define EMAC_SGMII_LN_VGA_INITVAL 0x0134
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#define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0 0x017C
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#define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0 0x0188
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#define EMAC_SGMII_LN_UCDR_SO_CONFIG 0x0194
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#define EMAC_SGMII_LN_RX_BAND 0x019C
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#define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0 0x01B8
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#define EMAC_SGMII_LN_RSM_CONFIG 0x01F0
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#define EMAC_SGMII_LN_SIGDET_ENABLES 0x0224
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#define EMAC_SGMII_LN_SIGDET_CNTRL 0x0228
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#define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL 0x022C
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#define EMAC_SGMII_LN_RX_EN_SIGNAL 0x02A0
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#define EMAC_SGMII_LN_RX_MISC_CNTRL0 0x02AC
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#define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV 0x02BC
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/* SGMII digital lane register values */
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#define UCDR_STEP_BY_TWO_MODE0 BIT(7)
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#define UCDR_xO_GAIN_MODE(x) ((x) & 0x7f)
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#define UCDR_ENABLE BIT(6)
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#define UCDR_SO_SATURATION(x) ((x) & 0x3f)
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#define SIGDET_LP_BYP_PS4 BIT(7)
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#define SIGDET_EN_PS0_TO_PS2 BIT(6)
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#define TXVAL_VALID_INIT BIT(4)
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#define KR_PCIGEN3_MODE BIT(0)
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#define MAIN_EN BIT(0)
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#define TX_MARGINING_MUX BIT(6)
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#define TX_MARGINING(x) ((x) & 0x3f)
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#define TX_PRE_MUX BIT(6)
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#define TX_POST_MUX BIT(6)
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#define CML_GEAR_MODE(x) (((x) & 7) << 3)
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#define CML2CMOS_IBOOST_MODE(x) ((x) & 7)
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#define MIXER_LOADB_MODE(x) (((x) & 0xf) << 2)
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#define MIXER_DATARATE_MODE(x) ((x) & 3)
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#define VGA_THRESH_DFE(x) ((x) & 0x3f)
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#define SIGDET_LP_BYP_PS0_TO_PS2 BIT(5)
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#define SIGDET_FLT_BYP BIT(0)
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#define SIGDET_LVL(x) (((x) & 0xf) << 4)
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#define SIGDET_DEGLITCH_CTRL(x) (((x) & 0xf) << 1)
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#define DRVR_LOGIC_CLK_EN BIT(4)
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#define DRVR_LOGIC_CLK_DIV(x) ((x) & 0xf)
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#define PARALLEL_RATE_MODE0(x) ((x) & 0x3)
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#define BAND_MODE0(x) ((x) & 0x3)
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#define LANE_MODE(x) ((x) & 0x1f)
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#define CDR_PD_SEL_MODE0(x) (((x) & 0x3) << 5)
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#define BYPASS_RSM_SAMP_CAL BIT(1)
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#define BYPASS_RSM_DLL_CAL BIT(0)
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#define L0_RX_EQUALIZE_ENABLE BIT(6)
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#define PWRDN_B BIT(0)
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#define CDR_MAX_CNT(x) ((x) & 0xff)
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#define SERDES_START_WAIT_TIMES 100
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struct emac_reg_write {
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unsigned int offset;
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u32 val;
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};
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static void emac_reg_write_all(void __iomem *base,
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const struct emac_reg_write *itr, size_t size)
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{
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size_t i;
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for (i = 0; i < size; ++itr, ++i)
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writel(itr->val, base + itr->offset);
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}
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static const struct emac_reg_write sgmii_laned[] = {
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/* CDR Settings */
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{EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0,
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UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)},
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{EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
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{EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)},
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/* TX/RX Settings */
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{EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2},
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{EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE},
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{EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN},
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{EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)},
|
||||
{EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX},
|
||||
{EMAC_SGMII_LN_TX_POST, TX_POST_MUX},
|
||||
|
||||
{EMAC_SGMII_LN_CML_CTRL_MODE0,
|
||||
CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)},
|
||||
{EMAC_SGMII_LN_MIXER_CTRL_MODE0,
|
||||
MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)},
|
||||
{EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)},
|
||||
{EMAC_SGMII_LN_SIGDET_ENABLES,
|
||||
SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP},
|
||||
{EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)},
|
||||
|
||||
{EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)},
|
||||
{EMAC_SGMII_LN_RX_MISC_CNTRL0, 0},
|
||||
{EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV,
|
||||
DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)},
|
||||
|
||||
{EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
|
||||
{EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(2)},
|
||||
{EMAC_SGMII_LN_RX_BAND, BAND_MODE0(3)},
|
||||
{EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
|
||||
{EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(3)},
|
||||
{EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL},
|
||||
};
|
||||
|
||||
static const struct emac_reg_write physical_coding_sublayer_programming[] = {
|
||||
{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
|
||||
{EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
|
||||
{EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
|
||||
{EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE},
|
||||
};
|
||||
|
||||
int emac_sgmii_init_qdf2432(struct emac_adapter *adpt)
|
||||
{
|
||||
struct emac_sgmii *phy = &adpt->phy;
|
||||
void __iomem *phy_regs = phy->base;
|
||||
void __iomem *laned = phy->digital;
|
||||
unsigned int i;
|
||||
u32 lnstatus;
|
||||
|
||||
/* PCS lane-x init */
|
||||
emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
|
||||
ARRAY_SIZE(physical_coding_sublayer_programming));
|
||||
|
||||
/* SGMII lane-x init */
|
||||
emac_reg_write_all(phy->digital, sgmii_laned, ARRAY_SIZE(sgmii_laned));
|
||||
|
||||
/* Power up PCS and start reset lane state machine */
|
||||
|
||||
writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
|
||||
writel(1, laned + SGMII_LN_RSM_START);
|
||||
|
||||
/* Wait for c_ready assertion */
|
||||
for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
|
||||
lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS);
|
||||
if (lnstatus & BIT(1))
|
||||
break;
|
||||
usleep_range(100, 200);
|
||||
}
|
||||
|
||||
if (i == SERDES_START_WAIT_TIMES) {
|
||||
netdev_err(adpt->netdev, "SGMII failed to start\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Disable digital and SERDES loopback */
|
||||
writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
|
||||
writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
|
||||
writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
|
||||
|
||||
/* Mask out all the SGMII Interrupt */
|
||||
writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
|
@ -274,11 +275,76 @@ static struct sgmii_ops fsm9900_ops = {
|
|||
.reset = emac_sgmii_common_reset,
|
||||
};
|
||||
|
||||
static struct sgmii_ops qdf2432_ops = {
|
||||
.init = emac_sgmii_init_qdf2432,
|
||||
.open = emac_sgmii_common_open,
|
||||
.close = emac_sgmii_common_close,
|
||||
.link_change = emac_sgmii_common_link_change,
|
||||
.reset = emac_sgmii_common_reset,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static struct sgmii_ops qdf2400_ops = {
|
||||
.init = emac_sgmii_init_qdf2400,
|
||||
.open = emac_sgmii_common_open,
|
||||
.close = emac_sgmii_common_close,
|
||||
.link_change = emac_sgmii_common_link_change,
|
||||
.reset = emac_sgmii_common_reset,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int emac_sgmii_acpi_match(struct device *dev, void *data)
|
||||
{
|
||||
#ifdef CONFIG_ACPI
|
||||
static const struct acpi_device_id match_table[] = {
|
||||
{
|
||||
.id = "QCOM8071",
|
||||
},
|
||||
{}
|
||||
};
|
||||
const struct acpi_device_id *id = acpi_match_device(match_table, dev);
|
||||
struct sgmii_ops **ops = data;
|
||||
|
||||
if (id) {
|
||||
acpi_handle handle = ACPI_HANDLE(dev);
|
||||
unsigned long long hrv;
|
||||
acpi_status status;
|
||||
|
||||
status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
|
||||
if (status) {
|
||||
if (status == AE_NOT_FOUND)
|
||||
/* Older versions of the QDF2432 ACPI tables do
|
||||
* not have an _HRV property.
|
||||
*/
|
||||
hrv = 1;
|
||||
else
|
||||
/* Something is wrong with the tables */
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (hrv) {
|
||||
case 1:
|
||||
*ops = &qdf2432_ops;
|
||||
return 1;
|
||||
case 2:
|
||||
*ops = &qdf2400_ops;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id emac_sgmii_dt_match[] = {
|
||||
{
|
||||
.compatible = "qcom,fsm9900-emac-sgmii",
|
||||
.data = &fsm9900_ops,
|
||||
},
|
||||
{
|
||||
.compatible = "qcom,qdf2432-emac-sgmii",
|
||||
.data = &qdf2432_ops,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -289,31 +355,45 @@ int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
|
|||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
const struct of_device_id *match;
|
||||
struct device_node *np;
|
||||
if (has_acpi_companion(&pdev->dev)) {
|
||||
struct device *dev;
|
||||
|
||||
np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "missing internal-phy property\n");
|
||||
return -ENODEV;
|
||||
dev = device_find_child(&pdev->dev, &phy->sgmii_ops,
|
||||
emac_sgmii_acpi_match);
|
||||
|
||||
if (!dev) {
|
||||
dev_warn(&pdev->dev, "cannot find internal phy node\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
sgmii_pdev = to_platform_device(dev);
|
||||
} else {
|
||||
const struct of_device_id *match;
|
||||
struct device_node *np;
|
||||
|
||||
np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "missing internal-phy property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sgmii_pdev = of_find_device_by_node(np);
|
||||
of_node_put(np);
|
||||
if (!sgmii_pdev) {
|
||||
dev_err(&pdev->dev, "invalid internal-phy property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
|
||||
if (!match) {
|
||||
dev_err(&pdev->dev, "unrecognized internal phy node\n");
|
||||
ret = -ENODEV;
|
||||
goto error_put_device;
|
||||
}
|
||||
|
||||
phy->sgmii_ops = (struct sgmii_ops *)match->data;
|
||||
}
|
||||
|
||||
sgmii_pdev = of_find_device_by_node(np);
|
||||
of_node_put(np);
|
||||
if (!sgmii_pdev) {
|
||||
dev_err(&pdev->dev, "invalid internal-phy property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
|
||||
if (!match) {
|
||||
dev_err(&pdev->dev, "unrecognized internal phy node\n");
|
||||
ret = -ENODEV;
|
||||
goto error_put_device;
|
||||
}
|
||||
|
||||
phy->sgmii_ops = (struct sgmii_ops *)match->data;
|
||||
|
||||
/* Base address is the first address */
|
||||
res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ struct emac_sgmii {
|
|||
int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt);
|
||||
|
||||
int emac_sgmii_init_fsm9900(struct emac_adapter *adpt);
|
||||
int emac_sgmii_init_qdf2432(struct emac_adapter *adpt);
|
||||
int emac_sgmii_init_qdf2400(struct emac_adapter *adpt);
|
||||
|
||||
int emac_sgmii_init(struct emac_adapter *adpt);
|
||||
int emac_sgmii_open(struct emac_adapter *adpt);
|
||||
|
|
|
|||
Loading…
Reference in a new issue