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[SPARC64]: Convert PCI over to generic struct iommu/strbuf.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
ee5ac9ddf2
commit
16ce82d846
6 changed files with 66 additions and 144 deletions
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@ -1,7 +1,6 @@
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/* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $
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* pci_iommu.c: UltraSparc PCI controller IOM/STC support.
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/* pci_iommu.c: UltraSparc PCI controller IOM/STC support.
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*
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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* Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
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*/
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@ -36,7 +35,7 @@
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"i" (ASI_PHYS_BYPASS_EC_E))
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/* Must be invoked under the IOMMU lock. */
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static void __iommu_flushall(struct pci_iommu *iommu)
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static void __iommu_flushall(struct iommu *iommu)
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{
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unsigned long tag;
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int entry;
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@ -64,7 +63,7 @@ static void __iommu_flushall(struct pci_iommu *iommu)
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#define IOPTE_IS_DUMMY(iommu, iopte) \
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((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
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static inline void iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
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static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
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{
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unsigned long val = iopte_val(*iopte);
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@ -75,7 +74,7 @@ static inline void iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
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}
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/* Based largely upon the ppc64 iommu allocator. */
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static long pci_arena_alloc(struct pci_iommu *iommu, unsigned long npages)
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static long pci_arena_alloc(struct iommu *iommu, unsigned long npages)
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{
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struct iommu_arena *arena = &iommu->arena;
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unsigned long n, i, start, end, limit;
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@ -124,7 +123,7 @@ static void pci_arena_free(struct iommu_arena *arena, unsigned long base, unsign
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__clear_bit(i, arena->map);
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}
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void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
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void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
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{
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unsigned long i, tsbbase, order, sz, num_tsb_entries;
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@ -170,7 +169,7 @@ void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset,
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iopte_make_dummy(iommu, &iommu->page_table[i]);
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}
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static inline iopte_t *alloc_npages(struct pci_iommu *iommu, unsigned long npages)
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static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages)
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{
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long entry;
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@ -181,12 +180,12 @@ static inline iopte_t *alloc_npages(struct pci_iommu *iommu, unsigned long npage
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return iommu->page_table + entry;
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}
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static inline void free_npages(struct pci_iommu *iommu, dma_addr_t base, unsigned long npages)
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static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages)
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{
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pci_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
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}
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static int iommu_alloc_ctx(struct pci_iommu *iommu)
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static int iommu_alloc_ctx(struct iommu *iommu)
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{
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int lowest = iommu->ctx_lowest_free;
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int sz = IOMMU_NUM_CTXS - lowest;
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@ -205,7 +204,7 @@ static int iommu_alloc_ctx(struct pci_iommu *iommu)
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return n;
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}
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static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
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static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
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{
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if (likely(ctx)) {
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__clear_bit(ctx, iommu->ctx_bitmap);
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@ -220,7 +219,7 @@ static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
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*/
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static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
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{
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struct pci_iommu *iommu;
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struct iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, first_page;
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void *ret;
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@ -266,7 +265,7 @@ static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr
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/* Free and unmap a consistent DMA translation. */
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static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
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{
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struct pci_iommu *iommu;
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struct iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, npages;
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@ -291,8 +290,8 @@ static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu,
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*/
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static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
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{
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr, ctx;
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@ -343,7 +342,7 @@ static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz,
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return PCI_DMA_ERROR_CODE;
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}
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static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
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static void pci_strbuf_flush(struct strbuf *strbuf, struct iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
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{
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int limit;
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@ -410,8 +409,8 @@ static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu,
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/* Unmap a single streaming mode DMA translation. */
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static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, ctx, i;
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@ -541,8 +540,8 @@ static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
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*/
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static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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struct iommu *iommu;
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struct strbuf *strbuf;
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unsigned long flags, ctx, npages, iopte_protection;
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iopte_t *base;
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u32 dma_base;
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/* Unmap a set of streaming mode DMA translations. */
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static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, ctx, i, npages;
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u32 bus_addr;
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*/
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static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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struct iommu *iommu;
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struct strbuf *strbuf;
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unsigned long flags, ctx, npages;
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iommu = pdev->dev.archdata.iommu;
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*/
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static void pci_4u_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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struct iommu *iommu;
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struct strbuf *strbuf;
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unsigned long flags, ctx, npages, i;
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u32 bus_addr;
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@ -798,7 +797,7 @@ int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
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if (pdev == NULL) {
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dma_addr_mask = 0xffffffff;
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} else {
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struct pci_iommu *iommu = pdev->dev.archdata.iommu;
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struct iommu *iommu = pdev->dev.archdata.iommu;
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dma_addr_mask = iommu->dma_addr_mask;
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@ -269,7 +269,7 @@ static void __psycho_check_one_stc(struct pci_controller_info *p,
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struct pci_pbm_info *pbm,
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int is_pbm_a)
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{
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struct pci_strbuf *strbuf = &pbm->stc;
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struct strbuf *strbuf = &pbm->stc;
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unsigned long regbase = p->pbm_A.controller_regs;
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unsigned long err_base, tag_base, line_base;
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u64 control;
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unsigned long afar,
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enum psycho_error_type type)
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{
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struct pci_iommu *iommu = p->pbm_A.iommu;
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struct iommu *iommu = p->pbm_A.iommu;
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unsigned long iommu_tag[16];
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unsigned long iommu_data[16];
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unsigned long flags;
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static void psycho_iommu_init(struct pci_controller_info *p)
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{
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struct pci_iommu *iommu = p->pbm_A.iommu;
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struct iommu *iommu = p->pbm_A.iommu;
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unsigned long i;
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u64 control;
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{
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struct linux_prom64_registers *pr_regs;
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struct pci_controller_info *p;
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struct pci_iommu *iommu;
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struct iommu *iommu;
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struct property *prop;
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u32 upa_portid;
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int is_pbm_a;
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prom_printf("PSYCHO: Fatal memory allocation error.\n");
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prom_halt();
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}
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iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
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iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
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if (!iommu) {
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prom_printf("PSYCHO: Fatal memory allocation error.\n");
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prom_halt();
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@ -1,7 +1,6 @@
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/* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
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* pci_sabre.c: Sabre specific PCI controller support.
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/* pci_sabre.c: Sabre specific PCI controller support.
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*
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* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
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* Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
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*/
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@ -499,7 +498,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
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unsigned long afsr,
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unsigned long afar)
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{
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struct pci_iommu *iommu = p->pbm_A.iommu;
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struct iommu *iommu = p->pbm_A.iommu;
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unsigned long iommu_tag[16];
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unsigned long iommu_data[16];
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unsigned long flags;
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@ -948,7 +947,7 @@ static void sabre_iommu_init(struct pci_controller_info *p,
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int tsbsize, unsigned long dvma_offset,
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u32 dma_mask)
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{
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struct pci_iommu *iommu = p->pbm_A.iommu;
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struct iommu *iommu = p->pbm_A.iommu;
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unsigned long i;
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u64 control;
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{
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const struct linux_prom64_registers *pr_regs;
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struct pci_controller_info *p;
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struct pci_iommu *iommu;
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struct iommu *iommu;
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int tsbsize;
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const u32 *busrange;
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const u32 *vdma;
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@ -279,7 +279,7 @@ struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
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static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
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enum schizo_error_type type)
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{
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struct pci_strbuf *strbuf = &pbm->stc;
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struct strbuf *strbuf = &pbm->stc;
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unsigned long regbase = pbm->pbm_regs;
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unsigned long err_base, tag_base, line_base;
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u64 control;
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@ -387,7 +387,7 @@ static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
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static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
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enum schizo_error_type type)
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{
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struct pci_iommu *iommu = pbm->iommu;
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struct iommu *iommu = pbm->iommu;
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unsigned long iommu_tag[16];
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unsigned long iommu_data[16];
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unsigned long flags;
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@ -1308,7 +1308,7 @@ static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
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static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
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{
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struct pci_iommu *iommu = pbm->iommu;
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struct iommu *iommu = pbm->iommu;
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unsigned long i, tagbase, database;
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struct property *prop;
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u32 vdma[2], dma_mask;
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@ -1580,7 +1580,7 @@ static inline int portid_compare(u32 x, u32 y, int chip_type)
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static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
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{
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struct pci_controller_info *p;
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struct pci_iommu *iommu;
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struct iommu *iommu;
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u32 portid;
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portid = of_getintprop_default(dp, "portid", 0xff);
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if (!p)
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goto memfail;
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iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
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iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
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if (!iommu)
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goto memfail;
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p->pbm_A.iommu = iommu;
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iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
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iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
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if (!iommu)
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goto memfail;
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@ -29,7 +29,7 @@
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#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
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struct pci_iommu_batch {
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struct iommu_batch {
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struct pci_dev *pdev; /* Device mapping is for. */
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unsigned long prot; /* IOMMU page protections */
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unsigned long entry; /* Index into IOTSB. */
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unsigned long npages; /* Number of pages in list. */
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};
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static DEFINE_PER_CPU(struct pci_iommu_batch, pci_iommu_batch);
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static DEFINE_PER_CPU(struct iommu_batch, pci_iommu_batch);
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/* Interrupts must be disabled. */
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static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry)
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{
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struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
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struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
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p->pdev = pdev;
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p->prot = prot;
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@ -51,7 +51,7 @@ static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long pro
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}
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/* Interrupts must be disabled. */
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static long pci_iommu_batch_flush(struct pci_iommu_batch *p)
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static long pci_iommu_batch_flush(struct iommu_batch *p)
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{
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struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
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unsigned long devhandle = pbm->devhandle;
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@ -89,7 +89,7 @@ static long pci_iommu_batch_flush(struct pci_iommu_batch *p)
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/* Interrupts must be disabled. */
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static inline long pci_iommu_batch_add(u64 phys_page)
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{
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struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
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struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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@ -103,7 +103,7 @@ static inline long pci_iommu_batch_add(u64 phys_page)
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/* Interrupts must be disabled. */
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static inline long pci_iommu_batch_end(void)
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{
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struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
|
||||
struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
|
||||
|
||||
BUG_ON(p->npages >= PGLIST_NENTS);
|
||||
|
||||
|
@ -159,7 +159,7 @@ static void pci_arena_free(struct iommu_arena *arena, unsigned long base, unsign
|
|||
|
||||
static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
|
||||
{
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, order, first_page, npages, n;
|
||||
void *ret;
|
||||
long entry;
|
||||
|
@ -225,7 +225,7 @@ static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr
|
|||
static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
|
||||
{
|
||||
struct pci_pbm_info *pbm;
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, order, npages, entry;
|
||||
u32 devhandle;
|
||||
|
||||
|
@ -257,7 +257,7 @@ static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu,
|
|||
|
||||
static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
|
||||
{
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, npages, oaddr;
|
||||
unsigned long i, base_paddr;
|
||||
u32 bus_addr, ret;
|
||||
|
@ -321,7 +321,7 @@ static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz,
|
|||
static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
|
||||
{
|
||||
struct pci_pbm_info *pbm;
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, npages;
|
||||
long entry;
|
||||
u32 devhandle;
|
||||
|
@ -456,7 +456,7 @@ static inline long fill_sg(long entry, struct pci_dev *pdev,
|
|||
|
||||
static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
||||
{
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, npages, prot;
|
||||
u32 dma_base;
|
||||
struct scatterlist *sgtmp;
|
||||
|
@ -532,7 +532,7 @@ static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int n
|
|||
static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
||||
{
|
||||
struct pci_pbm_info *pbm;
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, i, npages;
|
||||
long entry;
|
||||
u32 devhandle, bus_addr;
|
||||
|
@ -705,7 +705,7 @@ static void pci_sun4v_scan_bus(struct pci_controller_info *p)
|
|||
}
|
||||
|
||||
static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
|
||||
struct pci_iommu *iommu)
|
||||
struct iommu *iommu)
|
||||
{
|
||||
struct iommu_arena *arena = &iommu->arena;
|
||||
unsigned long i, cnt = 0;
|
||||
|
@ -734,7 +734,7 @@ static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
|
|||
|
||||
static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
|
||||
{
|
||||
struct pci_iommu *iommu = pbm->iommu;
|
||||
struct iommu *iommu = pbm->iommu;
|
||||
struct property *prop;
|
||||
unsigned long num_tsb_entries, sz;
|
||||
u32 vdma[2], dma_mask, dma_offset;
|
||||
|
@ -1279,7 +1279,7 @@ static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node
|
|||
void sun4v_pci_init(struct device_node *dp, char *model_name)
|
||||
{
|
||||
struct pci_controller_info *p;
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
struct property *prop;
|
||||
struct linux_prom64_registers *regs;
|
||||
u32 devhandle;
|
||||
|
@ -1319,13 +1319,13 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
|
|||
if (!p)
|
||||
goto fatal_memory_error;
|
||||
|
||||
iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
|
||||
iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
|
||||
if (!iommu)
|
||||
goto fatal_memory_error;
|
||||
|
||||
p->pbm_A.iommu = iommu;
|
||||
|
||||
iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
|
||||
iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
|
||||
if (!iommu)
|
||||
goto fatal_memory_error;
|
||||
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
/* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
|
||||
* pbm.h: UltraSparc PCI controller software state.
|
||||
/* pbm.h: UltraSparc PCI controller software state.
|
||||
*
|
||||
* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
|
||||
* Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
|
||||
*/
|
||||
|
||||
#ifndef __SPARC64_PBM_H
|
||||
|
@ -30,84 +29,7 @@
|
|||
* PCI bus.
|
||||
*/
|
||||
|
||||
struct pci_controller_info;
|
||||
|
||||
/* This contains the software state necessary to drive a PCI
|
||||
* controller's IOMMU.
|
||||
*/
|
||||
struct pci_iommu {
|
||||
/* This protects the controller's IOMMU and all
|
||||
* streaming buffers underneath.
|
||||
*/
|
||||
spinlock_t lock;
|
||||
|
||||
struct iommu_arena arena;
|
||||
|
||||
/* IOMMU page table, a linear array of ioptes. */
|
||||
iopte_t *page_table; /* The page table itself. */
|
||||
|
||||
/* Base PCI memory space address where IOMMU mappings
|
||||
* begin.
|
||||
*/
|
||||
u32 page_table_map_base;
|
||||
|
||||
/* IOMMU Controller Registers */
|
||||
unsigned long iommu_control; /* IOMMU control register */
|
||||
unsigned long iommu_tsbbase; /* IOMMU page table base register */
|
||||
unsigned long iommu_flush; /* IOMMU page flush register */
|
||||
unsigned long iommu_ctxflush; /* IOMMU context flush register */
|
||||
|
||||
/* This is a register in the PCI controller, which if
|
||||
* read will have no side-effects but will guarantee
|
||||
* completion of all previous writes into IOMMU/STC.
|
||||
*/
|
||||
unsigned long write_complete_reg;
|
||||
|
||||
/* In order to deal with some buggy third-party PCI bridges that
|
||||
* do wrong prefetching, we never mark valid mappings as invalid.
|
||||
* Instead we point them at this dummy page.
|
||||
*/
|
||||
unsigned long dummy_page;
|
||||
unsigned long dummy_page_pa;
|
||||
|
||||
/* CTX allocation. */
|
||||
unsigned long ctx_lowest_free;
|
||||
DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
|
||||
|
||||
/* Here a PCI controller driver describes the areas of
|
||||
* PCI memory space where DMA to/from physical memory
|
||||
* are addressed. Drivers interrogate the PCI layer
|
||||
* if their device has addressing limitations. They
|
||||
* do so via pci_dma_supported, and pass in a mask of
|
||||
* DMA address bits their device can actually drive.
|
||||
*
|
||||
* The test for being usable is:
|
||||
* (device_mask & dma_addr_mask) == dma_addr_mask
|
||||
*/
|
||||
u32 dma_addr_mask;
|
||||
};
|
||||
|
||||
extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
|
||||
|
||||
/* This describes a PCI bus module's streaming buffer. */
|
||||
struct pci_strbuf {
|
||||
int strbuf_enabled; /* Present and using it? */
|
||||
|
||||
/* Streaming Buffer Control Registers */
|
||||
unsigned long strbuf_control; /* STC control register */
|
||||
unsigned long strbuf_pflush; /* STC page flush register */
|
||||
unsigned long strbuf_fsync; /* STC flush synchronization reg */
|
||||
unsigned long strbuf_ctxflush; /* STC context flush register */
|
||||
unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */
|
||||
unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */
|
||||
volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
|
||||
|
||||
/* And this is the actual flush flag area.
|
||||
* We allocate extra because the chips require
|
||||
* a 64-byte aligned area.
|
||||
*/
|
||||
volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
|
||||
};
|
||||
extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
|
||||
|
||||
#define PCI_STC_FLUSHFLAG_INIT(STC) \
|
||||
(*((STC)->strbuf_flushflag) = 0UL)
|
||||
|
@ -120,6 +42,8 @@ struct pci_strbuf {
|
|||
#define PROM_PCIRNG_MAX 64
|
||||
#define PROM_PCIIMAP_MAX 64
|
||||
|
||||
struct pci_controller_info;
|
||||
|
||||
struct pci_pbm_info {
|
||||
/* PCI controller we sit under. */
|
||||
struct pci_controller_info *parent;
|
||||
|
@ -186,10 +110,10 @@ struct pci_pbm_info {
|
|||
#endif /* !(CONFIG_PCI_MSI) */
|
||||
|
||||
/* This PBM's streaming buffer. */
|
||||
struct pci_strbuf stc;
|
||||
struct strbuf stc;
|
||||
|
||||
/* IOMMU state, potentially shared by both PBM segments. */
|
||||
struct pci_iommu *iommu;
|
||||
struct iommu *iommu;
|
||||
|
||||
/* Now things for the actual PCI bus probes. */
|
||||
unsigned int pci_first_busno;
|
||||
|
|
Loading…
Reference in a new issue