From ad4e1a7caf937ad395ced585ca85a7d14395dc80 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:48 +0800 Subject: [PATCH 001/307] gpio: fix wrong checking condition for gpio range If index++ calculates from 0, the checking condition of "while (index++)" fails & it doesn't check any more. It doesn't follow the loop that used at here. Replace it by endless loop at here. Then it keeps parsing "gpio-ranges" property until it ends. Signed-off-by: Haojian Zhuang Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij --- drivers/gpio/gpiolib-of.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index a71a54a3e3f7..5150df6cba08 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -193,7 +193,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) if (!np) return; - do { + for (;; index++) { ret = of_parse_phandle_with_args(np, "gpio-ranges", "#gpio-range-cells", index, &pinspec); if (ret) @@ -222,8 +222,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) if (ret) break; - - } while (index++); + } } #else From a72149e82b65b76d2dae5428a6b211eb43933529 Mon Sep 17 00:00:00 2001 From: Jingoo Han Date: Tue, 26 Feb 2013 11:34:07 +0900 Subject: [PATCH 002/307] pinctrl: core: use devres_release() instead of devres_destroy() devres_release() can simplify the code, because devres_release() will call the destructor for the resource as well as freeing the devres data. Signed-off-by: Jingoo Han Acked-by: Stephen Warren Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index b0de6e7f1fdb..e2d214c5c58f 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -979,9 +979,8 @@ static int devm_pinctrl_match(struct device *dev, void *res, void *data) */ void devm_pinctrl_put(struct pinctrl *p) { - WARN_ON(devres_destroy(p->dev, devm_pinctrl_release, + WARN_ON(devres_release(p->dev, devm_pinctrl_release, devm_pinctrl_match, p)); - pinctrl_put(p); } EXPORT_SYMBOL_GPL(devm_pinctrl_put); From 022ab148d28e8466e45d28552224e3029f1cccd8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 10:25:07 +0100 Subject: [PATCH 003/307] pinctrl: Declare operation structures as const The pinconf, pinctrl and pinmux operation structures hold function pointers that are never modified. Declare them as const. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/devicetree.c | 4 ++-- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 6 +++--- drivers/pinctrl/pinconf.c | 2 +- drivers/pinctrl/pinctrl-abx500.c | 6 +++--- drivers/pinctrl/pinctrl-at91.c | 6 +++--- drivers/pinctrl/pinctrl-bcm2835.c | 6 +++--- drivers/pinctrl/pinctrl-exynos5440.c | 6 +++--- drivers/pinctrl/pinctrl-falcon.c | 2 +- drivers/pinctrl/pinctrl-imx.c | 6 +++--- drivers/pinctrl/pinctrl-lantiq.c | 4 ++-- drivers/pinctrl/pinctrl-mxs.c | 6 +++--- drivers/pinctrl/pinctrl-nomadik.c | 6 +++--- drivers/pinctrl/pinctrl-pxa3xx.c | 4 ++-- drivers/pinctrl/pinctrl-samsung.c | 6 +++--- drivers/pinctrl/pinctrl-single.c | 6 +++--- drivers/pinctrl/pinctrl-sirf.c | 4 ++-- drivers/pinctrl/pinctrl-sunxi.c | 6 +++--- drivers/pinctrl/pinctrl-tegra.c | 6 +++--- drivers/pinctrl/pinctrl-u300.c | 6 +++--- drivers/pinctrl/pinctrl-xway.c | 2 +- drivers/pinctrl/spear/pinctrl-spear.c | 4 ++-- include/linux/pinctrl/pinctrl.h | 6 +++--- 22 files changed, 55 insertions(+), 55 deletions(-) diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index fd40a11ad645..c7b7cb477129 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -41,7 +41,7 @@ static void dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { if (pctldev) { - struct pinctrl_ops *ops = pctldev->desc->pctlops; + const struct pinctrl_ops *ops = pctldev->desc->pctlops; ops->dt_free_map(pctldev, map, num_maps); } else { /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ @@ -122,7 +122,7 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename, { struct device_node *np_pctldev; struct pinctrl_dev *pctldev; - struct pinctrl_ops *ops; + const struct pinctrl_ops *ops; int ret; struct pinctrl_map *map; unsigned num_maps; diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index c689c04a4f52..61149914882d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -263,7 +263,7 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, return; } -static struct pinconf_ops mvebu_pinconf_ops = { +static const struct pinconf_ops mvebu_pinconf_ops = { .pin_config_group_get = mvebu_pinconf_group_get, .pin_config_group_set = mvebu_pinconf_group_set, .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show, @@ -369,7 +369,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, return -ENOTSUPP; } -static struct pinmux_ops mvebu_pinmux_ops = { +static const struct pinmux_ops mvebu_pinmux_ops = { .get_functions_count = mvebu_pinmux_get_funcs_count, .get_function_name = mvebu_pinmux_get_func_name, .get_function_groups = mvebu_pinmux_get_groups, @@ -470,7 +470,7 @@ static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops mvebu_pinctrl_ops = { +static const struct pinctrl_ops mvebu_pinctrl_ops = { .get_groups_count = mvebu_pinctrl_get_groups_count, .get_group_name = mvebu_pinctrl_get_group_name, .get_group_pins = mvebu_pinctrl_get_group_pins, diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index ac8d382a79bb..8aefd28c797e 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -670,7 +670,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) struct pinctrl_maps *maps_node; struct pinctrl_map const *map; struct pinctrl_dev *pctldev = NULL; - struct pinconf_ops *confops = NULL; + const struct pinconf_ops *confops = NULL; int i, j; bool found = false; diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index caecdd373061..169d72c59a7b 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -656,7 +656,7 @@ static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, { } -static struct pinmux_ops abx500_pinmux_ops = { +static const struct pinmux_ops abx500_pinmux_ops = { .get_functions_count = abx500_pmx_get_funcs_cnt, .get_function_name = abx500_pmx_get_func_name, .get_function_groups = abx500_pmx_get_func_groups, @@ -704,7 +704,7 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, chip->base + offset - 1); } -static struct pinctrl_ops abx500_pinctrl_ops = { +static const struct pinctrl_ops abx500_pinctrl_ops = { .get_groups_count = abx500_get_groups_cnt, .get_group_name = abx500_get_group_name, .get_group_pins = abx500_get_group_pins, @@ -778,7 +778,7 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev, return ret; } -static struct pinconf_ops abx500_pinconf_ops = { +static const struct pinconf_ops abx500_pinconf_ops = { .pin_config_get = abx500_pin_config_get, .pin_config_set = abx500_pin_config_set, }; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 75933a6aa828..e50fa5f863e1 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -294,7 +294,7 @@ static void at91_dt_free_map(struct pinctrl_dev *pctldev, { } -static struct pinctrl_ops at91_pctrl_ops = { +static const struct pinctrl_ops at91_pctrl_ops = { .get_groups_count = at91_get_groups_count, .get_group_name = at91_get_group_name, .get_group_pins = at91_get_group_pins, @@ -696,7 +696,7 @@ static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, /* Set the pin to some default state, GPIO is usually default */ } -static struct pinmux_ops at91_pmx_ops = { +static const struct pinmux_ops at91_pmx_ops = { .get_functions_count = at91_pmx_get_funcs_count, .get_function_name = at91_pmx_get_func_name, .get_function_groups = at91_pmx_get_groups, @@ -776,7 +776,7 @@ static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, { } -static struct pinconf_ops at91_pinconf_ops = { +static const struct pinconf_ops at91_pinconf_ops = { .pin_config_get = at91_pinconf_get, .pin_config_set = at91_pinconf_set, .pin_config_dbg_show = at91_pinconf_dbg_show, diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c index 4eb6d2c4e4df..f28d4b08771a 100644 --- a/drivers/pinctrl/pinctrl-bcm2835.c +++ b/drivers/pinctrl/pinctrl-bcm2835.c @@ -795,7 +795,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, return err; } -static struct pinctrl_ops bcm2835_pctl_ops = { +static const struct pinctrl_ops bcm2835_pctl_ops = { .get_groups_count = bcm2835_pctl_get_groups_count, .get_group_name = bcm2835_pctl_get_group_name, .get_group_pins = bcm2835_pctl_get_group_pins, @@ -872,7 +872,7 @@ static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return 0; } -static struct pinmux_ops bcm2835_pmx_ops = { +static const struct pinmux_ops bcm2835_pmx_ops = { .get_functions_count = bcm2835_pmx_get_functions_count, .get_function_name = bcm2835_pmx_get_function_name, .get_function_groups = bcm2835_pmx_get_function_groups, @@ -916,7 +916,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, return 0; } -static struct pinconf_ops bcm2835_pinconf_ops = { +static const struct pinconf_ops bcm2835_pinconf_ops = { .pin_config_get = bcm2835_pinconf_get, .pin_config_set = bcm2835_pinconf_set, }; diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c index 1376eb7305db..169ea3e5f777 100644 --- a/drivers/pinctrl/pinctrl-exynos5440.c +++ b/drivers/pinctrl/pinctrl-exynos5440.c @@ -286,7 +286,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, } /* list of pinctrl callbacks for the pinctrl core */ -static struct pinctrl_ops exynos5440_pctrl_ops = { +static const struct pinctrl_ops exynos5440_pctrl_ops = { .get_groups_count = exynos5440_get_group_count, .get_group_name = exynos5440_get_group_name, .get_group_pins = exynos5440_get_group_pins, @@ -374,7 +374,7 @@ static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, } /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ -static struct pinmux_ops exynos5440_pinmux_ops = { +static const struct pinmux_ops exynos5440_pinmux_ops = { .get_functions_count = exynos5440_get_functions_count, .get_function_name = exynos5440_pinmux_get_fname, .get_function_groups = exynos5440_pinmux_get_groups, @@ -523,7 +523,7 @@ static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev, } /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ -static struct pinconf_ops exynos5440_pinconf_ops = { +static const struct pinconf_ops exynos5440_pinconf_ops = { .pin_config_get = exynos5440_pinconf_get, .pin_config_set = exynos5440_pinconf_set, .pin_config_group_get = exynos5440_pinconf_group_get, diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index af97a1f90007..f9b2a1d4854f 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -353,7 +353,7 @@ static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev, { } -static struct pinconf_ops falcon_pinconf_ops = { +static const struct pinconf_ops falcon_pinconf_ops = { .pin_config_get = falcon_pinconf_get, .pin_config_set = falcon_pinconf_set, .pin_config_group_get = falcon_pinconf_group_get, diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 4cebb9c6c5c5..0ef190449eab 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -207,7 +207,7 @@ static void imx_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops imx_pctrl_ops = { +static const struct pinctrl_ops imx_pctrl_ops = { .get_groups_count = imx_get_groups_count, .get_group_name = imx_get_group_name, .get_group_pins = imx_get_group_pins, @@ -299,7 +299,7 @@ static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static struct pinmux_ops imx_pmx_ops = { +static const struct pinmux_ops imx_pmx_ops = { .get_functions_count = imx_pmx_get_funcs_count, .get_function_name = imx_pmx_get_func_name, .get_function_groups = imx_pmx_get_groups, @@ -397,7 +397,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, } } -static struct pinconf_ops imx_pinconf_ops = { +static const struct pinconf_ops imx_pinconf_ops = { .pin_config_get = imx_pinconf_get, .pin_config_set = imx_pinconf_set, .pin_config_dbg_show = imx_pinconf_dbg_show, diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index a70384611351..615c5002b757 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -169,7 +169,7 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops ltq_pctrl_ops = { +static const struct pinctrl_ops ltq_pctrl_ops = { .get_groups_count = ltq_get_group_count, .get_group_name = ltq_get_group_name, .get_group_pins = ltq_get_group_pins, @@ -311,7 +311,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev, return info->apply_mux(pctrldev, mfp, pin_func); } -static struct pinmux_ops ltq_pmx_ops = { +static const struct pinmux_ops ltq_pmx_ops = { .get_functions_count = ltq_pmx_func_count, .get_function_name = ltq_pmx_func_name, .get_function_groups = ltq_pmx_get_groups, diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c index 23af9f1f9c35..b45c4eb35798 100644 --- a/drivers/pinctrl/pinctrl-mxs.c +++ b/drivers/pinctrl/pinctrl-mxs.c @@ -158,7 +158,7 @@ static void mxs_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops mxs_pinctrl_ops = { +static const struct pinctrl_ops mxs_pinctrl_ops = { .get_groups_count = mxs_get_groups_count, .get_group_name = mxs_get_group_name, .get_group_pins = mxs_get_group_pins, @@ -219,7 +219,7 @@ static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static struct pinmux_ops mxs_pinmux_ops = { +static const struct pinmux_ops mxs_pinmux_ops = { .get_functions_count = mxs_pinctrl_get_funcs_count, .get_function_name = mxs_pinctrl_get_func_name, .get_function_groups = mxs_pinctrl_get_func_groups, @@ -319,7 +319,7 @@ static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "0x%lx", config); } -static struct pinconf_ops mxs_pinconf_ops = { +static const struct pinconf_ops mxs_pinconf_ops = { .pin_config_get = mxs_pinconf_get, .pin_config_set = mxs_pinconf_set, .pin_config_group_get = mxs_pinconf_group_get, diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 36d20293de5c..2328baaa86bf 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -1764,7 +1764,7 @@ int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops nmk_pinctrl_ops = { +static const struct pinctrl_ops nmk_pinctrl_ops = { .get_groups_count = nmk_get_groups_cnt, .get_group_name = nmk_get_group_name, .get_group_pins = nmk_get_group_pins, @@ -1975,7 +1975,7 @@ static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, /* Set the pin to some default state, GPIO is usually default */ } -static struct pinmux_ops nmk_pinmux_ops = { +static const struct pinmux_ops nmk_pinmux_ops = { .get_functions_count = nmk_pmx_get_funcs_cnt, .get_function_name = nmk_pmx_get_func_name, .get_function_groups = nmk_pmx_get_func_groups, @@ -2089,7 +2089,7 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static struct pinconf_ops nmk_pinconf_ops = { +static const struct pinconf_ops nmk_pinconf_ops = { .pin_config_get = nmk_pin_config_get, .pin_config_set = nmk_pin_config_set, }; diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c index 1f49bb02a6af..05e11de1d144 100644 --- a/drivers/pinctrl/pinctrl-pxa3xx.c +++ b/drivers/pinctrl/pinctrl-pxa3xx.c @@ -53,7 +53,7 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev, return 0; } -static struct pinctrl_ops pxa3xx_pctrl_ops = { +static const struct pinctrl_ops pxa3xx_pctrl_ops = { .get_groups_count = pxa3xx_get_groups_count, .get_group_name = pxa3xx_get_group_name, .get_group_pins = pxa3xx_get_group_pins, @@ -161,7 +161,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev, return 0; } -static struct pinmux_ops pxa3xx_pmx_ops = { +static const struct pinmux_ops pxa3xx_pmx_ops = { .get_functions_count = pxa3xx_pmx_get_funcs_count, .get_function_name = pxa3xx_pmx_get_func_name, .get_function_groups = pxa3xx_pmx_get_groups, diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index f206df175656..3475b92b24a4 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -214,7 +214,7 @@ static void samsung_dt_free_map(struct pinctrl_dev *pctldev, } /* list of pinctrl callbacks for the pinctrl core */ -static struct pinctrl_ops samsung_pctrl_ops = { +static const struct pinctrl_ops samsung_pctrl_ops = { .get_groups_count = samsung_get_group_count, .get_group_name = samsung_get_group_name, .get_group_pins = samsung_get_group_pins, @@ -357,7 +357,7 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, } /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ -static struct pinmux_ops samsung_pinmux_ops = { +static const struct pinmux_ops samsung_pinmux_ops = { .get_functions_count = samsung_get_functions_count, .get_function_name = samsung_pinmux_get_fname, .get_function_groups = samsung_pinmux_get_groups, @@ -468,7 +468,7 @@ static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev, } /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ -static struct pinconf_ops samsung_pinconf_ops = { +static const struct pinconf_ops samsung_pinconf_ops = { .pin_config_get = samsung_pinconf_get, .pin_config_set = samsung_pinconf_set, .pin_config_group_get = samsung_pinconf_group_get, diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5c32e880bcb2..0c0e2da9d880 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -270,7 +270,7 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, unsigned *num_maps); -static struct pinctrl_ops pcs_pinctrl_ops = { +static const struct pinctrl_ops pcs_pinctrl_ops = { .get_groups_count = pcs_get_groups_count, .get_group_name = pcs_get_group_name, .get_group_pins = pcs_get_group_pins, @@ -408,7 +408,7 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, return -ENOTSUPP; } -static struct pinmux_ops pcs_pinmux_ops = { +static const struct pinmux_ops pcs_pinmux_ops = { .get_functions_count = pcs_get_functions_count, .get_function_name = pcs_get_function_name, .get_function_groups = pcs_get_function_groups, @@ -451,7 +451,7 @@ static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, { } -static struct pinconf_ops pcs_pinconf_ops = { +static const struct pinconf_ops pcs_pinconf_ops = { .pin_config_get = pcs_pinconf_get, .pin_config_set = pcs_pinconf_set, .pin_config_group_get = pcs_pinconf_group_get, diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c index d02498b30c6e..0990a721758e 100644 --- a/drivers/pinctrl/pinctrl-sirf.c +++ b/drivers/pinctrl/pinctrl-sirf.c @@ -979,7 +979,7 @@ static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops sirfsoc_pctrl_ops = { +static const struct pinctrl_ops sirfsoc_pctrl_ops = { .get_groups_count = sirfsoc_get_groups_count, .get_group_name = sirfsoc_get_group_name, .get_group_pins = sirfsoc_get_group_pins, @@ -1181,7 +1181,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, return 0; } -static struct pinmux_ops sirfsoc_pinmux_ops = { +static const struct pinmux_ops sirfsoc_pinmux_ops = { .enable = sirfsoc_pinmux_enable, .disable = sirfsoc_pinmux_disable, .get_functions_count = sirfsoc_pinmux_get_funcs_count, diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index 80b11e3415bc..46b8f2d4f0a5 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -1029,7 +1029,7 @@ static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops sunxi_pctrl_ops = { +static const struct pinctrl_ops sunxi_pctrl_ops = { .dt_node_to_map = sunxi_pctrl_dt_node_to_map, .dt_free_map = sunxi_pctrl_dt_free_map, .get_groups_count = sunxi_pctrl_get_groups_count, @@ -1098,7 +1098,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, return 0; } -static struct pinconf_ops sunxi_pconf_ops = { +static const struct pinconf_ops sunxi_pconf_ops = { .pin_config_group_get = sunxi_pconf_group_get, .pin_config_group_set = sunxi_pconf_group_set, }; @@ -1204,7 +1204,7 @@ sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return ret; } -static struct pinmux_ops sunxi_pmx_ops = { +static const struct pinmux_ops sunxi_pmx_ops = { .get_functions_count = sunxi_pmx_get_funcs_cnt, .get_function_name = sunxi_pmx_get_func_name, .get_function_groups = sunxi_pmx_get_func_groups, diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index f195d77a3572..2fa9bc6cd7ab 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -316,7 +316,7 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops tegra_pinctrl_ops = { +static const struct pinctrl_ops tegra_pinctrl_ops = { .get_groups_count = tegra_pinctrl_get_groups_count, .get_group_name = tegra_pinctrl_get_group_name, .get_group_pins = tegra_pinctrl_get_group_pins, @@ -401,7 +401,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, pmx_writel(pmx, val, g->mux_bank, g->mux_reg); } -static struct pinmux_ops tegra_pinmux_ops = { +static const struct pinmux_ops tegra_pinmux_ops = { .get_functions_count = tegra_pinctrl_get_funcs_count, .get_function_name = tegra_pinctrl_get_func_name, .get_function_groups = tegra_pinctrl_get_func_groups, @@ -676,7 +676,7 @@ static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, } #endif -static struct pinconf_ops tegra_pinconf_ops = { +static const struct pinconf_ops tegra_pinconf_ops = { .pin_config_get = tegra_pinconf_get, .pin_config_set = tegra_pinconf_set, .pin_config_group_get = tegra_pinconf_group_get, diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 2b5772550836..6a3a7503e6a0 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -860,7 +860,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, " " DRIVER_NAME); } -static struct pinctrl_ops u300_pctrl_ops = { +static const struct pinctrl_ops u300_pctrl_ops = { .get_groups_count = u300_get_groups_count, .get_group_name = u300_get_group_name, .get_group_pins = u300_get_group_pins, @@ -1003,7 +1003,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static struct pinmux_ops u300_pmx_ops = { +static const struct pinmux_ops u300_pmx_ops = { .get_functions_count = u300_pmx_get_funcs_count, .get_function_name = u300_pmx_get_func_name, .get_function_groups = u300_pmx_get_groups, @@ -1046,7 +1046,7 @@ static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static struct pinconf_ops u300_pconf_ops = { +static const struct pinconf_ops u300_pconf_ops = { .is_generic = true, .pin_config_get = u300_pin_config_get, .pin_config_set = u300_pin_config_set, diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index 068224efa6fa..f2977cff8366 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -553,7 +553,7 @@ int xway_pinconf_group_set(struct pinctrl_dev *pctldev, return ret; } -static struct pinconf_ops xway_pinconf_ops = { +static const struct pinconf_ops xway_pinconf_ops = { .pin_config_get = xway_pinconf_get, .pin_config_set = xway_pinconf_set, .pin_config_group_set = xway_pinconf_group_set, diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index 6a7dae70db08..116da0412c4b 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -198,7 +198,7 @@ static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops spear_pinctrl_ops = { +static const struct pinctrl_ops spear_pinctrl_ops = { .get_groups_count = spear_pinctrl_get_groups_cnt, .get_group_name = spear_pinctrl_get_group_name, .get_group_pins = spear_pinctrl_get_group_pins, @@ -340,7 +340,7 @@ static void gpio_disable_free(struct pinctrl_dev *pctldev, gpio_request_endisable(pctldev, range, offset, false); } -static struct pinmux_ops spear_pinmux_ops = { +static const struct pinmux_ops spear_pinmux_ops = { .get_functions_count = spear_pinctrl_get_funcs_count, .get_function_name = spear_pinctrl_get_func_name, .get_function_groups = spear_pinctrl_get_func_groups, diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 778804df293f..2c2a9e8d8578 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -118,9 +118,9 @@ struct pinctrl_desc { const char *name; struct pinctrl_pin_desc const *pins; unsigned int npins; - struct pinctrl_ops *pctlops; - struct pinmux_ops *pmxops; - struct pinconf_ops *confops; + const struct pinctrl_ops *pctlops; + const struct pinmux_ops *pmxops; + const struct pinconf_ops *confops; struct module *owner; }; From e3929714942b242ecb55657e70d51e0eb4c77726 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Sun, 17 Feb 2013 21:58:47 +0800 Subject: [PATCH 004/307] pinctrl: abx500: Add terminating entry for of_device_id table The of_device_id table is supposed to be zero-terminated. Signed-off-by: Axel Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-abx500.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index 169d72c59a7b..e8abc3cf3033 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -834,6 +834,7 @@ static const struct of_device_id abx500_gpio_match[] = { { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, + { } }; static int abx500_gpio_probe(struct platform_device *pdev) From 86853c83e33738397564e9377ceeff94d4bc041c Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:47 +0800 Subject: [PATCH 005/307] gpio: add gpio offset in gpio range cells property Add gpio offset into "gpio-range-cells" property. It's used to support sparse pinctrl range in gpio chip. Signed-off-by: Haojian Zhuang Acked-by: Viresh Kumar Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio.txt | 6 +++--- arch/arm/boot/dts/spear1310.dtsi | 4 ++-- arch/arm/boot/dts/spear1340.dtsi | 4 ++-- arch/arm/boot/dts/spear310.dtsi | 4 ++-- arch/arm/boot/dts/spear320.dtsi | 4 ++-- drivers/gpio/gpiolib-of.c | 15 ++------------- 6 files changed, 13 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index a33628759d36..d933af370697 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example, compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; reg = <0x1460 0x18>; gpio-controller; - gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; + gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; } @@ -107,8 +107,8 @@ where, Next values specify the base pin and number of pins for the range handled by 'qe_pio_e' gpio. In the given example from base pin 20 to - pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled - by this gpio controller. + pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under + pinctrl2 with gpio offset 10 is handled by this gpio controller. The pinctrl node must have "#gpio-range-cells" property to show number of arguments to pass with phandle from gpio controllers node. diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi index 1513c1927cc8..122ae94076c8 100644 --- a/arch/arm/boot/dts/spear1310.dtsi +++ b/arch/arm/boot/dts/spear1310.dtsi @@ -89,7 +89,7 @@ gmac4: eth@5c700000 { pinmux: pinmux@e0700000 { compatible = "st,spear1310-pinmux"; reg = <0xe0700000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; apb { @@ -212,7 +212,7 @@ gpiopinctrl: gpio@d8400000 { interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 246>; + gpio-ranges = <&pinmux 0 0 246>; status = "disabled"; st-plgpio,ngpio = <246>; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index 34da11aa6795..c511c4772efd 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -63,7 +63,7 @@ i2s-rec@b2000000 { pinmux: pinmux@e0700000 { compatible = "st,spear1340-pinmux"; reg = <0xe0700000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; pwm: pwm@e0180000 { @@ -127,7 +127,7 @@ gpiopinctrl: gpio@e2800000 { interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 252>; + gpio-ranges = <&pinmux 0 0 252>; status = "disabled"; st-plgpio,ngpio = <250>; diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index ab45b8c81982..95372080eea6 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi @@ -25,7 +25,7 @@ ahb { pinmux: pinmux@b4000000 { compatible = "st,spear310-pinmux"; reg = <0xb4000000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; fsmc: flash@44000000 { @@ -102,7 +102,7 @@ gpiopinctrl: gpio@b4000000 { interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 102>; + gpio-ranges = <&pinmux 0 0 102>; status = "disabled"; st-plgpio,ngpio = <102>; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index caa5520b1fd4..ffea342aeec9 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -24,7 +24,7 @@ ahb { pinmux: pinmux@b3000000 { compatible = "st,spear320-pinmux"; reg = <0xb3000000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; clcd@90000000 { @@ -130,7 +130,7 @@ gpiopinctrl: gpio@b3000000 { interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 102>; + gpio-ranges = <&pinmux 0 0 102>; status = "disabled"; st-plgpio,ngpio = <102>; diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index a71a54a3e3f7..892040ad0095 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -203,22 +203,11 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) if (!pctldev) break; - /* - * This assumes that the n GPIO pins are consecutive in the - * GPIO number space, and that the pins are also consecutive - * in their local number space. Currently it is not possible - * to add different ranges for one and the same GPIO chip, - * as the code assumes that we have one consecutive range - * on both, mapping 1-to-1. - * - * TODO: make the OF bindings handle multiple sparse ranges - * on the same GPIO chip. - */ ret = gpiochip_add_pin_range(chip, pinctrl_dev_get_devname(pctldev), - 0, /* offset in gpiochip */ pinspec.args[0], - pinspec.args[1]); + pinspec.args[1], + pinspec.args[2]); if (ret) break; From f1f70479e999217ecbf619d71837fc5d77c680fb Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:49 +0800 Subject: [PATCH 006/307] gpio: pl061: support irqdomain Drop the support of irq generic chip. Now support irqdomain instead. Although set_wake() is defined in irq generic chip & it is not really used in pl061 gpio driver. Drop it at the same time. Signed-off-by: Haojian Zhuang Signed-off-by: Linus Walleij --- drivers/gpio/gpio-pl061.c | 108 +++++++++++++++++++++++--------------- 1 file changed, 67 insertions(+), 41 deletions(-) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index b820869ca93c..d1d603585a93 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -51,8 +52,7 @@ struct pl061_gpio { spinlock_t lock; void __iomem *base; - int irq_base; - struct irq_chip_generic *irq_gc; + struct irq_domain *domain; struct gpio_chip gc; #ifdef CONFIG_PM @@ -122,24 +122,20 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset) { struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); - if (chip->irq_base <= 0) - return -EINVAL; - - return chip->irq_base + offset; + return irq_create_mapping(chip->domain, offset); } static int pl061_irq_type(struct irq_data *d, unsigned trigger) { - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - struct pl061_gpio *chip = gc->private; - int offset = d->irq - chip->irq_base; + struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); + int offset = irqd_to_hwirq(d); unsigned long flags; u8 gpiois, gpioibe, gpioiev; if (offset < 0 || offset >= PL061_GPIO_NR) return -EINVAL; - raw_spin_lock_irqsave(&gc->lock, flags); + spin_lock_irqsave(&chip->lock, flags); gpioiev = readb(chip->base + GPIOIEV); @@ -168,7 +164,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger) writeb(gpioiev, chip->base + GPIOIEV); - raw_spin_unlock_irqrestore(&gc->lock, flags); + spin_unlock_irqrestore(&chip->lock, flags); return 0; } @@ -192,31 +188,61 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) chained_irq_exit(irqchip, desc); } -static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base) +static void pl061_irq_mask(struct irq_data *d) { - struct irq_chip_type *ct; + struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); + u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); + u8 gpioie; - chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base, - chip->base, handle_simple_irq); - chip->irq_gc->private = chip; - - ct = chip->irq_gc->chip_types; - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->chip.irq_set_type = pl061_irq_type; - ct->chip.irq_set_wake = irq_gc_set_wake; - ct->regs.mask = GPIOIE; - - irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR), - IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0); + spin_lock(&chip->lock); + gpioie = readb(chip->base + GPIOIE) & ~mask; + writeb(gpioie, chip->base + GPIOIE); + spin_unlock(&chip->lock); } +static void pl061_irq_unmask(struct irq_data *d) +{ + struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); + u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); + u8 gpioie; + + spin_lock(&chip->lock); + gpioie = readb(chip->base + GPIOIE) | mask; + writeb(gpioie, chip->base + GPIOIE); + spin_unlock(&chip->lock); +} + +static struct irq_chip pl061_irqchip = { + .name = "pl061 gpio", + .irq_mask = pl061_irq_mask, + .irq_unmask = pl061_irq_unmask, + .irq_set_type = pl061_irq_type, +}; + +static int pl061_irq_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct pl061_gpio *chip = d->host_data; + + irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq, + "pl061"); + irq_set_chip_data(virq, chip); + irq_set_irq_type(virq, IRQ_TYPE_NONE); + + return 0; +} + +static const struct irq_domain_ops pl061_domain_ops = { + .map = pl061_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; struct pl061_platform_data *pdata = dev->platform_data; struct pl061_gpio *chip; - int ret, irq, i; + int ret, irq, i, irq_base; chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (chip == NULL) @@ -224,22 +250,28 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) if (pdata) { chip->gc.base = pdata->gpio_base; - chip->irq_base = pdata->irq_base; - } else if (adev->dev.of_node) { + irq_base = pdata->irq_base; + if (irq_base <= 0) + return -ENODEV; + } else { chip->gc.base = -1; - chip->irq_base = 0; - } else - return -ENODEV; + irq_base = 0; + } if (!devm_request_mem_region(dev, adev->res.start, - resource_size(&adev->res), "pl061")) + resource_size(&adev->res), "pl061")) return -EBUSY; chip->base = devm_ioremap(dev, adev->res.start, - resource_size(&adev->res)); - if (chip->base == NULL) + resource_size(&adev->res)); + if (!chip->base) return -ENOMEM; + chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR, + irq_base, &pl061_domain_ops, chip); + if (!chip->domain) + return -ENODEV; + spin_lock_init(&chip->lock); chip->gc.direction_input = pl061_direction_input; @@ -259,12 +291,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) /* * irq_chip support */ - - if (chip->irq_base <= 0) - return 0; - - pl061_init_gc(chip, chip->irq_base); - writeb(0, chip->base + GPIOIE); /* disable irqs */ irq = adev->irq[0]; if (irq < 0) From 51e13c2475913d45a3ec546dee647538a9341d6a Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:50 +0800 Subject: [PATCH 007/307] pinctrl: check pinctrl ready for gpio range pinctrl_get_device_gpio_range() only checks whether a certain GPIO pin is in gpio range. But maybe some GPIO pins don't have back-end pinctrl interface, it means that these pins are always configured as GPIO function. For example, gpio159 isn't related to back-end pinctrl device in Hi3620 while other GPIO pins are related to back-end pinctrl device. Append pinctrl_ready_for_gpio_range() that is used to check whether pinctrl device with GPIO range is ready. This function will be called after pinctrl_get_device_gpio_range() fails. If pinctrl device with GPIO range is found, it means that pinctrl device is already launched and a certain GPIO pin just don't have back-end pinctrl interface. Then pinctrl_request_gpio() shouldn't return -EPROBE_DEFER in this case. Signed-off-by: Haojian Zhuang Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index e2d214c5c58f..f8a632dc877b 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "core.h" #include "devicetree.h" #include "pinmux.h" @@ -276,6 +277,39 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio) return NULL; } +/** + * pinctrl_ready_for_gpio_range() - check if other GPIO pins of + * the same GPIO chip are in range + * @gpio: gpio pin to check taken from the global GPIO pin space + * + * This function is complement of pinctrl_match_gpio_range(). If the return + * value of pinctrl_match_gpio_range() is NULL, this function could be used + * to check whether pinctrl device is ready or not. Maybe some GPIO pins + * of the same GPIO chip don't have back-end pinctrl interface. + * If the return value is true, it means that pinctrl device is ready & the + * certain GPIO pin doesn't have back-end pinctrl device. If the return value + * is false, it means that pinctrl device may not be ready. + */ +static bool pinctrl_ready_for_gpio_range(unsigned gpio) +{ + struct pinctrl_dev *pctldev; + struct pinctrl_gpio_range *range = NULL; + struct gpio_chip *chip = gpio_to_chip(gpio); + + /* Loop over the pin controllers */ + list_for_each_entry(pctldev, &pinctrldev_list, node) { + /* Loop over the ranges */ + list_for_each_entry(range, &pctldev->gpio_ranges, node) { + /* Check if any gpio range overlapped with gpio chip */ + if (range->base + range->npins - 1 < chip->base || + range->base > chip->base + chip->ngpio - 1) + continue; + return true; + } + } + return false; +} + /** * pinctrl_get_device_gpio_range() - find device for GPIO range * @gpio: the pin to locate the pin controller for @@ -443,6 +477,8 @@ int pinctrl_request_gpio(unsigned gpio) ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { + if (pinctrl_ready_for_gpio_range(gpio)) + ret = 0; mutex_unlock(&pinctrl_mutex); return ret; } From 39b70ee05199f9bea50641df104aee4dbd913d1d Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:51 +0800 Subject: [PATCH 008/307] gpio: pl061: bind pinctrl by gpio request Add the pl061_gpio_request() to request pinctrl. Create the logic between pl061 gpio driver and pinctrl (pinctrl-single) driver. While a gpio pin is requested, it will request pinctrl driver to set that pin with gpio function mode. So pinctrl driver should append .gpio_request_enable() in pinmux_ops. Signed-off-by: Haojian Zhuang Signed-off-by: Linus Walleij --- drivers/gpio/gpio-pl061.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index d1d603585a93..06ed257c5d31 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -60,6 +61,17 @@ struct pl061_gpio { #endif }; +static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + /* + * Map back to global GPIO space and request muxing, the direction + * parameter does not matter for this controller. + */ + int gpio = chip->base + offset; + + return pinctrl_request_gpio(gpio); +} + static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) { struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); @@ -274,6 +286,7 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&chip->lock); + chip->gc.request = pl061_gpio_request; chip->gc.direction_input = pl061_direction_input; chip->gc.direction_output = pl061_direction_output; chip->gc.get = pl061_get_value; From a1a277eb76b3507df7c41774048a644aa4dfd096 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:52 +0800 Subject: [PATCH 009/307] pinctrl: single: create new gpio function range Since gpio driver could create gpio range in DTS, it could invoke pinctrl_request_gpio(). In the pinctrl-single driver, it needs to configure pins with gpio function mode. A new gpio function range should be created in DTS file in below. pinctrl-single,gpio-range = ; range: gpio-range { #pinctrl-single,gpio-range-cells = <3>; }; The gpio-ranges property is used in gpio driver and the pinctrl-single,gpio-range property is used in pinctrl-single driver. 1. gpio-ranges is used for gpio driver in below. gpio-ranges = gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; 2. gpio driver could get pin offset from gpio-ranges property. pinctrl-single driver could get gpio function mode from gpio_func that is stored in @gpiofuncs list in struct pcs_device. This new pinctrl-single,gpio-range is used as complement for gpio-ranges property in gpio driver. Signed-off-by: Haojian Zhuang Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 73 +++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 0c0e2da9d880..f4bc602cdb08 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -76,6 +76,20 @@ struct pcs_function { struct list_head node; }; +/** + * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function + * @offset: offset base of pins + * @npins: number pins with the same mux value of gpio function + * @gpiofunc: mux value of gpio function + * @node: list node + */ +struct pcs_gpiofunc_range { + unsigned offset; + unsigned npins; + unsigned gpiofunc; + struct list_head node; +}; + /** * struct pcs_data - wrapper for data needed by pinctrl framework * @pa: pindesc array @@ -123,6 +137,7 @@ struct pcs_name { * @ftree: function index radix tree * @pingroups: list of pingroups * @functions: list of functions + * @gpiofuncs: list of gpio functions * @ngroups: number of pingroups * @nfuncs: number of functions * @desc: pin controller descriptor @@ -148,6 +163,7 @@ struct pcs_device { struct radix_tree_root ftree; struct list_head pingroups; struct list_head functions; + struct list_head gpiofuncs; unsigned ngroups; unsigned nfuncs; struct pinctrl_desc desc; @@ -403,9 +419,26 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, } static int pcs_request_gpio(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset) + struct pinctrl_gpio_range *range, unsigned pin) { - return -ENOTSUPP; + struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); + struct pcs_gpiofunc_range *frange = NULL; + struct list_head *pos, *tmp; + int mux_bytes = 0; + unsigned data; + + list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { + frange = list_entry(pos, struct pcs_gpiofunc_range, node); + if (pin >= frange->offset + frange->npins + || pin < frange->offset) + continue; + mux_bytes = pcs->width / BITS_PER_BYTE; + data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; + data |= frange->gpiofunc; + pcs->write(data, pcs->base + pin * mux_bytes); + break; + } + return 0; } static const struct pinmux_ops pcs_pinmux_ops = { @@ -879,6 +912,37 @@ static void pcs_free_resources(struct pcs_device *pcs) static struct of_device_id pcs_of_match[]; +static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) +{ + const char *propname = "pinctrl-single,gpio-range"; + const char *cellname = "#pinctrl-single,gpio-range-cells"; + struct of_phandle_args gpiospec; + struct pcs_gpiofunc_range *range; + int ret, i; + + for (i = 0; ; i++) { + ret = of_parse_phandle_with_args(node, propname, cellname, + i, &gpiospec); + /* Do not treat it as error. Only treat it as end condition. */ + if (ret) { + ret = 0; + break; + } + range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); + if (!range) { + ret = -ENOMEM; + break; + } + range->offset = gpiospec.args[0]; + range->npins = gpiospec.args[1]; + range->gpiofunc = gpiospec.args[2]; + mutex_lock(&pcs->mutex); + list_add_tail(&range->node, &pcs->gpiofuncs); + mutex_unlock(&pcs->mutex); + } + return ret; +} + static int pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -900,6 +964,7 @@ static int pcs_probe(struct platform_device *pdev) mutex_init(&pcs->mutex); INIT_LIST_HEAD(&pcs->pingroups); INIT_LIST_HEAD(&pcs->functions); + INIT_LIST_HEAD(&pcs->gpiofuncs); PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); @@ -975,6 +1040,10 @@ static int pcs_probe(struct platform_device *pdev) goto free; } + ret = pcs_add_gpio_func(np, pcs); + if (ret < 0) + goto free; + dev_info(pcs->dev, "%i pins at pa %p size %u\n", pcs->desc.npins, pcs->base, pcs->size); From 9cfd1724f070ffce27861cb7dcfca6808fd722b8 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:53 +0800 Subject: [PATCH 010/307] pinctrl: generic: dump pin configuration Add the support of dumping pin configuration. Signed-off-by: Haojian Zhuang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 14 ++++++++++++++ drivers/pinctrl/pinconf.h | 8 ++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 06c304ac6f7d..9c436858812c 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -12,6 +12,7 @@ #define pr_fmt(fmt) "generic pinconfig core: " fmt #include +#include #include #include #include @@ -120,4 +121,17 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, } } +void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned long config) +{ + int i; + + for(i = 0; i < ARRAY_SIZE(conf_items); i++) { + if (pinconf_to_config_param(config) != conf_items[i].param) + continue; + seq_printf(s, "%s: 0x%x", conf_items[i].display, + pinconf_to_config_argument(config)); + } +} +EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); #endif diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index e3ed8cb072a5..1f7113e40078 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -98,6 +98,8 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, struct seq_file *s, const char *gname); +void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned long config); #else static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, @@ -114,4 +116,10 @@ static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, return; } +static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned long config) +{ + return; +} #endif From 477ac771dd25d1cacfb832394f5207343508bdb4 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:54 +0800 Subject: [PATCH 011/307] pinctrl: single: set function mask as optional Since Hisilicon's pin controller is divided into two parts. One is the function mux, and the other is pin configuration. These two parts are in the different memory regions. So make pinctrl-single,function-mask as optional property. Then we can define pingroups without valid function mux that is only used for pin configuration. Signed-off-by: Haojian Zhuang Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index f4bc602cdb08..f9596fe26394 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -350,6 +350,9 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); + /* If function mask is null, needn't enable it. */ + if (!pcs->fmask) + return 0; func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) return -EINVAL; @@ -384,6 +387,10 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); + /* If function mask is null, needn't disable it. */ + if (!pcs->fmask) + return; + func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) { dev_err(pcs->dev, "%s could not find function%i\n", @@ -427,6 +434,10 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, int mux_bytes = 0; unsigned data; + /* If function mask is null, return directly. */ + if (!pcs->fmask) + return -ENOTSUPP; + list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { frange = list_entry(pos, struct pcs_gpiofunc_range, node); if (pin >= frange->offset + frange->npins @@ -969,10 +980,17 @@ static int pcs_probe(struct platform_device *pdev) PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); - PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask, - "function register mask not specified\n"); - pcs->fshift = ffs(pcs->fmask) - 1; - pcs->fmax = pcs->fmask >> pcs->fshift; + ret = of_property_read_u32(np, "pinctrl-single,function-mask", + &pcs->fmask); + if (!ret) { + pcs->fshift = ffs(pcs->fmask) - 1; + pcs->fmax = pcs->fmask >> pcs->fshift; + } else { + /* If mask property doesn't exist, function mux is invalid. */ + pcs->fmask = 0; + pcs->fshift = 0; + pcs->fmax = 0; + } ret = of_property_read_u32(np, "pinctrl-single,function-off", &pcs->foff); From 9dddb4df90d136429b6d6ddefceb49a9b93f6cd1 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:55 +0800 Subject: [PATCH 012/307] pinctrl: single: support generic pinconf Support the operation of generic pinconf. The supported config arguments are INPUT_SCHMITT, INPUT_SCHMITT_ENABLE, DRIVE_STRENGHT, BIAS_DISABLE, BIAS_PULLUP, BIAS_PULLDOWN, SLEW_RATE. Signed-off-by: Haojian Zhuang Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/pinctrl-single.c | 408 ++++++++++++++++++++++++++++++- 2 files changed, 402 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 34f51d2d90d2..5a690ce6d60d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -166,6 +166,7 @@ config PINCTRL_SINGLE depends on OF select PINMUX select PINCONF + select GENERIC_PINCONF help This selects the device tree based generic pinctrl driver. diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index f9596fe26394..4cdcf8582764 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -22,8 +22,10 @@ #include #include +#include #include "core.h" +#include "pinconf.h" #define DRIVER_NAME "pinctrl-single" #define PCS_MUX_PINS_NAME "pinctrl-single,pins" @@ -58,6 +60,33 @@ struct pcs_func_vals { unsigned mask; }; +/** + * struct pcs_conf_vals - pinconf parameter, pinconf register offset + * and value, enable, disable, mask + * @param: config parameter + * @val: user input bits in the pinconf register + * @enable: enable bits in the pinconf register + * @disable: disable bits in the pinconf register + * @mask: mask bits in the register value + */ +struct pcs_conf_vals { + enum pin_config_param param; + unsigned val; + unsigned enable; + unsigned disable; + unsigned mask; +}; + +/** + * struct pcs_conf_type - pinconf property name, pinconf param pair + * @name: property name in DTS file + * @param: config parameter + */ +struct pcs_conf_type { + const char *name; + enum pin_config_param param; +}; + /** * struct pcs_function - pinctrl function * @name: pinctrl function name @@ -73,6 +102,8 @@ struct pcs_function { unsigned nvals; const char **pgnames; int npgnames; + struct pcs_conf_vals *conf; + int nconfs; struct list_head node; }; @@ -131,6 +162,7 @@ struct pcs_name { * @fshift: function register shift * @foff: value to turn mux off * @fmax: max number of functions in fmask + * @is_pinconf: whether supports pinconf * @names: array of register names for pins * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree @@ -157,6 +189,7 @@ struct pcs_device { unsigned foff; unsigned fmax; bool bits_per_mux; + bool is_pinconf; struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; @@ -171,6 +204,16 @@ struct pcs_device { void (*write)(unsigned val, void __iomem *reg); }; +static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config); +static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long config); + +static enum pin_config_param pcs_bias[] = { + PIN_CONFIG_BIAS_PULL_DOWN, + PIN_CONFIG_BIAS_PULL_UP, +}; + /* * REVISIT: Reads and writes could eventually use regmap or something * generic. But at least on omaps, some mux registers are performance @@ -342,6 +385,28 @@ static int pcs_get_function_groups(struct pinctrl_dev *pctldev, return 0; } +static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, + struct pcs_function **func) +{ + struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); + struct pin_desc *pdesc = pin_desc_get(pctldev, pin); + const struct pinctrl_setting_mux *setting; + unsigned fselector; + + /* If pin is not described in DTS & enabled, mux_setting is NULL. */ + setting = pdesc->mux_setting; + if (!setting) + return -ENOTSUPP; + fselector = setting->func; + *func = radix_tree_lookup(&pcs->ftree, fselector); + if (!(*func)) { + dev_err(pcs->dev, "%s could not find function%i\n", + __func__, fselector); + return -ENOTSUPP; + } + return 0; +} + static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, unsigned group) { @@ -461,32 +526,191 @@ static const struct pinmux_ops pcs_pinmux_ops = { .gpio_request_enable = pcs_request_gpio, }; +/* Clear BIAS value */ +static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) +{ + unsigned long config; + int i; + for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { + config = pinconf_to_config_packed(pcs_bias[i], 0); + pcs_pinconf_set(pctldev, pin, config); + } +} + +/* + * Check whether PIN_CONFIG_BIAS_DISABLE is valid. + * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. + */ +static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) +{ + unsigned long config; + int i; + + for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { + config = pinconf_to_config_packed(pcs_bias[i], 0); + if (!pcs_pinconf_get(pctldev, pin, &config)) + goto out; + } + return true; +out: + return false; +} + static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { + struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); + struct pcs_function *func; + enum pin_config_param param; + unsigned offset = 0, data = 0, i, j, ret; + + ret = pcs_get_function(pctldev, pin, &func); + if (ret) + return ret; + + for (i = 0; i < func->nconfs; i++) { + param = pinconf_to_config_param(*config); + if (param == PIN_CONFIG_BIAS_DISABLE) { + if (pcs_pinconf_bias_disable(pctldev, pin)) { + *config = 0; + return 0; + } else { + return -ENOTSUPP; + } + } else if (param != func->conf[i].param) { + continue; + } + + offset = pin * (pcs->width / BITS_PER_BYTE); + data = pcs->read(pcs->base + offset) & func->conf[i].mask; + switch (func->conf[i].param) { + /* 4 parameters */ + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if ((data != func->conf[i].enable) || + (data == func->conf[i].disable)) + return -ENOTSUPP; + *config = 0; + break; + /* 2 parameters */ + case PIN_CONFIG_INPUT_SCHMITT: + for (j = 0; j < func->nconfs; j++) { + switch (func->conf[j].param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (data != func->conf[j].enable) + return -ENOTSUPP; + break; + default: + break; + } + } + *config = data; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + case PIN_CONFIG_SLEW_RATE: + default: + *config = data; + break; + } + return 0; + } return -ENOTSUPP; } static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long config) { + struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); + struct pcs_function *func; + unsigned offset = 0, shift = 0, arg = 0, i, data, ret; + u16 argument; + + ret = pcs_get_function(pctldev, pin, &func); + if (ret) + return ret; + + for (i = 0; i < func->nconfs; i++) { + if (pinconf_to_config_param(config) == func->conf[i].param) { + offset = pin * (pcs->width / BITS_PER_BYTE); + data = pcs->read(pcs->base + offset); + argument = pinconf_to_config_argument(config); + switch (func->conf[i].param) { + /* 2 parameters */ + case PIN_CONFIG_INPUT_SCHMITT: + case PIN_CONFIG_DRIVE_STRENGTH: + case PIN_CONFIG_SLEW_RATE: + shift = ffs(func->conf[i].mask) - 1; + arg = pinconf_to_config_argument(config); + data &= ~func->conf[i].mask; + data |= (arg << shift) & func->conf[i].mask; + break; + /* 4 parameters */ + case PIN_CONFIG_BIAS_DISABLE: + pcs_pinconf_clear_bias(pctldev, pin); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + if (argument) + pcs_pinconf_clear_bias(pctldev, pin); + /* fall through */ + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + data &= ~func->conf[i].mask; + if (argument) + data |= func->conf[i].enable; + else + data |= func->conf[i].disable; + break; + default: + return -ENOTSUPP; + } + pcs->write(data, pcs->base + offset); + return 0; + } + } return -ENOTSUPP; } static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned group, unsigned long *config) { - return -ENOTSUPP; + const unsigned *pins; + unsigned npins, old = 0; + int i, ret; + + ret = pcs_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + for (i = 0; i < npins; i++) { + if (pcs_pinconf_get(pctldev, pins[i], config)) + return -ENOTSUPP; + /* configs do not match between two pins */ + if (i && (old != *config)) + return -ENOTSUPP; + old = *config; + } + return 0; } static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, unsigned long config) { - return -ENOTSUPP; + const unsigned *pins; + unsigned npins; + int i, ret; + + ret = pcs_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + for (i = 0; i < npins; i++) { + if (pcs_pinconf_set(pctldev, pins[i], config)) + return -ENOTSUPP; + } + return 0; } static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned offset) + struct seq_file *s, unsigned pin) { } @@ -495,6 +719,13 @@ static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, { } +static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned long config) +{ + pinconf_generic_dump_config(pctldev, s, config); +} + static const struct pinconf_ops pcs_pinconf_ops = { .pin_config_get = pcs_pinconf_get, .pin_config_set = pcs_pinconf_set, @@ -502,6 +733,7 @@ static const struct pinconf_ops pcs_pinconf_ops = { .pin_config_group_set = pcs_pinconf_group_set, .pin_config_dbg_show = pcs_pinconf_dbg_show, .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, + .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, }; /** @@ -692,11 +924,157 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) return index; } +/* + * check whether data matches enable bits or disable bits + * Return value: 1 for matching enable bits, 0 for matching disable bits, + * and negative value for matching failure. + */ +static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) +{ + int ret = -EINVAL; + + if (data == enable) + ret = 1; + else if (data == disable) + ret = 0; + return ret; +} + +static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, + unsigned value, unsigned enable, unsigned disable, + unsigned mask) +{ + (*conf)->param = param; + (*conf)->val = value; + (*conf)->enable = enable; + (*conf)->disable = disable; + (*conf)->mask = mask; + (*conf)++; +} + +static void add_setting(unsigned long **setting, enum pin_config_param param, + unsigned arg) +{ + **setting = pinconf_to_config_packed(param, arg); + (*setting)++; +} + +/* add pinconf setting with 2 parameters */ +static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, + const char *name, enum pin_config_param param, + struct pcs_conf_vals **conf, unsigned long **settings) +{ + unsigned value[2]; + int ret; + + ret = of_property_read_u32_array(np, name, value, 2); + if (ret) + return; + /* set value & mask */ + value[0] &= value[1]; + /* skip enable & disable */ + add_config(conf, param, value[0], 0, 0, value[1]); + add_setting(settings, param, value[0]); +} + +/* add pinconf setting with 4 parameters */ +static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, + const char *name, enum pin_config_param param, + struct pcs_conf_vals **conf, unsigned long **settings) +{ + unsigned value[4]; + int ret; + + /* value to set, enable, disable, mask */ + ret = of_property_read_u32_array(np, name, value, 4); + if (ret) + return; + if (!value[3]) { + dev_err(pcs->dev, "mask field of the property can't be 0\n"); + return; + } + value[0] &= value[3]; + value[1] &= value[3]; + value[2] &= value[3]; + ret = pcs_config_match(value[0], value[1], value[2]); + if (ret < 0) + dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); + add_config(conf, param, value[0], value[1], value[2], value[3]); + add_setting(settings, param, ret); +} + +static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, + struct pcs_function *func, + struct pinctrl_map **map) + +{ + struct pinctrl_map *m = *map; + int i = 0, nconfs = 0; + unsigned long *settings = NULL, *s = NULL; + struct pcs_conf_vals *conf = NULL; + struct pcs_conf_type prop2[] = { + { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, + { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, + { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, + }; + struct pcs_conf_type prop4[] = { + { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, + { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, + { "pinctrl-single,input-schmitt-enable", + PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, + }; + + /* If pinconf isn't supported, don't parse properties in below. */ + if (!pcs->is_pinconf) + return 0; + + /* cacluate how much properties are supported in current node */ + for (i = 0; i < ARRAY_SIZE(prop2); i++) { + if (of_find_property(np, prop2[i].name, NULL)) + nconfs++; + } + for (i = 0; i < ARRAY_SIZE(prop4); i++) { + if (of_find_property(np, prop4[i].name, NULL)) + nconfs++; + } + if (!nconfs) + return 0; + + func->conf = devm_kzalloc(pcs->dev, + sizeof(struct pcs_conf_vals) * nconfs, + GFP_KERNEL); + if (!func->conf) + return -ENOMEM; + func->nconfs = nconfs; + conf = &(func->conf[0]); + m++; + settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs, + GFP_KERNEL); + if (!settings) + return -ENOMEM; + s = &settings[0]; + + for (i = 0; i < ARRAY_SIZE(prop2); i++) + pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, + &conf, &s); + for (i = 0; i < ARRAY_SIZE(prop4); i++) + pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, + &conf, &s); + m->type = PIN_MAP_TYPE_CONFIGS_GROUP; + m->data.configs.group_or_pin = np->name; + m->data.configs.configs = settings; + m->data.configs.num_configs = nconfs; + return 0; +} + +static void pcs_free_pingroups(struct pcs_device *pcs); + /** * smux_parse_one_pinctrl_entry() - parses a device tree mux entry * @pcs: pinctrl driver instance * @np: device node of the mux entry * @map: map entry + * @num_maps: number of map * @pgnames: pingroup names * * Note that this binding currently supports only sets of one register + value. @@ -713,6 +1091,7 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, struct device_node *np, struct pinctrl_map **map, + unsigned *num_maps, const char **pgnames) { struct pcs_func_vals *vals; @@ -785,8 +1164,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, (*map)->data.mux.group = np->name; (*map)->data.mux.function = np->name; + if (pcs->is_pinconf) { + if (pcs_parse_pinconf(pcs, np, function, map)) + goto free_pingroups; + *num_maps = 2; + } else { + *num_maps = 1; + } return 0; +free_pingroups: + pcs_free_pingroups(pcs); + *num_maps = 1; free_function: pcs_remove_function(pcs, function); @@ -815,7 +1204,8 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, pcs = pinctrl_dev_get_drvdata(pctldev); - *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL); + /* create 2 maps. One is for pinmux, and the other is for pinconf. */ + *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL); if (!*map) return -ENOMEM; @@ -827,13 +1217,13 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, goto free_map; } - ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames); + ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, + pgnames); if (ret < 0) { dev_err(pcs->dev, "no pins entries for %s\n", np_config->name); goto free_pgnames; } - *num_maps = 1; return 0; @@ -976,6 +1366,7 @@ static int pcs_probe(struct platform_device *pdev) INIT_LIST_HEAD(&pcs->pingroups); INIT_LIST_HEAD(&pcs->functions); INIT_LIST_HEAD(&pcs->gpiofuncs); + pcs->is_pinconf = match->data; PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); @@ -1046,6 +1437,8 @@ static int pcs_probe(struct platform_device *pdev) pcs->desc.pmxops = &pcs_pinmux_ops; pcs->desc.confops = &pcs_pinconf_ops; pcs->desc.owner = THIS_MODULE; + if (match->data) + pcs_pinconf_ops.is_generic = true; ret = pcs_allocate_pin_table(pcs); if (ret < 0) @@ -1086,7 +1479,8 @@ static int pcs_remove(struct platform_device *pdev) } static struct of_device_id pcs_of_match[] = { - { .compatible = DRIVER_NAME, }, + { .compatible = "pinctrl-single", .data = (void *)false }, + { .compatible = "pinconf-single", .data = (void *)true }, { }, }; MODULE_DEVICE_TABLE(of, pcs_of_match); From 32378ab781e3e5da6e25c51e452a43e21fbabb3a Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 17 Feb 2013 19:42:56 +0800 Subject: [PATCH 013/307] document: devicetree: bind pinconf with pin single Add comments with pinconf & gpio range in the document of pinctrl-single. Signed-off-by: Haojian Zhuang Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-single.txt | 107 +++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 2c81e45f1374..fa1746b639b9 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -1,7 +1,9 @@ One-register-per-pin type device tree based pinctrl driver Required properties: -- compatible : "pinctrl-single" +- compatible : "pinctrl-single" or "pinconf-single". + "pinctrl-single" means that pinconf isn't supported. + "pinconf-single" means that generic pinconf is supported. - reg : offset and length of the register set for the mux registers @@ -14,9 +16,61 @@ Optional properties: - pinctrl-single,function-off : function off mode for disabled state if available and same for all registers; if not specified, disabling of pin functions is ignored + - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin +- pinctrl-single,drive-strength : array of value that are used to configure + drive strength in the pinmux register. They're value of drive strength + current and drive strength mask. + + /* drive strength current, mask */ + pinctrl-single,power-source = <0x30 0xf0>; + +- pinctrl-single,bias-pullup : array of value that are used to configure the + input bias pullup in the pinmux register. + + /* input, enabled pullup bits, disabled pullup bits, mask */ + pinctrl-single,bias-pullup = <0 1 0 1>; + +- pinctrl-single,bias-pulldown : array of value that are used to configure the + input bias pulldown in the pinmux register. + + /* input, enabled pulldown bits, disabled pulldown bits, mask */ + pinctrl-single,bias-pulldown = <2 2 0 2>; + + * Two bits to control input bias pullup and pulldown: User should use + pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means + pullup, and the other one bit means pulldown. + * Three bits to control input bias enable, pullup and pulldown. User should + use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias + enable bit should be included in pullup or pulldown bits. + * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as + pinctrl-single,bias-disable. Because pinctrl single driver could implement + it by calling pulldown, pullup disabled. + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. In some silicons, there're two input + schmitt value (rising-edge & falling-edge) in the pinmux register. + + /* input schmitt value, mask */ + pinctrl-single,input-schmitt = <0x30 0x70>; + +- pinctrl-single,input-schmitt-enable : array of value that are used to + configure input schmitt enable or disable in the pinmux register. + + /* input, enable bits, disable bits, mask */ + pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; + +- pinctrl-single,gpio-range : list of value that are used to configure a GPIO + range. They're value of subnode phandle, pin base in pinctrl device, pin + number in this range, GPIO function value of this GPIO range. + The number of parameters is depend on #pinctrl-single,gpio-range-cells + property. + + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>; + This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. @@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. + +Optional sub-node: In case some pins could be configured as GPIO in the pinmux +register, those pins could be defined as a GPIO range. This sub-node is required +by pinctrl-single,gpio-range property. + +Required properties in sub-node: +- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in + pinctrl-single,gpio-range property. + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + Example: /* SoC common file */ @@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 { pinctrl-single,function-mask = <0x5F>; }; +/* third controller instance for pins in gpio domain */ +pmx_gpio: pinmux@d401e000 { + compatible = "pinconf-single"; + reg = <0xd401e000 0x0330>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + /* sparse GPIO range could be supported */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 + &range 12 1 0 &range 13 29 1 + &range 43 1 0 &range 44 49 1 + &range 94 1 1 &range 96 2 1>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; +}; + + /* board specific .dts file */ &pmx_core { @@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 { >; }; + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x208 0 /* UART0_RXD (IOCFG138) */ + 0x20c 0 /* UART0_TXD (IOCFG139) */ + >; + pinctrl-single,bias-pulldown = <0 2 2>; + pinctrl-single,bias-pullup = <0 1 1>; + }; + /* map uart2 pins */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < @@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 { }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; From a7bbdd7f8065b97108830662b31c18fc67449c87 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Mon, 4 Mar 2013 13:47:39 +0800 Subject: [PATCH 014/307] pinctrl: single: Fix build error If pcs->is_pinconf is false, it means does not support pinconf. If pcs->is_pinconf is true, is_generic flag is always true. This patch fixes below build error: CC [M] drivers/pinctrl/pinctrl-single.o drivers/pinctrl/pinctrl-single.c: In function 'pcs_probe': drivers/pinctrl/pinctrl-single.c:1441:3: error: assignment of member 'is_generic' in read-only object make[2]: *** [drivers/pinctrl/pinctrl-single.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Signed-off-by: Axel Lin Reviewed-by: Haojian Zhuang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 4cdcf8582764..e35dabd3135d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -734,6 +734,7 @@ static const struct pinconf_ops pcs_pinconf_ops = { .pin_config_dbg_show = pcs_pinconf_dbg_show, .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, + .is_generic = true, }; /** @@ -1435,10 +1436,9 @@ static int pcs_probe(struct platform_device *pdev) pcs->desc.name = DRIVER_NAME; pcs->desc.pctlops = &pcs_pinctrl_ops; pcs->desc.pmxops = &pcs_pinmux_ops; - pcs->desc.confops = &pcs_pinconf_ops; + if (pcs->is_pinconf) + pcs->desc.confops = &pcs_pinconf_ops; pcs->desc.owner = THIS_MODULE; - if (match->data) - pcs_pinconf_ops.is_generic = true; ret = pcs_allocate_pin_table(pcs); if (ret < 0) From b5f50bf923edfb1ab1dc3620db90989d5a9dafa5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 6 Mar 2013 16:12:44 +0100 Subject: [PATCH 015/307] pinctrl: sunxi: Add Allwinner A10 pin functions The initial driver contained only a limited set of pins functions because we lacked of documentation on it. Now that we have such documentation, finish to fill the array. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sunxi.c | 733 +++++++++++++++++++++++++------- 1 file changed, 571 insertions(+), 162 deletions(-) diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index 46b8f2d4f0a5..74f6d59790fe 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -30,482 +30,856 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x4, "uart2")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x4, "uart2")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */ + SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */ + SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */ + SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */ + SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */ + SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */ SUNXI_FUNCTION(0x4, "uart1")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */ SUNXI_FUNCTION(0x4, "uart1")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "uart6"), /* TX */ SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "uart6"), /* RX */ SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */ + SUNXI_FUNCTION(0x3, "can"), /* TX */ SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */ + SUNXI_FUNCTION(0x3, "can"), /* RX */ SUNXI_FUNCTION(0x4, "uart1")), /* RING */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ + SUNXI_FUNCTION(0x3, "ac97")), /* DO */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION(0x3, "ac97")), /* DI */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0")), /* TX */ + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "ir1")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0")), /* RX */ + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "ir1")), /* RX */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "sim")), /* DET */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "sim")), /* RST */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SDA */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0")), /* CK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ SUNXI_FUNCTION(0x4, "uart0")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ SUNXI_FUNCTION(0x4, "uart0")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi1"), /* CK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ + SUNXI_FUNCTION(0x4, "uart5"), /* TX */ + SUNXI_FUNCTION(0x5, "ms"), /* BS */ + SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ + SUNXI_FUNCTION(0x4, "uart5"), /* RX */ + SUNXI_FUNCTION(0x5, "ms"), /* CLK */ + SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ + SUNXI_FUNCTION(0x5, "ms"), /* D0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ + SUNXI_FUNCTION(0x5, "ms"), /* D1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ + SUNXI_FUNCTION(0x5, "ms"), /* D2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ + SUNXI_FUNCTION(0x5, "ms"), /* D3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x5, "sim"), /* RST */ + SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ + SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ + SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ + SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ + SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ + SUNXI_FUNCTION(0x5, "sim"), /* SCK */ + SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ + SUNXI_FUNCTION(0x5, "sim"), /* SDA */ + SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ + SUNXI_FUNCTION(0x4, "can"), /* TX */ + SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ + SUNXI_FUNCTION(0x4, "can"), /* RX */ + SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ + SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, SUNXI_FUNCTION(0x0, "gpio_in"), @@ -518,61 +892,96 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart5")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart5")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart6")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart6")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ + SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart2")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ }; static const struct sunxi_desc_pin sun5i_a13_pins[] = { From ee341a99de7386434a0d5cf4bc4329c3ab972a13 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 6 Mar 2013 16:12:45 +0100 Subject: [PATCH 016/307] pinctrl: sunxi: Add Allwinner A13 pin functions The initial driver contained only a limited set of pins functions because we lacked of documentation on it. Now that we have such documentation, finish to fill the array. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sunxi.c | 239 ++++++++++++++++++++++---------- 1 file changed, 169 insertions(+), 70 deletions(-) diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index 74f6d59790fe..cb491d6ba601 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -988,216 +988,305 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* RX */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ + SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ + SUNXI_FUNCTION(0x4, "spi2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ SUNXI_FUNCTION(0x4, "uart1")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ SUNXI_FUNCTION(0x4, "uart1")), /* RX */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, SUNXI_FUNCTION(0x0, "gpio_in"), @@ -1211,24 +1300,34 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ SUNXI_FUNCTION(0x4, "uart1")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ SUNXI_FUNCTION(0x4, "uart1")), /* RX */ - /* Hole */ +/* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart3")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ }; static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { From 34e12121f9f46dbeda1017cac4615c96ffe16c6d Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:44:48 +0900 Subject: [PATCH 017/307] ARM: shmobile: Remove unused headers from hotplug.c This file has no SoC-specific references in it, and fortunately it is still independent of OF so there is no real reason to drag in these headers. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/hotplug.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c index a1524e3367b0..efd0b36a4175 100644 --- a/arch/arm/mach-shmobile/hotplug.c +++ b/arch/arm/mach-shmobile/hotplug.c @@ -14,12 +14,8 @@ #include #include #include -#include #include -#include -#include #include -#include static cpumask_t dead_cpus; From d62242d7f63d6c874f783d8a691534080df1cb59 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:44:57 +0900 Subject: [PATCH 018/307] ARM: shmobile: Remove partial CPU Hotplug from EMEV2 Remove partial CPU hotplug support from EMEV2 SMP code. The upstream EMEV2 SMP support code has no CPU shutdown or reset ability so we cannot reboot the secondary CPU cores. Regular SMP operation is however still working as expected. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 953eb1f9388d..72620b1f87c8 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -62,29 +62,6 @@ static unsigned int __init emev2_get_core_count(void) return scu_base ? scu_get_core_count(scu_base) : 1; } -static int emev2_platform_cpu_kill(unsigned int cpu) -{ - return 0; /* not supported yet */ -} - -static int __maybe_unused emev2_cpu_kill(unsigned int cpu) -{ - int k; - - /* this function is running on another CPU than the offline target, - * here we need wait for shutdown code in platform_cpu_die() to - * finish before asking SoC-specific code to power off the CPU core. - */ - for (k = 0; k < 1000; k++) { - if (shmobile_cpu_is_dead(cpu)) - return emev2_platform_cpu_kill(cpu); - mdelay(1); - } - - return 0; -} - - static void __cpuinit emev2_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -126,9 +103,4 @@ struct smp_operations emev2_smp_ops __initdata = { .smp_prepare_cpus = emev2_smp_prepare_cpus, .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_kill = emev2_cpu_kill, - .cpu_die = shmobile_cpu_die, - .cpu_disable = shmobile_cpu_disable, -#endif }; From da252b8ee542e95d35374b1d31006f8fe5d59f6a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:06 +0900 Subject: [PATCH 019/307] ARM: shmobile: Move EMEV2 CPU boot vector setup code Move the boot vector setup code for the EMEV2 SoC to match the sh73a0 and r8a7779 implementations. With this in place all SoC specific SMP implementations for mach-shmobile uses the ->smp_prepare_cpus() callback to setup the boot vector. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 72620b1f87c8..64278215adaa 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -74,9 +74,6 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * /* enable cache coherency */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); - /* Tell ROM loader about our vector (in headsmp.S) */ - emev2_set_boot_vector(__pa(shmobile_secondary_vector)); - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); return 0; } @@ -87,6 +84,9 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); + /* Tell ROM loader about our vector (in headsmp.S) */ + emev2_set_boot_vector(__pa(shmobile_secondary_vector)); + /* enable cache coherency on CPU0 */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); } From f313ae4e98f2c0825a5a808e4b822214836b5085 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:16 +0900 Subject: [PATCH 020/307] ARM: shmobile: Remove sh73a0_get_core_count() Reduce the number of lines of code in smp-sh73a0.c by getting rid of the sh73a0_get_core_count() function. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index acb46a94ccdf..81c0f4ba1846 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -52,13 +52,6 @@ void __init sh73a0_register_twd(void) } #endif -static unsigned int __init sh73a0_get_core_count(void) -{ - void __iomem *scu_base = scu_base_addr(); - - return scu_get_core_count(scu_base); -} - static void __cpuinit sh73a0_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -90,7 +83,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) static void __init sh73a0_smp_init_cpus(void) { - unsigned int ncores = sh73a0_get_core_count(); + unsigned int ncores = scu_get_core_count(scu_base_addr()); shmobile_smp_init_cpus(ncores); } From 0ae56a951de0efbf36a51de5b2e91db10425c771 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:25 +0900 Subject: [PATCH 021/307] ARM: shmobile: Remove r8a7779_get_core_count() Reduce the number of lines of code in smp-r8a7779.c by getting rid of the r8a7779_get_core_count() function. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 3a4acf23edcf..f46b51658c3a 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -87,13 +87,6 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) __raw_writel(tmp, scu_base + 8); } -static unsigned int __init r8a7779_get_core_count(void) -{ - void __iomem *scu_base = scu_base_addr(); - - return scu_get_core_count(scu_base); -} - static int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; @@ -178,7 +171,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) static void __init r8a7779_smp_init_cpus(void) { - unsigned int ncores = r8a7779_get_core_count(); + unsigned int ncores = scu_get_core_count(scu_base_addr()); shmobile_smp_init_cpus(ncores); } From 2f747dbab424396b797d8abfb5d54c5e19003885 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:34 +0900 Subject: [PATCH 022/307] ARM: shmobile: Remove emev2_get_core_count() Reduce the number of lines of code in smp-emev2.c by getting rid of the emev2_get_core_count() function. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 64278215adaa..4ede41339a70 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -50,18 +50,6 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) } -static unsigned int __init emev2_get_core_count(void) -{ - if (!scu_base) { - scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); - emev2_clock_init(); /* need ioremapped SMU */ - } - - WARN_ON_ONCE(!scu_base); - - return scu_base ? scu_get_core_count(scu_base) : 1; -} - static void __cpuinit emev2_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -93,7 +81,14 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) static void __init emev2_smp_init_cpus(void) { - unsigned int ncores = emev2_get_core_count(); + unsigned int ncores; + + if (!scu_base) { + scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + emev2_clock_init(); /* need ioremapped SMU */ + } + + ncores = scu_base ? scu_get_core_count(scu_base) : 1; shmobile_smp_init_cpus(ncores); } From df2ddd7b9b781f0aee7fc90e6bed21e62ebf7564 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 8 Feb 2013 19:38:25 +0100 Subject: [PATCH 023/307] ARM: shmobile: add MMCIF and SDHI DT clock aliases to sh73a0 and r8a7740 Add clock lookup entries for SDHI and MMCIF device names, for the FDT case. Signed-off-by: Guennadi Liakhovetski Acked-by: Laurent Pinchart Acked-by: Linus Walleij [horms+renesas@verge.net.au: resolved trivial conflict in clock-r8a7740.c] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 4 ++++ arch/arm/mach-shmobile/clock-sh73a0.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 19ce885a3b43..1a9b9a29442a 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -611,11 +611,15 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* ICK */ CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index afa5423a0f93..5fa106b61149 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ + CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ + CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ From c58a1545e39ed1ff54dd2c167d3d25ae62c0dbd3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 29 Jan 2013 14:21:46 +0900 Subject: [PATCH 024/307] ARM: mach-shmobile: r8a7779: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the r8a7779 SoC to be initialised using a flattened device tree blob. Signed-off-by: Simon Horman --- v3 * Fix copy-paste error and use unique reg values for each CPU v2 As suggested by Mark Rutland * Add reg and device_type to cpus * Remove #address-cells from gic --- arch/arm/boot/dts/r8a7779.dtsi | 50 ++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/intc-r8a7779.c | 27 ++++++++--- 3 files changed, 72 insertions(+), 6 deletions(-) create mode 100644 arch/arm/boot/dts/r8a7779.dtsi diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi new file mode 100644 index 000000000000..8c6d52cee6c6 --- /dev/null +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -0,0 +1,50 @@ +/* + * Device Tree Source for Renesas r8a7740 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a7779"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + + gic: interrupt-controller@f0001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xf0001000 0x1000>, + <0xf0000100 0x100>; + }; +}; diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index e48606d8a2be..3f067100bb05 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -59,6 +59,7 @@ extern void r8a7740_pinmux_init(void); extern void r8a7740_pm_init(void); extern void r8a7779_init_irq(void); +extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index 8807c27f71f9..f9cc4bc9c798 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } -void __init r8a7779_init_irq(void) +static void __init r8a7779_init_irq_common(void) { - void __iomem *gic_dist_base = IOMEM(0xf0001000); - void __iomem *gic_cpu_base = IOMEM(0xf0000100); - - /* use GIC to handle interrupts */ - gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = r8a7779_set_wake; /* route all interrupts to ARM */ @@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void) __raw_writel(0xbffffffc, INT2SMSKCR3); __raw_writel(0x003fee3f, INT2SMSKCR4); } + +void __init r8a7779_init_irq(void) +{ + void __iomem *gic_dist_base = IOMEM(0xf0001000); + void __iomem *gic_cpu_base = IOMEM(0xf0000100); + + /* use GIC to handle interrupts */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); + + r8a7779_init_irq_common(); +} + +#ifdef CONFIG_OF +void __init r8a7779_init_irq_dt(void) +{ + irqchip_init(); + r8a7779_init_irq_common(); +} +#endif From 10e8d4f6dddb0f9dc408c2f2bde8399b243a42ca Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 21 Nov 2012 22:00:15 +0900 Subject: [PATCH 025/307] ARM: mach-shmobile: r8a7779: Minimal setup using DT Allow a minimal setup of the r8a7779 SoC using a flattened device tree. In particular, configure the i2c and ethernet controllers using a flattened device tree. SCI serial controller and TMU clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC. The ethernet controller also requires a regulator which is a board property. A sample snippet DT for the marzen board is as follows: /dts-v1/; /include/ "r8a7779.dtsi" / { fixedregulator3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; &lan0 { vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; }; Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 45 +++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 2 + arch/arm/mach-shmobile/setup-r8a7779.c | 59 ++++++++++++++++++-- 3 files changed, 100 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8c6d52cee6c6..2913759e93e2 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -47,4 +47,49 @@ gic: interrupt-controller@f0001000 { reg = <0xf0001000 0x1000>, <0xf0000100 0x100>; }; + + i2c0: i2c@0xffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc70000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 79 0x4>; + }; + + i2c1: i2c@0xffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc71000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 82 0x4>; + }; + + i2c2: i2c@0xffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc72000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 80 0x4>; + }; + + i2c3: i2c@0xffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc73000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 81 0x4>; + }; + + lan0: lan0@18000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x18000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = <0 28 0x4>; + reg-io-width = <4>; + }; }; diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 3f067100bb05..c72d301a8d98 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -63,7 +63,9 @@ extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); +extern void r8a7779_add_early_devices_dt(void); extern void r8a7779_add_standard_devices(void); +extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index c54ff9b29fe5..922dd4db21a0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -321,7 +322,7 @@ static struct platform_device i2c3_device = { .num_resources = ARRAY_SIZE(rcar_i2c3_res), }; -static struct platform_device *r8a7779_early_devices[] __initdata = { +static struct platform_device *r8a7779_early_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -330,15 +331,15 @@ static struct platform_device *r8a7779_early_devices[] __initdata = { &scif5_device, &tmu00_device, &tmu01_device, +}; + +static struct platform_device *r8a7779_early_devices[] __initdata = { &i2c0_device, &i2c1_device, &i2c2_device, &i2c3_device, }; -static struct platform_device *r8a7779_late_devices[] __initdata = { -}; - void __init r8a7779_add_standard_devices(void) { #ifdef CONFIG_CACHE_L2X0 @@ -349,10 +350,10 @@ void __init r8a7779_add_standard_devices(void) r8a7779_init_pm_domains(); + platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); - platform_add_devices(r8a7779_late_devices, - ARRAY_SIZE(r8a7779_late_devices)); } /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ @@ -367,6 +368,8 @@ void __init r8a7779_earlytimer_init(void) void __init r8a7779_add_early_devices(void) { + early_platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); early_platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); @@ -386,3 +389,47 @@ void __init r8a7779_add_early_devices(void) * command line in case of the marzen board. */ } + +#ifdef CONFIG_USE_OF +void __init r8a7779_add_early_devices_dt(void) +{ + shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ + + early_platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); + + /* Early serial console setup is not included here. + * See comment in r8a7779_add_early_devices(). + */ +} + +static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = { + {}, +}; + +void __init r8a7779_add_standard_devices_dt(void) +{ + /* clocks are setup late during boot in the case of DT */ + r8a7779_clock_init(); + + platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); + of_platform_populate(NULL, of_default_bus_match_table, + r8a7779_auxdata_lookup, NULL); +} + +static const char *r8a7779_compat_dt[] __initdata = { + "renesas,r8a7779", + NULL, +}; + +DT_MACHINE_START(SH73A0_DT, "Generic R8A7779 (Flattened Device Tree)") + .map_io = r8a7779_map_io, + .init_early = r8a7779_add_early_devices_dt, + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = r8a7779_init_irq_dt, + .init_machine = r8a7779_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7779_compat_dt, +MACHINE_END +#endif /* CONFIG_USE_OF */ From aa8d3bb177a3ba64407d98c75d5c6c5130ff2182 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:46:38 +0900 Subject: [PATCH 026/307] ARM: shmobile: Kill off sh73a0 scu_base_addr() function Replace scu_base_addr() with a static shmobile_scu_base variable and introduce SH73A0_SCU_BASE. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 81c0f4ba1846..0757f4a94bf5 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -39,13 +39,12 @@ #define PSTR_SHUTDOWN_MODE 3 -static void __iomem *scu_base_addr(void) -{ - return (void __iomem *)0xf0000000; -} +#define SH73A0_SCU_BASE IOMEM(0xf0000000) + +static void __iomem *shmobile_scu_base; #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); void __init sh73a0_register_twd(void) { twd_local_timer_register(&twd_local_timer); @@ -71,21 +70,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { - scu_enable(scu_base_addr()); + scu_enable(shmobile_scu_base); /* Map the reset vector (in headsmp-sh73a0.S) */ __raw_writel(0, APARMBAREA); /* 4k */ __raw_writel(__pa(sh73a0_secondary_vector), SBAR); /* enable cache coherency on booting CPU */ - scu_power_mode(scu_base_addr(), SCU_PM_NORMAL); + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); } static void __init sh73a0_smp_init_cpus(void) { - unsigned int ncores = scu_get_core_count(scu_base_addr()); + /* setup sh73a0 specific SCU base */ + shmobile_scu_base = SH73A0_SCU_BASE; - shmobile_smp_init_cpus(ncores); + shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } #ifdef CONFIG_HOTPLUG_CPU @@ -121,7 +121,7 @@ static void sh73a0_cpu_die(unsigned int cpu) flush_cache_all(); /* Set power off mode. This takes the CPU out of the MP cluster */ - scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF); + scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); /* Enter shutdown mode */ cpu_do_idle(); From 3b94afa38350ad5b592df5b6539a20a253e04b53 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:46:48 +0900 Subject: [PATCH 027/307] ARM: shmobile: Kill off r8a7779 scu_base_addr() function Replace scu_base_addr() with a static shmobile_scu_base variable and introduce R8A7779_SCU_BASE. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index f46b51658c3a..d92188d702ab 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -31,6 +31,9 @@ #include #define AVECR IOMEM(0xfe700040) +#define R8A7779_SCU_BASE IOMEM(0xf0000000) + +static void __iomem *shmobile_scu_base; static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ @@ -56,11 +59,6 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { [3] = &r8a7779_ch_cpu3, }; -static void __iomem *scu_base_addr(void) -{ - return (void __iomem *)0xf0000000; -} - static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; @@ -75,7 +73,7 @@ void __init r8a7779_register_twd(void) static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { - void __iomem *scu_base = scu_base_addr(); + void __iomem *scu_base = shmobile_scu_base; spin_lock(&scu_lock); tmp = __raw_readl(scu_base + 8); @@ -153,7 +151,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { int cpu = cpu_logical_map(0); - scu_enable(scu_base_addr()); + scu_enable(shmobile_scu_base); /* Map the reset vector (in headsmp.S) */ __raw_writel(__pa(shmobile_secondary_vector), AVECR); @@ -171,9 +169,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) static void __init r8a7779_smp_init_cpus(void) { - unsigned int ncores = scu_get_core_count(scu_base_addr()); + /* setup r8a7779 specific SCU base */ + shmobile_scu_base = R8A7779_SCU_BASE; - shmobile_smp_init_cpus(ncores); + shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } struct smp_operations r8a7779_smp_ops __initdata = { From d8a28ed1bc06128f8761b332c74759db1dc7d82c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:46:57 +0900 Subject: [PATCH 028/307] ARM: shmobile: Rework EMEV2 scu_base variable Rename the static scu_base variable into shmobile_scu_base. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 4ede41339a70..136867ea1e93 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -32,8 +32,9 @@ #define EMEV2_SCU_BASE 0x1e000000 +static void __iomem *shmobile_scu_base; + static DEFINE_SPINLOCK(scu_lock); -static void __iomem *scu_base; static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { @@ -42,10 +43,10 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) /* we assume this code is running on a different cpu * than the one that is changing coherency setting */ spin_lock(&scu_lock); - tmp = readl(scu_base + 8); + tmp = readl(shmobile_scu_base + 8); tmp &= ~clr; tmp |= set; - writel(tmp, scu_base + 8); + writel(tmp, shmobile_scu_base + 8); spin_unlock(&scu_lock); } @@ -70,7 +71,7 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { int cpu = cpu_logical_map(0); - scu_enable(scu_base); + scu_enable(shmobile_scu_base); /* Tell ROM loader about our vector (in headsmp.S) */ emev2_set_boot_vector(__pa(shmobile_secondary_vector)); @@ -83,12 +84,12 @@ static void __init emev2_smp_init_cpus(void) { unsigned int ncores; - if (!scu_base) { - scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + if (!shmobile_scu_base) { + shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); emev2_clock_init(); /* need ioremapped SMU */ } - ncores = scu_base ? scu_get_core_count(scu_base) : 1; + ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1; shmobile_smp_init_cpus(ncores); } From ec0d84a8d5522aaed3f932caff30a0b165c8cf44 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:47:07 +0900 Subject: [PATCH 029/307] ARM: shmobile: Move headsmp-sh73a0.S to headsmp-scu.S Rename headsmp-sh73a0.S into headsmp-scu.S and introduce shmobile_secondary_vector_scu(). The goal is to be able to share the function above between all mach-shmobile SoCs that use SCU for SMP. So far only sh73a0 use this. At this time the SCU base address is still hard coded in headsmp-scu.S to 0xf0000000, but this will be changed in the future. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/headsmp-scu.S | 50 ++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 2 +- arch/arm/mach-shmobile/smp-sh73a0.c | 4 +- 4 files changed, 54 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-shmobile/headsmp-scu.S diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index e1fac57514b9..245a8736754a 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o # SMP objects smp-y := platsmp.o headsmp.o smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o -smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-sh73a0.o +smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S new file mode 100644 index 000000000000..4ee287d9c508 --- /dev/null +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -0,0 +1,50 @@ +/* + * Shared SCU setup for mach-shmobile + * + * Copyright (C) 2012 Bastian Hecht + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + __CPUINIT +/* + * Reset vector for secondary CPUs. + * + * First we turn on L1 cache coherency for our CPU. Then we jump to + * shmobile_invalidate_start that invalidates the cache and hands over control + * to the common ARM startup code. + * This function will be mapped to address 0 by the SBAR register. + * A normal branch is out of range here so we need a long jump. We jump to + * the physical address as the MMU is still turned off. + */ + .align 12 +ENTRY(shmobile_secondary_vector_scu) + mrc p15, 0, r0, c0, c0, 5 @ read MIPDR + and r0, r0, #3 @ mask out cpu ID + lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits + mov r1, #0xf0000000 @ SCU base address + ldr r2, [r1, #8] @ SCU Power Status Register + mov r3, #3 + bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) + str r2, [r1, #8] @ write back + + ldr pc, 1f +1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +ENDPROC(shmobile_secondary_vector_scu) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index c72d301a8d98..20acf000b46b 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, struct twd_local_timer; extern void shmobile_setup_console(void); extern void shmobile_secondary_vector(void); +extern void shmobile_secondary_vector_scu(void); struct clk; extern int shmobile_clk_init(void); extern void shmobile_handle_irq_intc(struct pt_regs *); @@ -44,7 +45,6 @@ extern void sh73a0_add_standard_devices_dt(void); extern void sh73a0_clock_init(void); extern void sh73a0_pinmux_init(void); extern void sh73a0_pm_init(void); -extern void sh73a0_secondary_vector(void); extern struct clk sh73a0_extal1_clk; extern struct clk sh73a0_extal2_clk; extern struct clk sh73a0_extcki_clk; diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 0757f4a94bf5..de7518f745f0 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -72,9 +72,9 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { scu_enable(shmobile_scu_base); - /* Map the reset vector (in headsmp-sh73a0.S) */ + /* Map the reset vector (in headsmp-scu.S) */ __raw_writel(0, APARMBAREA); /* 4k */ - __raw_writel(__pa(sh73a0_secondary_vector), SBAR); + __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR); /* enable cache coherency on booting CPU */ scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); From 4c8228455d1008136d748e6973dd72578bab4697 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:47:17 +0900 Subject: [PATCH 030/307] ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S Update the code in headsmp-scu.S to use a global shmobile_scu_base variable both for convenient SCU base address storage and for the early SCU setup code in shmobile_secondary_vector_scu. With this patch applied r8a7779, sh73a0 and EMEV2 all make use of the global shmobile_scu_base variable. However only sh73a0 makes use of the SCU bring up code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 4 +- arch/arm/mach-shmobile/headsmp-scu.S | 8 +++- arch/arm/mach-shmobile/headsmp-sh73a0.S | 50 -------------------- arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/smp-emev2.c | 2 - arch/arm/mach-shmobile/smp-r8a7779.c | 2 - arch/arm/mach-shmobile/smp-sh73a0.c | 2 - 7 files changed, 10 insertions(+), 59 deletions(-) delete mode 100644 arch/arm/mach-shmobile/headsmp-sh73a0.S diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 245a8736754a..d7d20579bef7 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o smp-y := platsmp.o headsmp.o smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o -smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o -smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o +smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o +smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o # IRQ objects obj-$(CONFIG_ARCH_SH7372) += entry-intc.o diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index 4ee287d9c508..0b9317062b2a 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -39,7 +39,8 @@ ENTRY(shmobile_secondary_vector_scu) mrc p15, 0, r0, c0, c0, 5 @ read MIPDR and r0, r0, #3 @ mask out cpu ID lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - mov r1, #0xf0000000 @ SCU base address + ldr r1, =shmobile_scu_base + ldr r1, [r1] @ SCU base address ldr r2, [r1, #8] @ SCU Power Status Register mov r3, #3 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) @@ -48,3 +49,8 @@ ENTRY(shmobile_secondary_vector_scu) ldr pc, 1f 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET ENDPROC(shmobile_secondary_vector_scu) + + .text + .globl shmobile_scu_base +shmobile_scu_base: + .space 4 diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-sh73a0.S deleted file mode 100644 index bec4c0d9b713..000000000000 --- a/arch/arm/mach-shmobile/headsmp-sh73a0.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * SMP support for SoC sh73a0 - * - * Copyright (C) 2012 Bastian Hecht - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - __CPUINIT -/* - * Reset vector for secondary CPUs. - * - * First we turn on L1 cache coherency for our CPU. Then we jump to - * shmobile_invalidate_start that invalidates the cache and hands over control - * to the common ARM startup code. - * This function will be mapped to address 0 by the SBAR register. - * A normal branch is out of range here so we need a long jump. We jump to - * the physical address as the MMU is still turned off. - */ - .align 12 -ENTRY(sh73a0_secondary_vector) - mrc p15, 0, r0, c0, c0, 5 @ read MIPDR - and r0, r0, #3 @ mask out cpu ID - lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - mov r1, #0xf0000000 @ SCU base address - ldr r2, [r1, #8] @ SCU Power Status Register - mov r3, #3 - bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) - str r2, [r1, #8] @ write back - - ldr pc, 1f -1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET -ENDPROC(sh73a0_secondary_vector) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 20acf000b46b..84dcaa4279b2 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -95,6 +95,7 @@ extern int shmobile_cpu_is_dead(unsigned int cpu); static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } #endif +extern void __iomem *shmobile_scu_base; extern void shmobile_smp_init_cpus(unsigned int ncores); static inline void __init shmobile_init_late(void) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 136867ea1e93..bc8e071d55c6 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -32,8 +32,6 @@ #define EMEV2_SCU_BASE 0x1e000000 -static void __iomem *shmobile_scu_base; - static DEFINE_SPINLOCK(scu_lock); static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index d92188d702ab..7fd58a3a26d8 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -33,8 +33,6 @@ #define AVECR IOMEM(0xfe700040) #define R8A7779_SCU_BASE IOMEM(0xf0000000) -static void __iomem *shmobile_scu_base; - static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 1, /* ARM1 */ diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index de7518f745f0..2244fd074f72 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -41,8 +41,6 @@ #define SH73A0_SCU_BASE IOMEM(0xf0000000) -static void __iomem *shmobile_scu_base; - #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); void __init sh73a0_register_twd(void) From 1af4b3fa1912f20a3dd1e231e90b439c0226b9b1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:47:27 +0900 Subject: [PATCH 031/307] ARM: shmobile: Update EMEV2 to use scu_power_mode() Update the SMP code for EMEV2 to make use of the shared SCU function scu_power_mode() together with the early setup code in shmobile_secondary_vector_scu. With this patch in place the secondary CPUs modify the SCU setting during early boot instead of letting other CPUs deal with the coherency setting before boot. In other words, we used to setup coherency before boot in emev2_boot_secondary() but that bit is now instead handled by the code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 42 ++++++------------------------ 1 file changed, 8 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index bc8e071d55c6..8225c16b371b 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -28,27 +28,9 @@ #include #include #include -#include #define EMEV2_SCU_BASE 0x1e000000 -static DEFINE_SPINLOCK(scu_lock); - -static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) -{ - unsigned long tmp; - - /* we assume this code is running on a different cpu - * than the one that is changing coherency setting */ - spin_lock(&scu_lock); - tmp = readl(shmobile_scu_base + 8); - tmp &= ~clr; - tmp |= set; - writel(tmp, shmobile_scu_base + 8); - spin_unlock(&scu_lock); - -} - static void __cpuinit emev2_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -56,36 +38,28 @@ static void __cpuinit emev2_secondary_init(unsigned int cpu) static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) { - cpu = cpu_logical_map(cpu); - - /* enable cache coherency */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); - - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); return 0; } static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { - int cpu = cpu_logical_map(0); - scu_enable(shmobile_scu_base); - /* Tell ROM loader about our vector (in headsmp.S) */ - emev2_set_boot_vector(__pa(shmobile_secondary_vector)); + /* Tell ROM loader about our vector (in headsmp-scu.S) */ + emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu)); - /* enable cache coherency on CPU0 */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); + /* enable cache coherency on booting CPU */ + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); } static void __init emev2_smp_init_cpus(void) { unsigned int ncores; - if (!shmobile_scu_base) { - shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); - emev2_clock_init(); /* need ioremapped SMU */ - } + /* setup EMEV2 specific SCU base */ + shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + emev2_clock_init(); /* need ioremapped SMU */ ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1; From 342ab8741cf3da5505e0d253784d19365a2eca8f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:49:47 +0900 Subject: [PATCH 032/307] ARM: shmobile: Make EMEV2 setup functions static Adjust emev2_init_delay() and emev2_add_standard_devices_dt() to become static. They are not used outside this file anyway. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-emev2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index 47662a581c0a..e4545c152722 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void) ARRAY_SIZE(emev2_late_devices)); } -void __init emev2_init_delay(void) +static void __init emev2_init_delay(void) { shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ } @@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = { { } }; -void __init emev2_add_standard_devices_dt(void) +static void __init emev2_add_standard_devices_dt(void) { of_platform_populate(NULL, of_default_bus_match_table, emev2_auxdata_lookup, NULL); From 8a444474efbe808471366fb57f31ec802846a818 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 22 Feb 2013 18:17:51 +0100 Subject: [PATCH 033/307] ARM: shmobile: sh73a0: fix Z and ZG clock hierarchy Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 5fa106b61149..71843dd39e16 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), - [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0), + [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), From 4eca134f71a5d3095b54279b7e643b3c2df9512c Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: [PATCH 034/307] ARM: shmobile: sh73a0: Remove sh73a0_init_irq_dt() This is not needed as irq_set_wake is only used for suspend to ram which is not a requirement for bringing up boards using DT. Reported-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/intc-sh73a0.c | 8 -------- arch/arm/mach-shmobile/setup-sh73a0.c | 3 ++- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index 91faba666d46..a81a1d804e2e 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -460,11 +460,3 @@ void __init sh73a0_init_irq(void) sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; setup_irq(gic_spi(34), &sh73a0_pint1_cascade); } - -#ifdef CONFIG_OF -void __init sh73a0_init_irq_dt(void) -{ - irqchip_init(); - gic_arch_extn.irq_set_wake = sh73a0_set_wake; -} -#endif diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index bdab575f88bc..49483f4c76c5 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -921,7 +922,7 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .map_io = sh73a0_map_io, .init_early = sh73a0_add_early_devices_dt, .nr_irqs = NR_IRQS_LEGACY, - .init_irq = sh73a0_init_irq_dt, + .init_irq = irqchip_init, .init_machine = sh73a0_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = sh73a0_boards_compat_dt, From f998950788a4a488e37189b1bb056295cf1fe2f9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: [PATCH 035/307] ARM: shmobile: sh73a0: Add smp ops to DT_MACHINE_START This a board to be brought up with SMP enabled without a board file present. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh73a0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 49483f4c76c5..c7630aaaa260 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -919,6 +919,7 @@ static const char *sh73a0_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") + .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, .init_early = sh73a0_add_early_devices_dt, .nr_irqs = NR_IRQS_LEGACY, From e4e240841d62e24589cc2544430fe0c62699733a Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: [PATCH 036/307] ARM: shmobile: sh73a0: Remove warning about SMP Remove warning about SMP not working with the clock initialisation sheme used for reference DT. This is resolved by not selecting CONFIG_PREEMPT. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh73a0.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index c7630aaaa260..37baa481ce3b 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -879,14 +879,6 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -/* Please note that the clock initialisation shcheme used in - * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt() - * does not work with SMP as there is a yet to be resolved lock-up in - * workqueue initialisation. - * - * CONFIG_SMP should be disabled when using this code. - */ - void __init sh73a0_add_early_devices_dt(void) { shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ From 3b00f9342623a5ebc19bea663199864252bf3e93 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 10:53:05 +0900 Subject: [PATCH 037/307] ARM: shmobile: sh73a0: Do not use early devices with DT reference Do not initialise any early devices when using the minimal DT reference code. Only the delay needs to be initialised. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 2 +- arch/arm/mach-shmobile/setup-sh73a0.c | 24 ++++++++------------ 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 84dcaa4279b2..44cdeccaccd2 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -34,12 +34,12 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode); extern struct clk sh7372_extal1_clk; extern struct clk sh7372_extal2_clk; +extern void sh73a0_init_delay(void); extern void sh73a0_init_irq(void); extern void sh73a0_init_irq_dt(void); extern void sh73a0_map_io(void); extern void sh73a0_earlytimer_init(void); extern void sh73a0_add_early_devices(void); -extern void sh73a0_add_early_devices_dt(void); extern void sh73a0_add_standard_devices(void); extern void sh73a0_add_standard_devices_dt(void); extern void sh73a0_clock_init(void); diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 37baa481ce3b..2257a915746d 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -811,7 +811,7 @@ static struct platform_device ipmmu_device = { .num_resources = ARRAY_SIZE(ipmmu_resources), }; -static struct platform_device *sh73a0_early_devices_dt[] __initdata = { +static struct platform_device *sh73a0_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -848,8 +848,8 @@ void __init sh73a0_add_standard_devices(void) /* Clear software reset bit on SY-DMAC module */ __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); - platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); + platform_add_devices(sh73a0_devices_dt, + ARRAY_SIZE(sh73a0_devices_dt)); platform_add_devices(sh73a0_early_devices, ARRAY_SIZE(sh73a0_early_devices)); platform_add_devices(sh73a0_late_devices, @@ -868,8 +868,8 @@ void __init sh73a0_earlytimer_init(void) void __init sh73a0_add_early_devices(void) { - early_platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); + early_platform_add_devices(sh73a0_devices_dt, + ARRAY_SIZE(sh73a0_devices_dt)); early_platform_add_devices(sh73a0_early_devices, ARRAY_SIZE(sh73a0_early_devices)); @@ -879,15 +879,9 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -void __init sh73a0_add_early_devices_dt(void) +void __init sh73a0_init_delay(void) { shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ - - early_platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); - - /* setup early console here as well */ - shmobile_setup_console(); } static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { @@ -899,8 +893,8 @@ void __init sh73a0_add_standard_devices_dt(void) /* clocks are setup late during boot in the case of DT */ sh73a0_clock_init(); - platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); + platform_add_devices(sh73a0_devices_dt, + ARRAY_SIZE(sh73a0_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, sh73a0_auxdata_lookup, NULL); } @@ -913,7 +907,7 @@ static const char *sh73a0_boards_compat_dt[] __initdata = { DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, - .init_early = sh73a0_add_early_devices_dt, + .init_early = sh73a0_init_delay, .nr_irqs = NR_IRQS_LEGACY, .init_irq = irqchip_init, .init_machine = sh73a0_add_standard_devices_dt, From 916ddc355f061b636a71ee5e1d0eb977ee8a6938 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 10:53:05 +0900 Subject: [PATCH 038/307] ARM: shmobile: r8a7779: Do not use early devices with DT reference Do not initialise any early devices when using the minimal DT reference code. Only the delay needs to be initialised. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 2 +- arch/arm/mach-shmobile/setup-r8a7779.c | 25 +++++++------------- 2 files changed, 10 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 44cdeccaccd2..b8a4872f77b3 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -58,12 +58,12 @@ extern void r8a7740_clock_init(u8 md_ck); extern void r8a7740_pinmux_init(void); extern void r8a7740_pm_init(void); +extern void r8a7779_init_delay(void); extern void r8a7779_init_irq(void); extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); -extern void r8a7779_add_early_devices_dt(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_clock_init(void); diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 922dd4db21a0..b1f7a45b56b9 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -322,7 +322,7 @@ static struct platform_device i2c3_device = { .num_resources = ARRAY_SIZE(rcar_i2c3_res), }; -static struct platform_device *r8a7779_early_devices_dt[] __initdata = { +static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -350,8 +350,8 @@ void __init r8a7779_add_standard_devices(void) r8a7779_init_pm_domains(); - platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); + platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); } @@ -368,8 +368,8 @@ void __init r8a7779_earlytimer_init(void) void __init r8a7779_add_early_devices(void) { - early_platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); + early_platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); early_platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); @@ -391,16 +391,9 @@ void __init r8a7779_add_early_devices(void) } #ifdef CONFIG_USE_OF -void __init r8a7779_add_early_devices_dt(void) +void __init r8a7779_init_delay(void) { shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ - - early_platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); - - /* Early serial console setup is not included here. - * See comment in r8a7779_add_early_devices(). - */ } static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = { @@ -412,8 +405,8 @@ void __init r8a7779_add_standard_devices_dt(void) /* clocks are setup late during boot in the case of DT */ r8a7779_clock_init(); - platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); + platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, r8a7779_auxdata_lookup, NULL); } @@ -425,7 +418,7 @@ static const char *r8a7779_compat_dt[] __initdata = { DT_MACHINE_START(SH73A0_DT, "Generic R8A7779 (Flattened Device Tree)") .map_io = r8a7779_map_io, - .init_early = r8a7779_add_early_devices_dt, + .init_early = r8a7779_init_delay, .nr_irqs = NR_IRQS_LEGACY, .init_irq = r8a7779_init_irq_dt, .init_machine = r8a7779_add_standard_devices_dt, From e792120264ee869dc98bdec3842aa5731de0705b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 10:53:05 +0900 Subject: [PATCH 039/307] ARM: shmobile: r8a7779: Do not initialise i2c as an early device It is sufficient to initialise i2c as a late device. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index b1f7a45b56b9..7f8daf17947c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -333,7 +333,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = { &tmu01_device, }; -static struct platform_device *r8a7779_early_devices[] __initdata = { +static struct platform_device *r8a7779_late_devices[] __initdata = { &i2c0_device, &i2c1_device, &i2c2_device, @@ -352,8 +352,8 @@ void __init r8a7779_add_standard_devices(void) platform_add_devices(r8a7779_devices_dt, ARRAY_SIZE(r8a7779_devices_dt)); - platform_add_devices(r8a7779_early_devices, - ARRAY_SIZE(r8a7779_early_devices)); + platform_add_devices(r8a7779_late_devices, + ARRAY_SIZE(r8a7779_late_devices)); } /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ @@ -370,8 +370,6 @@ void __init r8a7779_add_early_devices(void) { early_platform_add_devices(r8a7779_devices_dt, ARRAY_SIZE(r8a7779_devices_dt)); - early_platform_add_devices(r8a7779_early_devices, - ARRAY_SIZE(r8a7779_early_devices)); /* Early serial console setup is not included here due to * memory map collisions. The SCIF serial ports in r8a7779 From 8819ce4b8874ac1db7b52f7eac7cf9d8e3989102 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 11:32:36 +0900 Subject: [PATCH 040/307] ARM: shmobile: r8a7779: Remove lan from dtsi The ethernet controller is not part of the r8a7779 SoC. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 2913759e93e2..0016302952ec 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -83,13 +83,4 @@ i2c3: i2c@0xffc73000 { interrupt-parent = <&gic>; interrupts = <0 81 0x4>; }; - - lan0: lan0@18000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x18000000 0x100>; - phy-mode = "mii"; - interrupt-parent = <&gic>; - interrupts = <0 28 0x4>; - reg-io-width = <4>; - }; }; From 73e5709875e8b28c63ef8261d61c9eb06b499964 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:46:57 +0900 Subject: [PATCH 041/307] ARM: shmobile: Fix base address readout in headsmp-scu.S Rework the early SCU setup code in headsmp-scu.S to read the base address in the same way as we use to fetch the address of the invalidation function. Reported-by: Bastian Hecht Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/headsmp-scu.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index 0b9317062b2a..7d113f898e7f 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -39,7 +39,7 @@ ENTRY(shmobile_secondary_vector_scu) mrc p15, 0, r0, c0, c0, 5 @ read MIPDR and r0, r0, #3 @ mask out cpu ID lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - ldr r1, =shmobile_scu_base + ldr r1, 2f ldr r1, [r1] @ SCU base address ldr r2, [r1, #8] @ SCU Power Status Register mov r3, #3 @@ -48,6 +48,7 @@ ENTRY(shmobile_secondary_vector_scu) ldr pc, 1f 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET ENDPROC(shmobile_secondary_vector_scu) .text From 76853504c35ef5cf488cf6bac4b65677f3bb672e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:07 +0900 Subject: [PATCH 042/307] ARM: shmobile: Rework SH73A0_SCU_BASE IOMEM() usage Rework the IOMEM() usage for the SCU base address in the case of sh73a0. Removes recently introduced build warnings: arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default] arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].start') [enabled by default] arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default] /arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].end') [enabled by default] Reported-by: Arnd Bergmann Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 2244fd074f72..593f8de28c5e 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -39,7 +39,7 @@ #define PSTR_SHUTDOWN_MODE 3 -#define SH73A0_SCU_BASE IOMEM(0xf0000000) +#define SH73A0_SCU_BASE 0xf0000000 #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); @@ -81,7 +81,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) static void __init sh73a0_smp_init_cpus(void) { /* setup sh73a0 specific SCU base */ - shmobile_scu_base = SH73A0_SCU_BASE; + shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } From abf88136f73da52162d7e70bd1d8d4294c08bf1e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:16 +0900 Subject: [PATCH 043/307] ARM: shmobile: Use R8A7779_SCU_BASE with TWD Rework the IOMEM() usage for the SCU base address in the case of r8a7779. Adjusts the TWD to use R8A7779_SCU_BASE. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 7fd58a3a26d8..e69ce259a2d7 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -31,7 +31,7 @@ #include #define AVECR IOMEM(0xfe700040) -#define R8A7779_SCU_BASE IOMEM(0xf0000000) +#define R8A7779_SCU_BASE 0xf0000000 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ @@ -61,8 +61,7 @@ static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); - +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); void __init r8a7779_register_twd(void) { twd_local_timer_register(&twd_local_timer); @@ -168,7 +167,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) static void __init r8a7779_smp_init_cpus(void) { /* setup r8a7779 specific SCU base */ - shmobile_scu_base = R8A7779_SCU_BASE; + shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } From bbf2627c77355ee07cb589904efaf814cfc223d1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:25 +0900 Subject: [PATCH 044/307] ARM: shmobile: Update r8a7779 to check SCU for hotplug Update the r8a7779 CPU Hotplug code to use SCU PSR to wait for the target CPU core. Previously the shared code in hotplug.c was used to let cpu_kill() wait for cpu_die(). With this change in place the r8a7779 SMP code does not depend on hotplug.c anymore. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 38 +++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index e69ce259a2d7..63c8db966fb2 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,16 @@ void __init r8a7779_register_twd(void) } #endif +static int r8a7779_scu_psr_core_disabled(int cpu) +{ + unsigned long mask = 3 << (cpu * 8); + + if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) + return 1; + + return 0; +} + static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { void __iomem *scu_base = shmobile_scu_base; @@ -89,9 +100,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) cpu = cpu_logical_map(cpu); - /* disable cache coherency */ - modify_scu_cpu_psr(3 << (cpu * 8), 0); - if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -110,7 +118,7 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) * finish before asking SoC-specific code to power off the CPU core. */ for (k = 0; k < 1000; k++) { - if (shmobile_cpu_is_dead(cpu)) + if (r8a7779_scu_psr_core_disabled(cpu)) return r8a7779_platform_cpu_kill(cpu); mdelay(1); @@ -119,6 +127,24 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) return 0; } +static void __maybe_unused r8a7779_cpu_die(unsigned int cpu) +{ + dsb(); + flush_cache_all(); + + /* disable cache coherency */ + modify_scu_cpu_psr(3 << (cpu * 8), 0); + + /* Endless loop until power off from r8a7779_cpu_kill() */ + while (1) + cpu_do_idle(); +} + +static int __maybe_unused r8a7779_cpu_disable(unsigned int cpu) +{ + /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ + return cpu == 0 ? -EPERM : 0; +} static void __cpuinit r8a7779_secondary_init(unsigned int cpu) { @@ -179,7 +205,7 @@ struct smp_operations r8a7779_smp_ops __initdata = { .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill, - .cpu_die = shmobile_cpu_die, - .cpu_disable = shmobile_cpu_disable, + .cpu_die = r8a7779_cpu_die, + .cpu_disable = r8a7779_cpu_disable, #endif }; From 8bbcd729d219ca7cdc06ad3b0dea161c4c41b807 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:35 +0900 Subject: [PATCH 045/307] ARM: shmobile: Update r8a7779 to use scu_power_mode() Update the SMP code for R8A7779 to make use of the shared SCU function scu_power_mode() together with the early setup code in shmobile_secondary_vector_scu. With this patch in place the secondary CPUs modify the SCU setting during early boot instead of letting other CPUs deal with the coherency setting before boot. In other words, we used to setup coherency before boot in r8a7779_boot_secondary() but that bit is now instead handled by the code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 32 +++++----------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 63c8db966fb2..bdd38091dc9e 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -58,9 +58,6 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { [3] = &r8a7779_ch_cpu3, }; -static DEFINE_SPINLOCK(scu_lock); -static unsigned long tmp; - #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); void __init r8a7779_register_twd(void) @@ -79,20 +76,6 @@ static int r8a7779_scu_psr_core_disabled(int cpu) return 0; } -static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) -{ - void __iomem *scu_base = shmobile_scu_base; - - spin_lock(&scu_lock); - tmp = __raw_readl(scu_base + 8); - tmp &= ~clr; - tmp |= set; - spin_unlock(&scu_lock); - - /* disable cache coherency after releasing the lock */ - __raw_writel(tmp, scu_base + 8); -} - static int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; @@ -133,7 +116,7 @@ static void __maybe_unused r8a7779_cpu_die(unsigned int cpu) flush_cache_all(); /* disable cache coherency */ - modify_scu_cpu_psr(3 << (cpu * 8), 0); + scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); /* Endless loop until power off from r8a7779_cpu_kill() */ while (1) @@ -158,9 +141,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct cpu = cpu_logical_map(cpu); - /* enable cache coherency */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); - if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -172,15 +152,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { - int cpu = cpu_logical_map(0); - scu_enable(shmobile_scu_base); - /* Map the reset vector (in headsmp.S) */ - __raw_writel(__pa(shmobile_secondary_vector), AVECR); + /* Map the reset vector (in headsmp-scu.S) */ + __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); - /* enable cache coherency on CPU0 */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); + /* enable cache coherency on booting CPU */ + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); r8a7779_pm_init(); From eebadd676499e4c8aee181a669cc8a386e308c31 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:44 +0900 Subject: [PATCH 046/307] ARM: shmobile: Use sh73a0-specific cpu disable code Convert the sh73a0 CPU Hotplug code to use a local implementation of ->cpu_disable(). With this change in place the sh73a0 SMP code does no longer depend on hotplug.c. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 593f8de28c5e..5ae502b16437 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -124,6 +124,11 @@ static void sh73a0_cpu_die(unsigned int cpu) /* Enter shutdown mode */ cpu_do_idle(); } + +static int sh73a0_cpu_disable(unsigned int cpu) +{ + return 0; /* CPU0 and CPU1 supported */ +} #endif /* CONFIG_HOTPLUG_CPU */ struct smp_operations sh73a0_smp_ops __initdata = { @@ -134,6 +139,6 @@ struct smp_operations sh73a0_smp_ops __initdata = { #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill, .cpu_die = sh73a0_cpu_die, - .cpu_disable = shmobile_cpu_disable_any, + .cpu_disable = sh73a0_cpu_disable, #endif }; From fd0865c3f7054d9068007fd280681cb4ea7929a1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:54 +0900 Subject: [PATCH 047/307] ARM: shmobile: Rearrange r8a7779 cpu hotplug code Update the r8a7779 SMP code and CPU Hotplug in particular to follow the same style as sh73a0. This means dropping __maybe_unused for #ifdef CONFIG_HOTPLUG_CPU. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 96 ++++++++++++++-------------- 1 file changed, 49 insertions(+), 47 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index bdd38091dc9e..ea4535a5c4e2 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -66,16 +66,6 @@ void __init r8a7779_register_twd(void) } #endif -static int r8a7779_scu_psr_core_disabled(int cpu) -{ - unsigned long mask = 3 << (cpu * 8); - - if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) - return 1; - - return 0; -} - static int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; @@ -92,43 +82,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) return ret ? ret : 1; } -static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) -{ - int k; - - /* this function is running on another CPU than the offline target, - * here we need wait for shutdown code in platform_cpu_die() to - * finish before asking SoC-specific code to power off the CPU core. - */ - for (k = 0; k < 1000; k++) { - if (r8a7779_scu_psr_core_disabled(cpu)) - return r8a7779_platform_cpu_kill(cpu); - - mdelay(1); - } - - return 0; -} - -static void __maybe_unused r8a7779_cpu_die(unsigned int cpu) -{ - dsb(); - flush_cache_all(); - - /* disable cache coherency */ - scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); - - /* Endless loop until power off from r8a7779_cpu_kill() */ - while (1) - cpu_do_idle(); -} - -static int __maybe_unused r8a7779_cpu_disable(unsigned int cpu) -{ - /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ - return cpu == 0 ? -EPERM : 0; -} - static void __cpuinit r8a7779_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -176,6 +129,55 @@ static void __init r8a7779_smp_init_cpus(void) shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } +#ifdef CONFIG_HOTPLUG_CPU +static int r8a7779_scu_psr_core_disabled(int cpu) +{ + unsigned long mask = 3 << (cpu * 8); + + if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) + return 1; + + return 0; +} + +static int r8a7779_cpu_kill(unsigned int cpu) +{ + int k; + + /* this function is running on another CPU than the offline target, + * here we need wait for shutdown code in platform_cpu_die() to + * finish before asking SoC-specific code to power off the CPU core. + */ + for (k = 0; k < 1000; k++) { + if (r8a7779_scu_psr_core_disabled(cpu)) + return r8a7779_platform_cpu_kill(cpu); + + mdelay(1); + } + + return 0; +} + +static void r8a7779_cpu_die(unsigned int cpu) +{ + dsb(); + flush_cache_all(); + + /* disable cache coherency */ + scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); + + /* Endless loop until power off from r8a7779_cpu_kill() */ + while (1) + cpu_do_idle(); +} + +static int r8a7779_cpu_disable(unsigned int cpu) +{ + /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ + return cpu == 0 ? -EPERM : 0; +} +#endif /* CONFIG_HOTPLUG_CPU */ + struct smp_operations r8a7779_smp_ops __initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, From 5e4460fcc845ae669e20eac67558871d3f0ca432 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:48:03 +0900 Subject: [PATCH 048/307] ARM: shmobile: Remove unused hotplug.c Each CPU Hotplug implementation for mach-shmobile is now self-contained, so this change removes unused helper code in hotplug.c. The two CPU Hotplug capable SoCs sh73a0 and r8a7779 remain unchanged. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 1 - arch/arm/mach-shmobile/hotplug.c | 64 -------------------- arch/arm/mach-shmobile/include/mach/common.h | 10 --- 3 files changed, 75 deletions(-) delete mode 100644 arch/arm/mach-shmobile/hotplug.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index d7d20579bef7..b646ff4d742a 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o # SMP objects smp-y := platsmp.o headsmp.o -smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c deleted file mode 100644 index efd0b36a4175..000000000000 --- a/arch/arm/mach-shmobile/hotplug.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * SMP support for R-Mobile / SH-Mobile - * - * Copyright (C) 2010 Magnus Damm - * - * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include - -static cpumask_t dead_cpus; - -void shmobile_cpu_die(unsigned int cpu) -{ - /* hardware shutdown code running on the CPU that is being offlined */ - flush_cache_all(); - dsb(); - - /* notify platform_cpu_kill() that hardware shutdown is finished */ - cpumask_set_cpu(cpu, &dead_cpus); - - /* wait for SoC code in platform_cpu_kill() to shut off CPU core - * power. CPU bring up starts from the reset vector. - */ - while (1) { - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); - } -} - -int shmobile_cpu_disable(unsigned int cpu) -{ - cpumask_clear_cpu(cpu, &dead_cpus); - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} - -int shmobile_cpu_disable_any(unsigned int cpu) -{ - cpumask_clear_cpu(cpu, &dead_cpus); - return 0; -} - -int shmobile_cpu_is_dead(unsigned int cpu) -{ - return cpumask_test_cpu(cpu, &dead_cpus); -} diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index b8a4872f77b3..1ca1ad938d19 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -85,16 +85,6 @@ int shmobile_cpuidle_init(void); static inline int shmobile_cpuidle_init(void) { return 0; } #endif -extern void shmobile_cpu_die(unsigned int cpu); -extern int shmobile_cpu_disable(unsigned int cpu); -extern int shmobile_cpu_disable_any(unsigned int cpu); - -#ifdef CONFIG_HOTPLUG_CPU -extern int shmobile_cpu_is_dead(unsigned int cpu); -#else -static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } -#endif - extern void __iomem *shmobile_scu_base; extern void shmobile_smp_init_cpus(unsigned int ncores); From 386e9464fab9beb6d55081edb120f2ed9a22ca41 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Tue, 26 Feb 2013 11:03:27 -0600 Subject: [PATCH 049/307] ARM: mach-shmobile: r8a7740: Add DT names to clock list This adds temporarily the alternative device names to the clock list that are used when booting via Device Tree setup. Signed-off-by: Bastian Hecht Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 1a9b9a29442a..1feb9a2286a8 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -593,18 +593,27 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), + CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]), CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), + CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), + CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), + CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]), CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), + CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]), CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), + CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]), CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), From 652f9452781630cb624928c48803db353cdeb09f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 25 Feb 2013 01:39:44 -0800 Subject: [PATCH 050/307] ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID R-Car H1 datasheet GIC number is indicating GIC ICCIAR / interrupt ID number, not SPI number, but current marzen board code is using gic_spi() with un-understandable calculation. This patch adds new gic_iid() macro which means ICCIAR / interrupt ID, and used the number currently written on datasheet. Signed-off-by: Kuninori Morimoto [ horms+renesas@verge.net.au: Split board-marzen.c portion into a separate patch ] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/irqs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 06a5da3c3050..992ed213cec1 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -5,6 +5,7 @@ /* GIC */ #define gic_spi(nr) ((nr) + 32) +#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ /* INTCS */ #define INTCS_VECT_BASE 0x3400 From 349f556edd9bdf691d85f38758021668b1013d8e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:11:03 -0800 Subject: [PATCH 051/307] ARM: shmobile: r8a7779: fixup dtsi typo r8a7779 is not r8a7740 chip Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 0016302952ec..c73eb3771be9 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -1,5 +1,5 @@ /* - * Device Tree Source for Renesas r8a7740 + * Device Tree Source for Renesas r8a7779 * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman From abe0e14b0b51b26bdf80ccaf4d7ee99a4b261af0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:11:20 -0800 Subject: [PATCH 052/307] ARM: shmobile: r8a7779: fixup DT machine name r8a7779 is not sh73a0 Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 7f8daf17947c..932285841b71 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -414,7 +414,7 @@ static const char *r8a7779_compat_dt[] __initdata = { NULL, }; -DT_MACHINE_START(SH73A0_DT, "Generic R8A7779 (Flattened Device Tree)") +DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") .map_io = r8a7779_map_io, .init_early = r8a7779_init_delay, .nr_irqs = NR_IRQS_LEGACY, From dbe95ad00b95a8baaedd87ce84996d95e5811055 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:11:41 -0800 Subject: [PATCH 053/307] ARM: shmobile: r8a7779: use gic_iid macro "ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID" enabled to use gic_iid macro. This patch exchange current GIC interrupt setting from gic_spi() to gic_iid() Signed-off-by: Kuninori Morimoto [ horms+renesas@verge.net.au: Updated git commit id in changelog ] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 932285841b71..0068b9f85bc0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -92,7 +92,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(88)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), }; static struct platform_device scif0_device = { @@ -109,7 +109,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(89)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), }; static struct platform_device scif1_device = { @@ -126,7 +126,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(90)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), }; static struct platform_device scif2_device = { @@ -143,7 +143,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(91)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), }; static struct platform_device scif3_device = { @@ -160,7 +160,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(92)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), }; static struct platform_device scif4_device = { @@ -177,7 +177,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(93)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), }; static struct platform_device scif5_device = { @@ -204,7 +204,7 @@ static struct resource tmu00_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(32), + .start = gic_iid(0x40), .flags = IORESOURCE_IRQ, }, }; @@ -234,7 +234,7 @@ static struct resource tmu01_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(33), + .start = gic_iid(0x41), .flags = IORESOURCE_IRQ, }, }; @@ -256,7 +256,7 @@ static struct resource rcar_i2c0_res[] = { .end = 0xffc70fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(79), + .start = gic_iid(0x6f), .flags = IORESOURCE_IRQ, }, }; @@ -274,7 +274,7 @@ static struct resource rcar_i2c1_res[] = { .end = 0xffc71fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(82), + .start = gic_iid(0x72), .flags = IORESOURCE_IRQ, }, }; @@ -292,7 +292,7 @@ static struct resource rcar_i2c2_res[] = { .end = 0xffc72fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(80), + .start = gic_iid(0x70), .flags = IORESOURCE_IRQ, }, }; @@ -310,7 +310,7 @@ static struct resource rcar_i2c3_res[] = { .end = 0xffc73fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(81), + .start = gic_iid(0x71), .flags = IORESOURCE_IRQ, }, }; From 195f96220143dc2672bfb84db9aad3ee536a6c98 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:30:19 -0800 Subject: [PATCH 054/307] ARM: shmobile: tidyup chip series definition order for r8a7740/r8a7779 move r8a7740_meram_workaround() to r8a7740 area from r8a7779 area Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 1ca1ad938d19..86fcdf9fde1b 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -50,6 +50,7 @@ extern struct clk sh73a0_extal2_clk; extern struct clk sh73a0_extcki_clk; extern struct clk sh73a0_extalr_clk; +extern void r8a7740_meram_workaround(void); extern void r8a7740_init_irq(void); extern void r8a7740_map_io(void); extern void r8a7740_add_early_devices(void); @@ -69,8 +70,6 @@ extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); -extern void r8a7740_meram_workaround(void); - extern void r8a7779_register_twd(void); #ifdef CONFIG_SUSPEND From 25a65975fc33826cfb8cdc399c5bb7f4b5364c51 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 4 Mar 2013 00:32:16 -0800 Subject: [PATCH 055/307] ARM: shmobile: r8a7779: add Thermal support on DT 76cc1887496fe80138c6b07c37d7f81e4cf27cde (thermal: rcar: add Device Tree support) supported rcar_thermal DT probing. rcar thermal driver doesn't support IRQ on r8a7779 chip since it is using old design IRQ. R-Car/R-Mobile next generation chips are using new design IRQ, and rcar thermal driver is supporting these. This patch adds rcar_thermal DT support for r8a7779 without IRQ. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index c73eb3771be9..18383db464b0 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -83,4 +83,9 @@ i2c3: i2c@0xffc73000 { interrupt-parent = <&gic>; interrupts = <0 81 0x4>; }; + + thermal@ffc48000 { + compatible = "renesas,rcar-thermal"; + reg = <0xffc48000 0x38>; + }; }; From 7840a65a0384f87b7d02fdaff5001a6d8f5f6491 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 27 Feb 2013 23:34:36 +0300 Subject: [PATCH 056/307] ARM: mach-shmobile: r8a7779: SATA DT configuration Allow configuration of the r8a7779 SoC SATA controller using a flattened device tree. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 18383db464b0..fe5c6f213271 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -88,4 +88,11 @@ thermal@ffc48000 { compatible = "renesas,rcar-thermal"; reg = <0xffc48000 0x38>; }; + + sata: sata@fc600000 { + compatible = "renesas,rcar-sata"; + reg = <0xfc600000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 100 0x4>; + }; }; From a7b9837c7749bf3333151a7d060d239caff1569d Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 27 Feb 2013 23:39:14 +0300 Subject: [PATCH 057/307] ARM: mach-shmobile: r8a7779: add SATA support Add SATA clock for r8a7779 SoC (for both device tree and usual cases). Register SATA controller as a "late" platform device on r8a7779 SoC. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7779.c | 4 ++++ arch/arm/mach-shmobile/setup-r8a7779.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 1db36537255c..0f66d356e1bc 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = { }; enum { MSTP323, MSTP322, MSTP321, MSTP320, + MSTP115, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -99,6 +100,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ @@ -156,6 +158,8 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), /* MSTP32 clocks */ + CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ + CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 0068b9f85bc0..10031fef074a 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -322,6 +323,30 @@ static struct platform_device i2c3_device = { .num_resources = ARRAY_SIZE(rcar_i2c3_res), }; +static struct resource sata_resources[] = { + [0] = { + .name = "rcar-sata", + .start = 0xfc600000, + .end = 0xfc601fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(100), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sata_device = { + .name = "sata_rcar", + .id = -1, + .resource = sata_resources, + .num_resources = ARRAY_SIZE(sata_resources), + .dev = { + .dma_mask = &sata_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif0_device, &scif1_device, @@ -338,6 +363,7 @@ static struct platform_device *r8a7779_late_devices[] __initdata = { &i2c1_device, &i2c2_device, &i2c3_device, + &sata_device, }; void __init r8a7779_add_standard_devices(void) From d60cd5f16b5af62672209eddd64f70be3f68d17b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 8 Mar 2013 02:31:03 +0300 Subject: [PATCH 058/307] ARM: shmobile: R8A7779: use gic_iid() in SATA IRQ resource Commit "ARM: shmobile: r8a7779: use gic_iid macro" switched R8A7779 platform devices to using gic_iid() macro instead of gic_spi() but commit "ARM: mach- shmobile: r8a7779: add SATA support" added another use of gic_spi(). Convert the SATA IRQ resource to using gic_iid(). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 10031fef074a..042df35e71a0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -331,7 +331,7 @@ static struct resource sata_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(100), + .start = gic_iid(0x84), .flags = IORESOURCE_IRQ, }, }; From 6a40cdd5440d7b61a349bc04e85eed4fa7c24a3c Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 5 Mar 2013 14:58:53 +0800 Subject: [PATCH 059/307] pinctrl: abx500: Fix checking if pin use AlternateFunction register It's pointless to check "af.alt_bit1 == UNUSED" twice. This looks like a copy-paste bug, I think what we want is to check if *both* af.alt_bit1 and af.alt_bit2 are UNUSED. Signed-off-by: Axel Lin Acked-by: Patrice Chotard Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-abx500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index caecdd373061..c542a97c82f3 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -422,7 +422,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, } /* check if pin use AlternateFunction register */ - if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED)) + if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) return mode; /* * if pin GPIOSEL bit is set and pin supports alternate function, From 53ded8191e81507da0786ac45152eebb68d25d0c Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:18:18 +0100 Subject: [PATCH 060/307] pinctrl: Print the correct information in debugfs pinconf-state file A bad copy&paste resulted in the debugfs pinconf-state file printing the pin name instead of the state name. Fix it. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index ac8d382a79bb..d611ecfcbf70 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -622,7 +622,7 @@ static const struct file_operations pinconf_dbg_pinname_fops = { static int pinconf_dbg_state_print(struct seq_file *s, void *d) { if (strlen(dbg_state_name)) - seq_printf(s, "%s\n", dbg_pinname); + seq_printf(s, "%s\n", dbg_state_name); else seq_printf(s, "No pin state set\n"); return 0; From bf4d7be57ba9040347065f48a60f895a254f6e28 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Wed, 13 Mar 2013 17:13:46 +0530 Subject: [PATCH 061/307] pinctrl: generic: Fix compilation error The function definition of pinconf_generic_dump_config is defined under CONFIG_DEBUG_FS macro. Define the declaration too under this macro. Without this patch we get the following build error: drivers/built-in.o: In function `pcs_pinconf_config_dbg_show': drivers/pinctrl/pinctrl-single.c:726: undefined reference to `pinconf_generic_dump_config' Signed-off-by: Sachin Kamat Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index e3ed8cb072a5..bfda73d64eed 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -90,7 +90,7 @@ static inline void pinconf_init_device_debugfs(struct dentry *devroot, * pin config. */ -#ifdef CONFIG_GENERIC_PINCONF +#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_DEBUG_FS) void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin); From fe330ce8e1cfc5cb3ba091e28e871aaab436b258 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 15 Feb 2013 16:04:47 +0100 Subject: [PATCH 062/307] sh-pfc: Declare operation structures as const The pinconf, pinctrl and pinmux operation structures hold function pointers that are never modified. Declare them as const. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 11e0e1374d65..887930e78d58 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -70,7 +70,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, "%s", DRV_NAME); } -static struct pinctrl_ops sh_pfc_pinctrl_ops = { +static const struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_groups_count = sh_pfc_get_groups_count, .get_group_name = sh_pfc_get_group_name, .get_group_pins = sh_pfc_get_group_pins, @@ -252,7 +252,7 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, return sh_pfc_reconfig_pin(pmx->pfc, offset, type); } -static struct pinmux_ops sh_pfc_pinmux_ops = { +static const struct pinmux_ops sh_pfc_pinmux_ops = { .get_functions_count = sh_pfc_get_functions_count, .get_function_name = sh_pfc_get_function_name, .get_function_groups = sh_pfc_get_function_groups, @@ -308,7 +308,7 @@ static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, " %s", pinmux_type_str[config]); } -static struct pinconf_ops sh_pfc_pinconf_ops = { +static const struct pinconf_ops sh_pfc_pinconf_ops = { .pin_config_get = sh_pfc_pinconf_get, .pin_config_set = sh_pfc_pinconf_set, .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, From dcc427e1a82df8ff123f12186af31dbe30dfa7cb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 16:38:30 +0100 Subject: [PATCH 063/307] sh-pfc: Don't define the per-device pinctrl struct instances as global The pinctrl_desc and pinctrl_gpio_range structures registered with the pinctrl core are per-device instances. Move them to the dynamically allocated sh_pfc_pinctrl structure and initialize them at runtime. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 40 ++++++++++++++------------------ 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 887930e78d58..d113746ec873 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -27,6 +27,9 @@ struct sh_pfc_pinctrl { struct pinctrl_dev *pctl; + struct pinctrl_desc pctl_desc; + struct pinctrl_gpio_range range; + struct sh_pfc *pfc; struct pinmux_gpio **functions; @@ -314,19 +317,6 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = { .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, }; -static struct pinctrl_gpio_range sh_pfc_gpio_range = { - .name = DRV_NAME, - .id = 0, -}; - -static struct pinctrl_desc sh_pfc_pinctrl_desc = { - .name = DRV_NAME, - .owner = THIS_MODULE, - .pctlops = &sh_pfc_pinctrl_ops, - .pmxops = &sh_pfc_pinmux_ops, - .confops = &sh_pfc_pinconf_ops, -}; - static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, struct pinmux_gpio *gpio, unsigned offset) { @@ -386,9 +376,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) spin_unlock_irqrestore(&pfc->lock, flags); - sh_pfc_pinctrl_desc.pins = pmx->pads; - sh_pfc_pinctrl_desc.npins = pmx->nr_pads; - return 0; } @@ -438,16 +425,25 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) if (unlikely(ret != 0)) return ret; - pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx); + pmx->pctl_desc.name = DRV_NAME; + pmx->pctl_desc.owner = THIS_MODULE; + pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; + pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; + pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; + pmx->pctl_desc.pins = pmx->pads; + pmx->pctl_desc.npins = pmx->nr_pads; + + pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); if (IS_ERR(pmx->pctl)) return PTR_ERR(pmx->pctl); - sh_pfc_gpio_range.npins = pfc->info->last_gpio - - pfc->info->first_gpio + 1; - sh_pfc_gpio_range.base = pfc->info->first_gpio; - sh_pfc_gpio_range.pin_base = pfc->info->first_gpio; + pmx->range.name = DRV_NAME, + pmx->range.id = 0; + pmx->range.npins = pfc->info->last_gpio - pfc->info->first_gpio + 1; + pmx->range.base = pfc->info->first_gpio; + pmx->range.pin_base = pfc->info->first_gpio; - pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range); + pinctrl_add_gpio_range(pmx->pctl, &pmx->range); return 0; } From 942785db87740d144eba0dd717991e07878aaffb Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 12 Feb 2013 16:34:31 +0100 Subject: [PATCH 064/307] sh-pfc: Fix a typo and simplify a definition on sh73a0 Fix definition of the SDHIWP0 function and simplify the CPU_ALL_PORT definition on sh73a0. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 709008e94124..232731bcdd22 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -25,11 +25,7 @@ #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \ - PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \ - PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \ - PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \ + PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ PORT_10(fn, pfx##10, sfx), \ PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ @@ -1502,7 +1498,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), - PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), + PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT257_IN_PU), PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), From e3e89ae43e132b80039614098597ad2fec6cfbb1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 28 Nov 2012 20:52:53 +0100 Subject: [PATCH 065/307] sh-pfc: Drop the sh_pfc_pinctrl spinlock The spinlock is used to protect data that is only accessed sequentially during initialization. Remove it. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index d113746ec873..9bd0a830c140 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -37,8 +37,6 @@ struct sh_pfc_pinctrl { struct pinctrl_pin_desc *pads; unsigned int nr_pads; - - spinlock_t lock; }; static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) @@ -321,7 +319,6 @@ static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, struct pinmux_gpio *gpio, unsigned offset) { struct pinmux_data_reg *dummy; - unsigned long flags; int bit; gpio->flags &= ~PINMUX_FLAG_TYPE; @@ -330,10 +327,7 @@ static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, gpio->flags |= PINMUX_TYPE_GPIO; else { gpio->flags |= PINMUX_TYPE_FUNCTION; - - spin_lock_irqsave(&pmx->lock, flags); pmx->nr_functions++; - spin_unlock_irqrestore(&pmx->lock, flags); } } @@ -381,7 +375,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { - unsigned long flags; int i, fn; pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * @@ -389,8 +382,6 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) if (unlikely(!pmx->functions)) return -ENOMEM; - spin_lock_irqsave(&pmx->lock, flags); - for (i = fn = 0; i < pmx->nr_pads; i++) { struct pinmux_gpio *gpio = pfc->info->gpios + i; @@ -398,8 +389,6 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) pmx->functions[fn++] = gpio; } - spin_unlock_irqrestore(&pmx->lock, flags); - return 0; } @@ -412,8 +401,6 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) if (unlikely(!pmx)) return -ENOMEM; - spin_lock_init(&pmx->lock); - pmx->pfc = pfc; pfc->pinctrl = pmx; From d785fdb5d8ebdb0081624e9d8b220ff199c22645 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 28 Nov 2012 20:56:48 +0100 Subject: [PATCH 066/307] sh-pfc: Don't take the sh_pfc spinlock in sh_pfc_map_gpios() The sh_pfc_map_gpios() function is only called at initialization time when no other task can access the sh_pfc fields. Don't protect the operation with a spinlock. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 9bd0a830c140..4ce2753cb2df 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -334,7 +334,6 @@ static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, /* pinmux ranges -> pinctrl pin descs */ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { - unsigned long flags; int i; pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1; @@ -346,8 +345,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) return -ENOMEM; } - spin_lock_irqsave(&pfc->lock, flags); - /* * We don't necessarily have a 1:1 mapping between pin and linux * GPIO number, as the latter maps to the associated enum_id. @@ -368,8 +365,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) sh_pfc_map_one_gpio(pfc, pmx, gpio, i); } - spin_unlock_irqrestore(&pfc->lock, flags); - return 0; } From 35ad42719efcd25d310d1ad5f8b0f3a5c68e671d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 28 Nov 2012 22:05:49 +0100 Subject: [PATCH 067/307] sh-pfc: Use GPIO_FN instead of PINMUX_GPIO where possible The GPIO_FN macro expands to the PINMUX_GPIO macro. The regular expression to 'unexpand' PINMUX_GPIO to GPIO_FN is s/\tPINMUX_GPIO(GPIO_FN_\([A-Z0-9_]*\),[ \t]*\1_MARK)/\tGPIO_FN(\1)/ This consolidates SoC-specific PFC information to use the same macros for all SoCs. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh7203.c | 462 ++++++++++----------- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 422 +++++++++---------- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 584 +++++++++++++------------- drivers/pinctrl/sh-pfc/pfc-sh7720.c | 307 +++++++------- drivers/pinctrl/sh-pfc/pfc-sh7722.c | 456 ++++++++++---------- drivers/pinctrl/sh-pfc/pfc-sh7723.c | 618 ++++++++++++++-------------- drivers/pinctrl/sh-pfc/pfc-sh7724.c | 614 +++++++++++++-------------- drivers/pinctrl/sh-pfc/pfc-sh7757.c | 596 +++++++++++++-------------- drivers/pinctrl/sh-pfc/pfc-sh7785.c | 330 +++++++-------- drivers/pinctrl/sh-pfc/pfc-sh7786.c | 272 ++++++------ drivers/pinctrl/sh-pfc/pfc-shx3.c | 124 +++--- 11 files changed, 2392 insertions(+), 2393 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index 01b425dfd162..22be49b3bd38 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -817,260 +817,260 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PF0, PF0_DATA), /* INTC */ - PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), + GPIO_FN(PINT7_PB), + GPIO_FN(PINT6_PB), + GPIO_FN(PINT5_PB), + GPIO_FN(PINT4_PB), + GPIO_FN(PINT3_PB), + GPIO_FN(PINT2_PB), + GPIO_FN(PINT1_PB), + GPIO_FN(PINT0_PB), + GPIO_FN(PINT7_PD), + GPIO_FN(PINT6_PD), + GPIO_FN(PINT5_PD), + GPIO_FN(PINT4_PD), + GPIO_FN(PINT3_PD), + GPIO_FN(PINT2_PD), + GPIO_FN(PINT1_PD), + GPIO_FN(PINT0_PD), + GPIO_FN(IRQ7_PB), + GPIO_FN(IRQ6_PB), + GPIO_FN(IRQ5_PB), + GPIO_FN(IRQ4_PB), + GPIO_FN(IRQ3_PB), + GPIO_FN(IRQ2_PB), + GPIO_FN(IRQ1_PB), + GPIO_FN(IRQ0_PB), + GPIO_FN(IRQ7_PD), + GPIO_FN(IRQ6_PD), + GPIO_FN(IRQ5_PD), + GPIO_FN(IRQ4_PD), + GPIO_FN(IRQ3_PD), + GPIO_FN(IRQ2_PD), + GPIO_FN(IRQ1_PD), + GPIO_FN(IRQ0_PD), + GPIO_FN(IRQ7_PE), + GPIO_FN(IRQ6_PE), + GPIO_FN(IRQ5_PE), + GPIO_FN(IRQ4_PE), + GPIO_FN(IRQ3_PE), + GPIO_FN(IRQ2_PE), + GPIO_FN(IRQ1_PE), + GPIO_FN(IRQ0_PE), - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), - PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK), - PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK), + GPIO_FN(WDTOVF), + GPIO_FN(IRQOUT), + GPIO_FN(REFOUT), + GPIO_FN(IRQOUT_REFOUT), + GPIO_FN(UBCTRG), /* CAN */ - PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), - PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), + GPIO_FN(CTX1), + GPIO_FN(CRX1), + GPIO_FN(CTX0), + GPIO_FN(CTX0_CTX1), + GPIO_FN(CRX0), + GPIO_FN(CRX0_CRX1), /* IIC3 */ - PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), - PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + GPIO_FN(SDA3), + GPIO_FN(SCL3), + GPIO_FN(SDA2), + GPIO_FN(SCL2), + GPIO_FN(SDA1), + GPIO_FN(SCL1), + GPIO_FN(SDA0), + GPIO_FN(SCL0), /* DMAC */ - PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK), - PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK), - PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK), - PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK), - PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK), - PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK), - PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK), - PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + GPIO_FN(TEND0_PD), + GPIO_FN(TEND0_PE), + GPIO_FN(DACK0_PD), + GPIO_FN(DACK0_PE), + GPIO_FN(DREQ0_PD), + GPIO_FN(DREQ0_PE), + GPIO_FN(TEND1_PD), + GPIO_FN(TEND1_PE), + GPIO_FN(DACK1_PD), + GPIO_FN(DACK1_PE), + GPIO_FN(DREQ1_PD), + GPIO_FN(DREQ1_PE), + GPIO_FN(DACK2), + GPIO_FN(DREQ2), + GPIO_FN(DACK3), + GPIO_FN(DREQ3), /* ADC */ - PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK), + GPIO_FN(ADTRG_PD), + GPIO_FN(ADTRG_PE), /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), - PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK), - PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK), - PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK), - PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK), - PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK), - PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), - PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(CS4), + GPIO_FN(MRES), + GPIO_FN(BS), + GPIO_FN(IOIS16), + GPIO_FN(CS1), + GPIO_FN(CS6_CE1B), + GPIO_FN(CE2B), + GPIO_FN(CS5_CE1A), + GPIO_FN(CE2A), + GPIO_FN(FRAME), + GPIO_FN(WAIT), + GPIO_FN(RDWR), + GPIO_FN(CKE), + GPIO_FN(CASU), + GPIO_FN(BREQ), + GPIO_FN(RASU), + GPIO_FN(BACK), + GPIO_FN(CASL), + GPIO_FN(RASL), + GPIO_FN(WE3_DQMUU_AH_ICIO_WR), + GPIO_FN(WE2_DQMUL_ICIORD), + GPIO_FN(WE1_DQMLU_WE), + GPIO_FN(WE0_DQMLL), + GPIO_FN(CS3), + GPIO_FN(CS2), + GPIO_FN(A1), + GPIO_FN(A0), + GPIO_FN(CS7), /* TMU */ - PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK), + GPIO_FN(TIOC4D), + GPIO_FN(TIOC4C), + GPIO_FN(TIOC4B), + GPIO_FN(TIOC4A), + GPIO_FN(TIOC3D), + GPIO_FN(TIOC3C), + GPIO_FN(TIOC3B), + GPIO_FN(TIOC3A), + GPIO_FN(TIOC2B), + GPIO_FN(TIOC1B), + GPIO_FN(TIOC2A), + GPIO_FN(TIOC1A), + GPIO_FN(TIOC0D), + GPIO_FN(TIOC0C), + GPIO_FN(TIOC0B), + GPIO_FN(TIOC0A), + GPIO_FN(TCLKD_PD), + GPIO_FN(TCLKC_PD), + GPIO_FN(TCLKB_PD), + GPIO_FN(TCLKA_PD), + GPIO_FN(TCLKD_PF), + GPIO_FN(TCLKC_PF), + GPIO_FN(TCLKB_PF), + GPIO_FN(TCLKA_PF), /* SSU */ - PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK), + GPIO_FN(SCS0_PD), + GPIO_FN(SSO0_PD), + GPIO_FN(SSI0_PD), + GPIO_FN(SSCK0_PD), + GPIO_FN(SCS0_PF), + GPIO_FN(SSO0_PF), + GPIO_FN(SSI0_PF), + GPIO_FN(SSCK0_PF), + GPIO_FN(SCS1_PD), + GPIO_FN(SSO1_PD), + GPIO_FN(SSI1_PD), + GPIO_FN(SSCK1_PD), + GPIO_FN(SCS1_PF), + GPIO_FN(SSO1_PF), + GPIO_FN(SSI1_PF), + GPIO_FN(SSCK1_PF), /* SCIF */ - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + GPIO_FN(TXD0), + GPIO_FN(RXD0), + GPIO_FN(SCK0), + GPIO_FN(TXD1), + GPIO_FN(RXD1), + GPIO_FN(SCK1), + GPIO_FN(TXD2), + GPIO_FN(RXD2), + GPIO_FN(SCK2), + GPIO_FN(RTS3), + GPIO_FN(CTS3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(SCK3), /* SSI */ - PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), + GPIO_FN(AUDIO_CLK), + GPIO_FN(SSIDATA3), + GPIO_FN(SSIWS3), + GPIO_FN(SSISCK3), + GPIO_FN(SSIDATA2), + GPIO_FN(SSIWS2), + GPIO_FN(SSISCK2), + GPIO_FN(SSIDATA1), + GPIO_FN(SSIWS1), + GPIO_FN(SSISCK1), + GPIO_FN(SSIDATA0), + GPIO_FN(SSIWS0), + GPIO_FN(SSISCK0), /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + GPIO_FN(FCE), + GPIO_FN(FRB), + GPIO_FN(NAF7), + GPIO_FN(NAF6), + GPIO_FN(NAF5), + GPIO_FN(NAF4), + GPIO_FN(NAF3), + GPIO_FN(NAF2), + GPIO_FN(NAF1), + GPIO_FN(NAF0), + GPIO_FN(FSC), + GPIO_FN(FOE), + GPIO_FN(FCDE), + GPIO_FN(FWE), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + GPIO_FN(LCD_VEPWC), + GPIO_FN(LCD_VCPWC), + GPIO_FN(LCD_CLK), + GPIO_FN(LCD_FLM), + GPIO_FN(LCD_M_DISP), + GPIO_FN(LCD_CL2), + GPIO_FN(LCD_CL1), + GPIO_FN(LCD_DON), + GPIO_FN(LCD_DATA15), + GPIO_FN(LCD_DATA14), + GPIO_FN(LCD_DATA13), + GPIO_FN(LCD_DATA12), + GPIO_FN(LCD_DATA11), + GPIO_FN(LCD_DATA10), + GPIO_FN(LCD_DATA9), + GPIO_FN(LCD_DATA8), + GPIO_FN(LCD_DATA7), + GPIO_FN(LCD_DATA6), + GPIO_FN(LCD_DATA5), + GPIO_FN(LCD_DATA4), + GPIO_FN(LCD_DATA3), + GPIO_FN(LCD_DATA2), + GPIO_FN(LCD_DATA1), + GPIO_FN(LCD_DATA0), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 2ba5639dcf34..ebe9c7ceb575 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -1218,252 +1218,252 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PK0, PK0_DATA), /* INTC */ - PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), + GPIO_FN(PINT7_PG), + GPIO_FN(PINT6_PG), + GPIO_FN(PINT5_PG), + GPIO_FN(PINT4_PG), + GPIO_FN(PINT3_PG), + GPIO_FN(PINT2_PG), + GPIO_FN(PINT1_PG), - PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), + GPIO_FN(IRQ7_PC), + GPIO_FN(IRQ6_PC), + GPIO_FN(IRQ5_PC), + GPIO_FN(IRQ4_PC), + GPIO_FN(IRQ3_PG), + GPIO_FN(IRQ2_PG), + GPIO_FN(IRQ1_PJ), + GPIO_FN(IRQ0_PJ), + GPIO_FN(IRQ3_PE), + GPIO_FN(IRQ2_PE), + GPIO_FN(IRQ1_PE), + GPIO_FN(IRQ0_PE), /* WDT */ - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + GPIO_FN(WDTOVF), /* CAN */ - PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), + GPIO_FN(CTX1), + GPIO_FN(CRX1), + GPIO_FN(CTX0), + GPIO_FN(CRX0), + GPIO_FN(CRX0_CRX1), /* DMAC */ - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + GPIO_FN(TEND0), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), + GPIO_FN(TEND1), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), /* ADC */ - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(ADTRG), /* BSCh */ - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A18, A18_MARK), - PINMUX_GPIO(GPIO_FN_A17, A17_MARK), - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_A15, A15_MARK), - PINMUX_GPIO(GPIO_FN_A14, A14_MARK), - PINMUX_GPIO(GPIO_FN_A13, A13_MARK), - PINMUX_GPIO(GPIO_FN_A12, A12_MARK), - PINMUX_GPIO(GPIO_FN_A11, A11_MARK), - PINMUX_GPIO(GPIO_FN_A10, A10_MARK), - PINMUX_GPIO(GPIO_FN_A9, A9_MARK), - PINMUX_GPIO(GPIO_FN_A8, A8_MARK), - PINMUX_GPIO(GPIO_FN_A7, A7_MARK), - PINMUX_GPIO(GPIO_FN_A6, A6_MARK), - PINMUX_GPIO(GPIO_FN_A5, A5_MARK), - PINMUX_GPIO(GPIO_FN_A4, A4_MARK), - PINMUX_GPIO(GPIO_FN_A3, A3_MARK), - PINMUX_GPIO(GPIO_FN_A2, A2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A18), + GPIO_FN(A17), + GPIO_FN(A16), + GPIO_FN(A15), + GPIO_FN(A14), + GPIO_FN(A13), + GPIO_FN(A12), + GPIO_FN(A11), + GPIO_FN(A10), + GPIO_FN(A9), + GPIO_FN(A8), + GPIO_FN(A7), + GPIO_FN(A6), + GPIO_FN(A5), + GPIO_FN(A4), + GPIO_FN(A3), + GPIO_FN(A2), + GPIO_FN(A1), + GPIO_FN(A0), - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), - PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), - PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK), - PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK), - PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), - PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), - PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), - PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + GPIO_FN(BS), + GPIO_FN(CS4), + GPIO_FN(CS3), + GPIO_FN(CS2), + GPIO_FN(CS1), + GPIO_FN(CS0), + GPIO_FN(CS6CE1B), + GPIO_FN(CS5CE1A), + GPIO_FN(CE2A), + GPIO_FN(CE2B), + GPIO_FN(RD), + GPIO_FN(RDWR), + GPIO_FN(ICIOWRAH), + GPIO_FN(ICIORD), + GPIO_FN(WE1DQMUWE), + GPIO_FN(WE0DQML), + GPIO_FN(RAS), + GPIO_FN(CAS), + GPIO_FN(CKE), + GPIO_FN(WAIT), + GPIO_FN(BREQ), + GPIO_FN(BACK), + GPIO_FN(IOIS16), /* TMU */ - PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), + GPIO_FN(TIOC4D), + GPIO_FN(TIOC4C), + GPIO_FN(TIOC4B), + GPIO_FN(TIOC4A), + GPIO_FN(TIOC3D), + GPIO_FN(TIOC3C), + GPIO_FN(TIOC3B), + GPIO_FN(TIOC3A), + GPIO_FN(TIOC2B), + GPIO_FN(TIOC1B), + GPIO_FN(TIOC2A), + GPIO_FN(TIOC1A), + GPIO_FN(TIOC0D), + GPIO_FN(TIOC0C), + GPIO_FN(TIOC0B), + GPIO_FN(TIOC0A), + GPIO_FN(TCLKD), + GPIO_FN(TCLKC), + GPIO_FN(TCLKB), + GPIO_FN(TCLKA), /* SCIF */ - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), - PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), - PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), - PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), - PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), - PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), - PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), - PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), + GPIO_FN(TXD0), + GPIO_FN(RXD0), + GPIO_FN(SCK0), + GPIO_FN(TXD1), + GPIO_FN(RXD1), + GPIO_FN(SCK1), + GPIO_FN(TXD2), + GPIO_FN(RXD2), + GPIO_FN(SCK2), + GPIO_FN(RTS3), + GPIO_FN(CTS3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(SCK3), + GPIO_FN(TXD4), + GPIO_FN(RXD4), + GPIO_FN(TXD5), + GPIO_FN(RXD5), + GPIO_FN(TXD6), + GPIO_FN(RXD6), + GPIO_FN(TXD7), + GPIO_FN(RXD7), + GPIO_FN(RTS1), + GPIO_FN(CTS1), /* RSPI */ - PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK), - PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK), - PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK), - PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), - PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK), - PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), - PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), - PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK), - PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), + GPIO_FN(RSPCK0), + GPIO_FN(MOSI0), + GPIO_FN(MISO0_PF12), + GPIO_FN(MISO1), + GPIO_FN(SSL00), + GPIO_FN(RSPCK1), + GPIO_FN(MOSI1), + GPIO_FN(MISO1_PG19), + GPIO_FN(SSL10), /* IIC3 */ - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + GPIO_FN(SCL0), + GPIO_FN(SCL1), + GPIO_FN(SCL2), + GPIO_FN(SDA0), + GPIO_FN(SDA1), + GPIO_FN(SDA2), /* SSI */ - PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), - PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), + GPIO_FN(SSISCK0), + GPIO_FN(SSIWS0), + GPIO_FN(SSITXD0), + GPIO_FN(SSIRXD0), + GPIO_FN(SSIWS1), + GPIO_FN(SSIWS2), + GPIO_FN(SSIWS3), + GPIO_FN(SSISCK1), + GPIO_FN(SSISCK2), + GPIO_FN(SSISCK3), + GPIO_FN(SSIDATA1), + GPIO_FN(SSIDATA2), + GPIO_FN(SSIDATA3), + GPIO_FN(AUDIO_CLK), /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), + GPIO_FN(SIOFTXD), + GPIO_FN(SIOFRXD), + GPIO_FN(SIOFSYNC), + GPIO_FN(SIOFSCK), /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), - PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), + GPIO_FN(SPDIF_IN), + GPIO_FN(SPDIF_OUT), /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(FRB), /* VDC3 */ - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_HSYNC), - PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), + GPIO_FN(DV_DATA7), + GPIO_FN(DV_DATA6), + GPIO_FN(DV_DATA5), + GPIO_FN(DV_DATA4), + GPIO_FN(DV_DATA3), + GPIO_FN(DV_DATA2), + GPIO_FN(DV_DATA1), + GPIO_FN(DV_DATA0), - PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), + GPIO_FN(LCD_CLK), + GPIO_FN(LCD_EXTCLK), + GPIO_FN(LCD_VSYNC), + GPIO_FN(LCD_HSYNC), + GPIO_FN(LCD_DE), - PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + GPIO_FN(LCD_DATA15), + GPIO_FN(LCD_DATA14), + GPIO_FN(LCD_DATA13), + GPIO_FN(LCD_DATA12), + GPIO_FN(LCD_DATA11), + GPIO_FN(LCD_DATA10), + GPIO_FN(LCD_DATA9), + GPIO_FN(LCD_DATA8), + GPIO_FN(LCD_DATA7), + GPIO_FN(LCD_DATA6), + GPIO_FN(LCD_DATA5), + GPIO_FN(LCD_DATA4), + GPIO_FN(LCD_DATA3), + GPIO_FN(LCD_DATA2), + GPIO_FN(LCD_DATA1), + GPIO_FN(LCD_DATA0), - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + GPIO_FN(LCD_M_DISP), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index b1b5d6d4ad76..87cb6933e02b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -1615,334 +1615,334 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), /* INTC */ - PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK), + GPIO_FN(IRQ7_PG), + GPIO_FN(IRQ6_PG), + GPIO_FN(IRQ5_PG), + GPIO_FN(IRQ4_PG), + GPIO_FN(IRQ3_PG), + GPIO_FN(IRQ2_PG), + GPIO_FN(IRQ1_PG), + GPIO_FN(IRQ0_PG), + GPIO_FN(IRQ7_PF), + GPIO_FN(IRQ6_PF), + GPIO_FN(IRQ5_PF), + GPIO_FN(IRQ4_PF), + GPIO_FN(IRQ3_PJ), + GPIO_FN(IRQ2_PJ), + GPIO_FN(IRQ1_PJ), + GPIO_FN(IRQ0_PJ), + GPIO_FN(IRQ1_PC), + GPIO_FN(IRQ0_PC), - PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK), + GPIO_FN(PINT7_PG), + GPIO_FN(PINT6_PG), + GPIO_FN(PINT5_PG), + GPIO_FN(PINT4_PG), + GPIO_FN(PINT3_PG), + GPIO_FN(PINT2_PG), + GPIO_FN(PINT1_PG), + GPIO_FN(PINT0_PG), + GPIO_FN(PINT7_PH), + GPIO_FN(PINT6_PH), + GPIO_FN(PINT5_PH), + GPIO_FN(PINT4_PH), + GPIO_FN(PINT3_PH), + GPIO_FN(PINT2_PH), + GPIO_FN(PINT1_PH), + GPIO_FN(PINT0_PH), + GPIO_FN(PINT7_PJ), + GPIO_FN(PINT6_PJ), + GPIO_FN(PINT5_PJ), + GPIO_FN(PINT4_PJ), + GPIO_FN(PINT3_PJ), + GPIO_FN(PINT2_PJ), + GPIO_FN(PINT1_PJ), + GPIO_FN(PINT0_PJ), /* WDT */ - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + GPIO_FN(WDTOVF), /* CAN */ - PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK), + GPIO_FN(CTX1), + GPIO_FN(CRX1), + GPIO_FN(CTX0), + GPIO_FN(CRX0), + GPIO_FN(CRX0_CRX1), + GPIO_FN(CRX0_CRX1_CRX2), /* DMAC */ - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + GPIO_FN(TEND0), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), + GPIO_FN(TEND1), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), /* ADC */ - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(ADTRG), /* BSCh */ - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A18, A18_MARK), - PINMUX_GPIO(GPIO_FN_A17, A17_MARK), - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_A15, A15_MARK), - PINMUX_GPIO(GPIO_FN_A14, A14_MARK), - PINMUX_GPIO(GPIO_FN_A13, A13_MARK), - PINMUX_GPIO(GPIO_FN_A12, A12_MARK), - PINMUX_GPIO(GPIO_FN_A11, A11_MARK), - PINMUX_GPIO(GPIO_FN_A10, A10_MARK), - PINMUX_GPIO(GPIO_FN_A9, A9_MARK), - PINMUX_GPIO(GPIO_FN_A8, A8_MARK), - PINMUX_GPIO(GPIO_FN_A7, A7_MARK), - PINMUX_GPIO(GPIO_FN_A6, A6_MARK), - PINMUX_GPIO(GPIO_FN_A5, A5_MARK), - PINMUX_GPIO(GPIO_FN_A4, A4_MARK), - PINMUX_GPIO(GPIO_FN_A3, A3_MARK), - PINMUX_GPIO(GPIO_FN_A2, A2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A18), + GPIO_FN(A17), + GPIO_FN(A16), + GPIO_FN(A15), + GPIO_FN(A14), + GPIO_FN(A13), + GPIO_FN(A12), + GPIO_FN(A11), + GPIO_FN(A10), + GPIO_FN(A9), + GPIO_FN(A8), + GPIO_FN(A7), + GPIO_FN(A6), + GPIO_FN(A5), + GPIO_FN(A4), + GPIO_FN(A3), + GPIO_FN(A2), + GPIO_FN(A1), + GPIO_FN(A0), - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), - PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), - PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK), - PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK), - PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), - PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), - PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), - PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + GPIO_FN(BS), + GPIO_FN(CS4), + GPIO_FN(CS3), + GPIO_FN(CS2), + GPIO_FN(CS1), + GPIO_FN(CS0), + GPIO_FN(CS5CE1A), + GPIO_FN(CE2A), + GPIO_FN(CE2B), + GPIO_FN(RD), + GPIO_FN(RDWR), + GPIO_FN(WE3ICIOWRAHDQMUU), + GPIO_FN(WE2ICIORDDQMUL), + GPIO_FN(WE1DQMUWE), + GPIO_FN(WE0DQML), + GPIO_FN(RAS), + GPIO_FN(CAS), + GPIO_FN(CKE), + GPIO_FN(WAIT), + GPIO_FN(BREQ), + GPIO_FN(BACK), + GPIO_FN(IOIS16), /* TMU */ - PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), + GPIO_FN(TIOC4D), + GPIO_FN(TIOC4C), + GPIO_FN(TIOC4B), + GPIO_FN(TIOC4A), + GPIO_FN(TIOC3D), + GPIO_FN(TIOC3C), + GPIO_FN(TIOC3B), + GPIO_FN(TIOC3A), + GPIO_FN(TIOC2B), + GPIO_FN(TIOC1B), + GPIO_FN(TIOC2A), + GPIO_FN(TIOC1A), + GPIO_FN(TIOC0D), + GPIO_FN(TIOC0C), + GPIO_FN(TIOC0B), + GPIO_FN(TIOC0A), + GPIO_FN(TCLKD), + GPIO_FN(TCLKC), + GPIO_FN(TCLKB), + GPIO_FN(TCLKA), /* SCIF */ - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), - PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK), - PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), - PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), - PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK), - PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK), - PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK), - PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), - PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), - PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK), - PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), - PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), - PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK), - PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK), + GPIO_FN(SCK0), + GPIO_FN(TXD0), + GPIO_FN(RXD0), + GPIO_FN(SCK1), + GPIO_FN(TXD1), + GPIO_FN(RXD1), + GPIO_FN(RTS1), + GPIO_FN(CTS1), + GPIO_FN(SCK2), + GPIO_FN(TXD2), + GPIO_FN(RXD2), + GPIO_FN(SCK3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(SCK4), + GPIO_FN(TXD4), + GPIO_FN(RXD4), + GPIO_FN(SCK5), + GPIO_FN(TXD5), + GPIO_FN(RXD5), + GPIO_FN(RTS5), + GPIO_FN(CTS5), + GPIO_FN(SCK6), + GPIO_FN(TXD6), + GPIO_FN(RXD6), + GPIO_FN(SCK7), + GPIO_FN(TXD7), + GPIO_FN(RXD7), + GPIO_FN(RTS7), + GPIO_FN(CTS7), /* RSPI */ - PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK), - PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK), - PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK), - PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK), - PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK), - PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK), - PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK), - PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK), - PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), - PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), - PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), - PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), + GPIO_FN(RSPCK0_PJ16), + GPIO_FN(SSL00_PJ17), + GPIO_FN(MOSI0_PJ18), + GPIO_FN(MISO0_PJ19), + GPIO_FN(RSPCK0_PB17), + GPIO_FN(SSL00_PB18), + GPIO_FN(MOSI0_PB19), + GPIO_FN(MISO0_PB20), + GPIO_FN(RSPCK1), + GPIO_FN(MOSI1), + GPIO_FN(MISO1), + GPIO_FN(SSL10), /* IIC3 */ - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + GPIO_FN(SCL0), + GPIO_FN(SCL1), + GPIO_FN(SCL2), + GPIO_FN(SDA0), + GPIO_FN(SDA1), + GPIO_FN(SDA2), /* SSI */ - PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), - PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), - PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK), + GPIO_FN(SSISCK0), + GPIO_FN(SSIWS0), + GPIO_FN(SSITXD0), + GPIO_FN(SSIRXD0), + GPIO_FN(SSIWS1), + GPIO_FN(SSIWS2), + GPIO_FN(SSIWS3), + GPIO_FN(SSISCK1), + GPIO_FN(SSISCK2), + GPIO_FN(SSISCK3), + GPIO_FN(SSIDATA1), + GPIO_FN(SSIDATA2), + GPIO_FN(SSIDATA3), + GPIO_FN(AUDIO_CLK), + GPIO_FN(AUDIO_XOUT), /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), + GPIO_FN(SIOFTXD), + GPIO_FN(SIOFRXD), + GPIO_FN(SIOFSYNC), + GPIO_FN(SIOFSCK), /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), - PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), + GPIO_FN(SPDIF_IN), + GPIO_FN(SPDIF_OUT), /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(FRB), /* VDC3 */ - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_HSYNC), - PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), + GPIO_FN(DV_DATA23), + GPIO_FN(DV_DATA22), + GPIO_FN(DV_DATA21), + GPIO_FN(DV_DATA20), + GPIO_FN(DV_DATA19), + GPIO_FN(DV_DATA18), + GPIO_FN(DV_DATA17), + GPIO_FN(DV_DATA16), + GPIO_FN(DV_DATA15), + GPIO_FN(DV_DATA14), + GPIO_FN(DV_DATA13), + GPIO_FN(DV_DATA12), + GPIO_FN(DV_DATA11), + GPIO_FN(DV_DATA10), + GPIO_FN(DV_DATA9), + GPIO_FN(DV_DATA8), + GPIO_FN(DV_DATA7), + GPIO_FN(DV_DATA6), + GPIO_FN(DV_DATA5), + GPIO_FN(DV_DATA4), + GPIO_FN(DV_DATA3), + GPIO_FN(DV_DATA2), + GPIO_FN(DV_DATA1), + GPIO_FN(DV_DATA0), - PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), + GPIO_FN(LCD_CLK), + GPIO_FN(LCD_EXTCLK), + GPIO_FN(LCD_VSYNC), + GPIO_FN(LCD_HSYNC), + GPIO_FN(LCD_DE), - PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK), + GPIO_FN(LCD_DATA23_PG23), + GPIO_FN(LCD_DATA22_PG22), + GPIO_FN(LCD_DATA21_PG21), + GPIO_FN(LCD_DATA20_PG20), + GPIO_FN(LCD_DATA19_PG19), + GPIO_FN(LCD_DATA18_PG18), + GPIO_FN(LCD_DATA17_PG17), + GPIO_FN(LCD_DATA16_PG16), + GPIO_FN(LCD_DATA15_PG15), + GPIO_FN(LCD_DATA14_PG14), + GPIO_FN(LCD_DATA13_PG13), + GPIO_FN(LCD_DATA12_PG12), + GPIO_FN(LCD_DATA11_PG11), + GPIO_FN(LCD_DATA10_PG10), + GPIO_FN(LCD_DATA9_PG9), + GPIO_FN(LCD_DATA8_PG8), + GPIO_FN(LCD_DATA7_PG7), + GPIO_FN(LCD_DATA6_PG6), + GPIO_FN(LCD_DATA5_PG5), + GPIO_FN(LCD_DATA4_PG4), + GPIO_FN(LCD_DATA3_PG3), + GPIO_FN(LCD_DATA2_PG2), + GPIO_FN(LCD_DATA1_PG1), + GPIO_FN(LCD_DATA0_PG0), - PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK), + GPIO_FN(LCD_DATA23_PJ23), + GPIO_FN(LCD_DATA22_PJ22), + GPIO_FN(LCD_DATA21_PJ21), + GPIO_FN(LCD_DATA20_PJ20), + GPIO_FN(LCD_DATA19_PJ19), + GPIO_FN(LCD_DATA18_PJ18), + GPIO_FN(LCD_DATA17_PJ17), + GPIO_FN(LCD_DATA16_PJ16), + GPIO_FN(LCD_DATA15_PJ15), + GPIO_FN(LCD_DATA14_PJ14), + GPIO_FN(LCD_DATA13_PJ13), + GPIO_FN(LCD_DATA12_PJ12), + GPIO_FN(LCD_DATA11_PJ11), + GPIO_FN(LCD_DATA10_PJ10), + GPIO_FN(LCD_DATA9_PJ9), + GPIO_FN(LCD_DATA8_PJ8), + GPIO_FN(LCD_DATA7_PJ7), + GPIO_FN(LCD_DATA6_PJ6), + GPIO_FN(LCD_DATA5_PJ5), + GPIO_FN(LCD_DATA4_PJ4), + GPIO_FN(LCD_DATA3_PJ3), + GPIO_FN(LCD_DATA2_PJ2), + GPIO_FN(LCD_DATA1_PJ1), + GPIO_FN(LCD_DATA0_PJ0), - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + GPIO_FN(LCD_M_DISP), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 10872ed688a6..e2e4520a14c4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -761,197 +761,196 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), - PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(IOIS16), + GPIO_FN(RAS), + GPIO_FN(CAS), + GPIO_FN(CKE), + GPIO_FN(CS5B_CE1A), + GPIO_FN(CS6B_CE1B), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A0), + GPIO_FN(REFOUT), + GPIO_FN(IRQOUT), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), - PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), + GPIO_FN(LCD_DATA15), + GPIO_FN(LCD_DATA14), + GPIO_FN(LCD_DATA13), + GPIO_FN(LCD_DATA12), + GPIO_FN(LCD_DATA11), + GPIO_FN(LCD_DATA10), + GPIO_FN(LCD_DATA9), + GPIO_FN(LCD_DATA8), + GPIO_FN(LCD_DATA7), + GPIO_FN(LCD_DATA6), + GPIO_FN(LCD_DATA5), + GPIO_FN(LCD_DATA4), + GPIO_FN(LCD_DATA3), + GPIO_FN(LCD_DATA2), + GPIO_FN(LCD_DATA1), + GPIO_FN(LCD_DATA0), + GPIO_FN(LCD_M_DISP), + GPIO_FN(LCD_CL1), + GPIO_FN(LCD_CL2), + GPIO_FN(LCD_DON), + GPIO_FN(LCD_FLM), + GPIO_FN(LCD_VEPWC), + GPIO_FN(LCD_VCPWC), /* AFEIF */ - PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK), - PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK), - PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK), - PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK), - PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK), - PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK), - PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK), + GPIO_FN(AFE_RXIN), + GPIO_FN(AFE_RDET), + GPIO_FN(AFE_FS), + GPIO_FN(AFE_TXOUT), + GPIO_FN(AFE_SCLK), + GPIO_FN(AFE_RLYCNT), + GPIO_FN(AFE_HC1), /* IIC */ - PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK), - PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK), + GPIO_FN(IIC_SCL), + GPIO_FN(IIC_SDA), /* DAC */ - PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK), - PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK), + GPIO_FN(DA1), + GPIO_FN(DA0), /* ADC */ - PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), - PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), - PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), - PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(AN3), + GPIO_FN(AN2), + GPIO_FN(AN1), + GPIO_FN(AN0), + GPIO_FN(ADTRG), /* USB */ - PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK), + GPIO_FN(USB1D_RCV), + GPIO_FN(USB1D_TXSE0), + GPIO_FN(USB1D_TXDPLS), + GPIO_FN(USB1D_DMNS), + GPIO_FN(USB1D_DPLS), + GPIO_FN(USB1D_SPEED), + GPIO_FN(USB1D_TXENL), - PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK), - PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP, - USB1_PWR_EN_USBF_UPLUP_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK), + GPIO_FN(USB2_PWR_EN), + GPIO_FN(USB1_PWR_EN_USBF_UPLUP), + GPIO_FN(USB1D_SUSPEND), /* INTC */ - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK), + GPIO_FN(IRQ5), + GPIO_FN(IRQ4), + GPIO_FN(IRQ3_IRL3), + GPIO_FN(IRQ2_IRL2), + GPIO_FN(IRQ1_IRL1), + GPIO_FN(IRQ0_IRL0), /* PCC */ - PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK), - PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK), - PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK), - PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK), - PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK), - PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK), - PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK), - PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK), - PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK), - PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK), + GPIO_FN(PCC_REG), + GPIO_FN(PCC_DRV), + GPIO_FN(PCC_BVD2), + GPIO_FN(PCC_BVD1), + GPIO_FN(PCC_CD2), + GPIO_FN(PCC_CD1), + GPIO_FN(PCC_RESET), + GPIO_FN(PCC_RDY), + GPIO_FN(PCC_VS2), + GPIO_FN(PCC_VS1), /* HUDI */ - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK), - PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK), - PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK), - PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK), - PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK), - PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), + GPIO_FN(AUDCK), + GPIO_FN(AUDSYNC), + GPIO_FN(ASEBRKAK), + GPIO_FN(TRST), + GPIO_FN(TMS), + GPIO_FN(TDO), + GPIO_FN(TDI), + GPIO_FN(TCK), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), + GPIO_FN(TEND1), + GPIO_FN(TEND0), /* SIOF0 */ - PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), + GPIO_FN(SIOF0_SYNC), + GPIO_FN(SIOF0_MCLK), + GPIO_FN(SIOF0_TXD), + GPIO_FN(SIOF0_RXD), + GPIO_FN(SIOF0_SCK), /* SIOF1 */ - PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), + GPIO_FN(SIOF1_SYNC), + GPIO_FN(SIOF1_MCLK), + GPIO_FN(SIOF1_TXD), + GPIO_FN(SIOF1_RXD), + GPIO_FN(SIOF1_SCK), /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + GPIO_FN(SCIF0_TXD), + GPIO_FN(SCIF0_RXD), + GPIO_FN(SCIF0_RTS), + GPIO_FN(SCIF0_CTS), + GPIO_FN(SCIF0_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + GPIO_FN(SCIF1_TXD), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_RTS), + GPIO_FN(SCIF1_CTS), + GPIO_FN(SCIF1_SCK), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK), + GPIO_FN(TPU_TO1), + GPIO_FN(TPU_TO0), + GPIO_FN(TPU_TI3B), + GPIO_FN(TPU_TI3A), + GPIO_FN(TPU_TI2B), + GPIO_FN(TPU_TI2A), + GPIO_FN(TPU_TO3), + GPIO_FN(TPU_TO2), /* SIM */ - PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), - PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + GPIO_FN(SIM_D), + GPIO_FN(SIM_CLK), + GPIO_FN(SIM_RST), /* MMC */ - PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), - PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK), - PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK), + GPIO_FN(MMC_DAT), + GPIO_FN(MMC_CMD), + GPIO_FN(MMC_CLK), + GPIO_FN(MMC_VDDON), + GPIO_FN(MMC_ODMOD), /* SYSC */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + GPIO_FN(STATUS0), + GPIO_FN(STATUS1), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 2de0929315e6..225fa96b6a21 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -984,284 +984,284 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + GPIO_FN(SCIF0_TXD), + GPIO_FN(SCIF0_RXD), + GPIO_FN(SCIF0_RTS), + GPIO_FN(SCIF0_CTS), + GPIO_FN(SCIF0_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + GPIO_FN(SCIF1_TXD), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_RTS), + GPIO_FN(SCIF1_CTS), + GPIO_FN(SCIF1_SCK), /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), + GPIO_FN(SCIF2_TXD), + GPIO_FN(SCIF2_RXD), + GPIO_FN(SCIF2_RTS), + GPIO_FN(SCIF2_CTS), + GPIO_FN(SCIF2_SCK), /* SIO */ - PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK), - PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK), - PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK), - PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK), - PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK), + GPIO_FN(SIOTXD), + GPIO_FN(SIORXD), + GPIO_FN(SIOD), + GPIO_FN(SIOSTRB0), + GPIO_FN(SIOSTRB1), + GPIO_FN(SIOSCK), + GPIO_FN(SIOMCK), /* CEU */ - PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), - PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK), - PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), + GPIO_FN(VIO_D15), + GPIO_FN(VIO_D14), + GPIO_FN(VIO_D13), + GPIO_FN(VIO_D12), + GPIO_FN(VIO_D11), + GPIO_FN(VIO_D10), + GPIO_FN(VIO_D9), + GPIO_FN(VIO_D8), + GPIO_FN(VIO_D7), + GPIO_FN(VIO_D6), + GPIO_FN(VIO_D5), + GPIO_FN(VIO_D4), + GPIO_FN(VIO_D3), + GPIO_FN(VIO_D2), + GPIO_FN(VIO_D1), + GPIO_FN(VIO_D0), + GPIO_FN(VIO_CLK), + GPIO_FN(VIO_VD), + GPIO_FN(VIO_HD), + GPIO_FN(VIO_FLD), + GPIO_FN(VIO_CKO), + GPIO_FN(VIO_STEX), + GPIO_FN(VIO_STEM), + GPIO_FN(VIO_VD2), + GPIO_FN(VIO_HD2), + GPIO_FN(VIO_CLK2), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), + GPIO_FN(LCDD23), + GPIO_FN(LCDD22), + GPIO_FN(LCDD21), + GPIO_FN(LCDD20), + GPIO_FN(LCDD19), + GPIO_FN(LCDD18), + GPIO_FN(LCDD17), + GPIO_FN(LCDD16), + GPIO_FN(LCDD15), + GPIO_FN(LCDD14), + GPIO_FN(LCDD13), + GPIO_FN(LCDD12), + GPIO_FN(LCDD11), + GPIO_FN(LCDD10), + GPIO_FN(LCDD9), + GPIO_FN(LCDD8), + GPIO_FN(LCDD7), + GPIO_FN(LCDD6), + GPIO_FN(LCDD5), + GPIO_FN(LCDD4), + GPIO_FN(LCDD3), + GPIO_FN(LCDD2), + GPIO_FN(LCDD1), + GPIO_FN(LCDD0), + GPIO_FN(LCDLCLK), /* Main LCD */ - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), + GPIO_FN(LCDDON), + GPIO_FN(LCDVCPWC), + GPIO_FN(LCDVEPWC), + GPIO_FN(LCDVSYN), /* Main LCD - RGB Mode */ - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), + GPIO_FN(LCDDCK), + GPIO_FN(LCDHSYN), + GPIO_FN(LCDDISP), /* Main LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), + GPIO_FN(LCDRS), + GPIO_FN(LCDCS), + GPIO_FN(LCDWR), + GPIO_FN(LCDRD), /* Sub LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK), + GPIO_FN(LCDDON2), + GPIO_FN(LCDVCPWC2), + GPIO_FN(LCDVEPWC2), + GPIO_FN(LCDVSYN2), + GPIO_FN(LCDCS2), /* BSC */ - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), + GPIO_FN(IOIS16), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(BS), + GPIO_FN(CS6B_CE1B), + GPIO_FN(WAIT), + GPIO_FN(CS6A_CE2B), /* SBSC */ - PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK), - PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK), - PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK), - PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK), - PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK), - PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK), - PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK), - PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK), - PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK), - PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK), - PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK), - PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK), - PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK), - PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK), - PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK), - PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK), + GPIO_FN(HPD63), + GPIO_FN(HPD62), + GPIO_FN(HPD61), + GPIO_FN(HPD60), + GPIO_FN(HPD59), + GPIO_FN(HPD58), + GPIO_FN(HPD57), + GPIO_FN(HPD56), + GPIO_FN(HPD55), + GPIO_FN(HPD54), + GPIO_FN(HPD53), + GPIO_FN(HPD52), + GPIO_FN(HPD51), + GPIO_FN(HPD50), + GPIO_FN(HPD49), + GPIO_FN(HPD48), + GPIO_FN(HPDQM7), + GPIO_FN(HPDQM6), + GPIO_FN(HPDQM5), + GPIO_FN(HPDQM4), /* IRQ */ - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + GPIO_FN(IRQ0), + GPIO_FN(IRQ1), + GPIO_FN(IRQ2), + GPIO_FN(IRQ3), + GPIO_FN(IRQ4), + GPIO_FN(IRQ5), + GPIO_FN(IRQ6), + GPIO_FN(IRQ7), /* SDHI */ - PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK), - PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK), - PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK), - PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK), - PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK), - PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK), - PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK), + GPIO_FN(SDHICD), + GPIO_FN(SDHIWP), + GPIO_FN(SDHID3), + GPIO_FN(SDHID2), + GPIO_FN(SDHID1), + GPIO_FN(SDHID0), + GPIO_FN(SDHICMD), + GPIO_FN(SDHICLK), /* SIU - Port A */ - PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK), - PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK), + GPIO_FN(SIUAOLR), + GPIO_FN(SIUAOBT), + GPIO_FN(SIUAISLD), + GPIO_FN(SIUAILR), + GPIO_FN(SIUAIBT), + GPIO_FN(SIUAOSLD), + GPIO_FN(SIUMCKA), + GPIO_FN(SIUFCKA), /* SIU - Port B */ - PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK), - PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK), + GPIO_FN(SIUBOLR), + GPIO_FN(SIUBOBT), + GPIO_FN(SIUBISLD), + GPIO_FN(SIUBILR), + GPIO_FN(SIUBIBT), + GPIO_FN(SIUBOSLD), + GPIO_FN(SIUMCKB), + GPIO_FN(SIUFCKB), /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + GPIO_FN(DACK), + GPIO_FN(DREQ0), /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), + GPIO_FN(DV_CLKI), + GPIO_FN(DV_CLK), + GPIO_FN(DV_HSYNC), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_D15), + GPIO_FN(DV_D14), + GPIO_FN(DV_D13), + GPIO_FN(DV_D12), + GPIO_FN(DV_D11), + GPIO_FN(DV_D10), + GPIO_FN(DV_D9), + GPIO_FN(DV_D8), + GPIO_FN(DV_D7), + GPIO_FN(DV_D6), + GPIO_FN(DV_D5), + GPIO_FN(DV_D4), + GPIO_FN(DV_D3), + GPIO_FN(DV_D2), + GPIO_FN(DV_D1), + GPIO_FN(DV_D0), /* CPG */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), + GPIO_FN(STATUS0), + GPIO_FN(PDSTATUS), /* SIOF0 */ - PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), + GPIO_FN(SIOF0_MCK), + GPIO_FN(SIOF0_SCK), + GPIO_FN(SIOF0_SYNC), + GPIO_FN(SIOF0_SS1), + GPIO_FN(SIOF0_SS2), + GPIO_FN(SIOF0_TXD), + GPIO_FN(SIOF0_RXD), /* SIOF1 */ - PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), + GPIO_FN(SIOF1_MCK), + GPIO_FN(SIOF1_SCK), + GPIO_FN(SIOF1_SYNC), + GPIO_FN(SIOF1_SS1), + GPIO_FN(SIOF1_SS2), + GPIO_FN(SIOF1_TXD), + GPIO_FN(SIOF1_RXD), /* SIM */ - PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), - PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + GPIO_FN(SIM_D), + GPIO_FN(SIM_CLK), + GPIO_FN(SIM_RST), /* TSIF */ - PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK), + GPIO_FN(TS_SDAT), + GPIO_FN(TS_SCK), + GPIO_FN(TS_SDEN), + GPIO_FN(TS_SPSYNC), /* IRDA */ - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), + GPIO_FN(IRDA_IN), + GPIO_FN(IRDA_OUT), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK), + GPIO_FN(TPUTO), /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(NAF7), + GPIO_FN(NAF6), + GPIO_FN(NAF5), + GPIO_FN(NAF4), + GPIO_FN(NAF3), + GPIO_FN(NAF2), + GPIO_FN(NAF1), + GPIO_FN(NAF0), + GPIO_FN(FCDE), + GPIO_FN(FOE), + GPIO_FN(FSC), + GPIO_FN(FWE), + GPIO_FN(FRB), /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), + GPIO_FN(KEYIN0), + GPIO_FN(KEYIN1), + GPIO_FN(KEYIN2), + GPIO_FN(KEYIN3), + GPIO_FN(KEYIN4), + GPIO_FN(KEYOUT0), + GPIO_FN(KEYOUT1), + GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT3), + GPIO_FN(KEYOUT4_IN6), + GPIO_FN(KEYOUT5_IN5), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 609673d3d70e..49fd5c82e3cf 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -1141,374 +1141,374 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK), + GPIO_FN(SCIF0_PTT_TXD), + GPIO_FN(SCIF0_PTT_RXD), + GPIO_FN(SCIF0_PTT_SCK), + GPIO_FN(SCIF0_PTU_TXD), + GPIO_FN(SCIF0_PTU_RXD), + GPIO_FN(SCIF0_PTU_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK), + GPIO_FN(SCIF1_PTS_TXD), + GPIO_FN(SCIF1_PTS_RXD), + GPIO_FN(SCIF1_PTS_SCK), + GPIO_FN(SCIF1_PTV_TXD), + GPIO_FN(SCIF1_PTV_RXD), + GPIO_FN(SCIF1_PTV_SCK), /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK), + GPIO_FN(SCIF2_PTT_TXD), + GPIO_FN(SCIF2_PTT_RXD), + GPIO_FN(SCIF2_PTT_SCK), + GPIO_FN(SCIF2_PTU_TXD), + GPIO_FN(SCIF2_PTU_RXD), + GPIO_FN(SCIF2_PTU_SCK), /* SCIF3 */ - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK), + GPIO_FN(SCIF3_PTS_TXD), + GPIO_FN(SCIF3_PTS_RXD), + GPIO_FN(SCIF3_PTS_SCK), + GPIO_FN(SCIF3_PTS_RTS), + GPIO_FN(SCIF3_PTS_CTS), + GPIO_FN(SCIF3_PTV_TXD), + GPIO_FN(SCIF3_PTV_RXD), + GPIO_FN(SCIF3_PTV_SCK), + GPIO_FN(SCIF3_PTV_RTS), + GPIO_FN(SCIF3_PTV_CTS), /* SCIF4 */ - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK), + GPIO_FN(SCIF4_PTE_TXD), + GPIO_FN(SCIF4_PTE_RXD), + GPIO_FN(SCIF4_PTE_SCK), + GPIO_FN(SCIF4_PTN_TXD), + GPIO_FN(SCIF4_PTN_RXD), + GPIO_FN(SCIF4_PTN_SCK), /* SCIF5 */ - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK), + GPIO_FN(SCIF5_PTE_TXD), + GPIO_FN(SCIF5_PTE_RXD), + GPIO_FN(SCIF5_PTE_SCK), + GPIO_FN(SCIF5_PTN_TXD), + GPIO_FN(SCIF5_PTN_RXD), + GPIO_FN(SCIF5_PTN_SCK), /* CEU */ - PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), + GPIO_FN(VIO_D15), + GPIO_FN(VIO_D14), + GPIO_FN(VIO_D13), + GPIO_FN(VIO_D12), + GPIO_FN(VIO_D11), + GPIO_FN(VIO_D10), + GPIO_FN(VIO_D9), + GPIO_FN(VIO_D8), + GPIO_FN(VIO_D7), + GPIO_FN(VIO_D6), + GPIO_FN(VIO_D5), + GPIO_FN(VIO_D4), + GPIO_FN(VIO_D3), + GPIO_FN(VIO_D2), + GPIO_FN(VIO_D1), + GPIO_FN(VIO_D0), + GPIO_FN(VIO_CLK1), + GPIO_FN(VIO_VD1), + GPIO_FN(VIO_HD1), + GPIO_FN(VIO_FLD), + GPIO_FN(VIO_CKO), + GPIO_FN(VIO_VD2), + GPIO_FN(VIO_HD2), + GPIO_FN(VIO_CLK2), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK), + GPIO_FN(LCDD23), + GPIO_FN(LCDD22), + GPIO_FN(LCDD21), + GPIO_FN(LCDD20), + GPIO_FN(LCDD19), + GPIO_FN(LCDD18), + GPIO_FN(LCDD17), + GPIO_FN(LCDD16), + GPIO_FN(LCDD15), + GPIO_FN(LCDD14), + GPIO_FN(LCDD13), + GPIO_FN(LCDD12), + GPIO_FN(LCDD11), + GPIO_FN(LCDD10), + GPIO_FN(LCDD9), + GPIO_FN(LCDD8), + GPIO_FN(LCDD7), + GPIO_FN(LCDD6), + GPIO_FN(LCDD5), + GPIO_FN(LCDD4), + GPIO_FN(LCDD3), + GPIO_FN(LCDD2), + GPIO_FN(LCDD1), + GPIO_FN(LCDD0), + GPIO_FN(LCDLCLK_PTR), + GPIO_FN(LCDLCLK_PTW), /* Main LCD */ - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), + GPIO_FN(LCDDON), + GPIO_FN(LCDVCPWC), + GPIO_FN(LCDVEPWC), + GPIO_FN(LCDVSYN), /* Main LCD - RGB Mode */ - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), + GPIO_FN(LCDDCK), + GPIO_FN(LCDHSYN), + GPIO_FN(LCDDISP), /* Main LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), + GPIO_FN(LCDRS), + GPIO_FN(LCDCS), + GPIO_FN(LCDWR), + GPIO_FN(LCDRD), /* IRQ */ - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + GPIO_FN(IRQ0), + GPIO_FN(IRQ1), + GPIO_FN(IRQ2), + GPIO_FN(IRQ3), + GPIO_FN(IRQ4), + GPIO_FN(IRQ5), + GPIO_FN(IRQ6), + GPIO_FN(IRQ7), /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + GPIO_FN(AUDCK), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), /* SDHI0 (PTD) */ - PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK), + GPIO_FN(SDHI0CD_PTD), + GPIO_FN(SDHI0WP_PTD), + GPIO_FN(SDHI0D3_PTD), + GPIO_FN(SDHI0D2_PTD), + GPIO_FN(SDHI0D1_PTD), + GPIO_FN(SDHI0D0_PTD), + GPIO_FN(SDHI0CMD_PTD), + GPIO_FN(SDHI0CLK_PTD), /* SDHI0 (PTS) */ - PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK), + GPIO_FN(SDHI0CD_PTS), + GPIO_FN(SDHI0WP_PTS), + GPIO_FN(SDHI0D3_PTS), + GPIO_FN(SDHI0D2_PTS), + GPIO_FN(SDHI0D1_PTS), + GPIO_FN(SDHI0D0_PTS), + GPIO_FN(SDHI0CMD_PTS), + GPIO_FN(SDHI0CLK_PTS), /* SDHI1 */ - PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), + GPIO_FN(SDHI1CD), + GPIO_FN(SDHI1WP), + GPIO_FN(SDHI1D3), + GPIO_FN(SDHI1D2), + GPIO_FN(SDHI1D1), + GPIO_FN(SDHI1D0), + GPIO_FN(SDHI1CMD), + GPIO_FN(SDHI1CLK), /* SIUA */ - PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSPD, SIUAOSPD_MARK), + GPIO_FN(SIUAFCK), + GPIO_FN(SIUAILR), + GPIO_FN(SIUAIBT), + GPIO_FN(SIUAISLD), + GPIO_FN(SIUAOLR), + GPIO_FN(SIUAOBT), + GPIO_FN(SIUAOSLD), + GPIO_FN(SIUAMCK), + GPIO_FN(SIUAISPD), + GPIO_FN(SIUAOSPD), /* SIUB */ - PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK), + GPIO_FN(SIUBFCK), + GPIO_FN(SIUBILR), + GPIO_FN(SIUBIBT), + GPIO_FN(SIUBISLD), + GPIO_FN(SIUBOLR), + GPIO_FN(SIUBOBT), + GPIO_FN(SIUBOSLD), + GPIO_FN(SIUBMCK), /* IRDA */ - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), + GPIO_FN(IRDA_IN), + GPIO_FN(IRDA_OUT), /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), + GPIO_FN(DV_CLKI), + GPIO_FN(DV_CLK), + GPIO_FN(DV_HSYNC), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_D15), + GPIO_FN(DV_D14), + GPIO_FN(DV_D13), + GPIO_FN(DV_D12), + GPIO_FN(DV_D11), + GPIO_FN(DV_D10), + GPIO_FN(DV_D9), + GPIO_FN(DV_D8), + GPIO_FN(DV_D7), + GPIO_FN(DV_D6), + GPIO_FN(DV_D5), + GPIO_FN(DV_D4), + GPIO_FN(DV_D3), + GPIO_FN(DV_D2), + GPIO_FN(DV_D1), + GPIO_FN(DV_D0), /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), + GPIO_FN(KEYIN0), + GPIO_FN(KEYIN1), + GPIO_FN(KEYIN2), + GPIO_FN(KEYIN3), + GPIO_FN(KEYIN4), + GPIO_FN(KEYOUT0), + GPIO_FN(KEYOUT1), + GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT3), + GPIO_FN(KEYOUT4_IN6), + GPIO_FN(KEYOUT5_IN5), /* MSIOF0 (PTF) */ - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK), + GPIO_FN(MSIOF0_PTF_TXD), + GPIO_FN(MSIOF0_PTF_RXD), + GPIO_FN(MSIOF0_PTF_MCK), + GPIO_FN(MSIOF0_PTF_TSYNC), + GPIO_FN(MSIOF0_PTF_TSCK), + GPIO_FN(MSIOF0_PTF_RSYNC), + GPIO_FN(MSIOF0_PTF_RSCK), + GPIO_FN(MSIOF0_PTF_SS1), + GPIO_FN(MSIOF0_PTF_SS2), /* MSIOF0 (PTT+PTX) */ - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK), + GPIO_FN(MSIOF0_PTT_TXD), + GPIO_FN(MSIOF0_PTT_RXD), + GPIO_FN(MSIOF0_PTX_MCK), + GPIO_FN(MSIOF0_PTT_TSYNC), + GPIO_FN(MSIOF0_PTT_TSCK), + GPIO_FN(MSIOF0_PTT_RSYNC), + GPIO_FN(MSIOF0_PTT_RSCK), + GPIO_FN(MSIOF0_PTT_SS1), + GPIO_FN(MSIOF0_PTT_SS2), /* MSIOF1 */ - PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), + GPIO_FN(MSIOF1_TXD), + GPIO_FN(MSIOF1_RXD), + GPIO_FN(MSIOF1_MCK), + GPIO_FN(MSIOF1_TSYNC), + GPIO_FN(MSIOF1_TSCK), + GPIO_FN(MSIOF1_RSYNC), + GPIO_FN(MSIOF1_RSCK), + GPIO_FN(MSIOF1_SS1), + GPIO_FN(MSIOF1_SS2), /* TSIF */ - PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK), + GPIO_FN(TS0_SDAT), + GPIO_FN(TS0_SCK), + GPIO_FN(TS0_SDEN), + GPIO_FN(TS0_SPSYNC), /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(NAF7), + GPIO_FN(NAF6), + GPIO_FN(NAF5), + GPIO_FN(NAF4), + GPIO_FN(NAF3), + GPIO_FN(NAF2), + GPIO_FN(NAF1), + GPIO_FN(NAF0), + GPIO_FN(FCDE), + GPIO_FN(FOE), + GPIO_FN(FSC), + GPIO_FN(FWE), + GPIO_FN(FRB), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), /* ADC */ - PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), - PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), - PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), - PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(AN3), + GPIO_FN(AN2), + GPIO_FN(AN1), + GPIO_FN(AN0), + GPIO_FN(ADTRG), /* CPG */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), + GPIO_FN(STATUS0), + GPIO_FN(PDSTATUS), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), + GPIO_FN(TPUTO0), + GPIO_FN(TPUTO1), + GPIO_FN(TPUTO2), + GPIO_FN(TPUTO3), /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), - PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(IOIS16), + GPIO_FN(WAIT), + GPIO_FN(BS), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(CS6B_CE1B), + GPIO_FN(CS6A_CE2B), + GPIO_FN(CS5B_CE1A), + GPIO_FN(CS5A_CE2A), + GPIO_FN(WE3_ICIOWR), + GPIO_FN(WE2_ICIORD), /* ATAPI */ - PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), - PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), - PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), - PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), - PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), - PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), - PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), - PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), - PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), - PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), - PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), - PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), - PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), - PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), - PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), - PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), - PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), - PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), - PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), - PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), - PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), - PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), - PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), - PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), - PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), - PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), - PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), - PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), + GPIO_FN(IDED15), + GPIO_FN(IDED14), + GPIO_FN(IDED13), + GPIO_FN(IDED12), + GPIO_FN(IDED11), + GPIO_FN(IDED10), + GPIO_FN(IDED9), + GPIO_FN(IDED8), + GPIO_FN(IDED7), + GPIO_FN(IDED6), + GPIO_FN(IDED5), + GPIO_FN(IDED4), + GPIO_FN(IDED3), + GPIO_FN(IDED2), + GPIO_FN(IDED1), + GPIO_FN(IDED0), + GPIO_FN(DIRECTION), + GPIO_FN(EXBUF_ENB), + GPIO_FN(IDERST), + GPIO_FN(IODACK), + GPIO_FN(IODREQ), + GPIO_FN(IDEIORDY), + GPIO_FN(IDEINT), + GPIO_FN(IDEIOWR), + GPIO_FN(IDEIORD), + GPIO_FN(IDECS1), + GPIO_FN(IDECS0), + GPIO_FN(IDEA2), + GPIO_FN(IDEA1), + GPIO_FN(IDEA0), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 233fbf750b39..054b700a7e01 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -1420,367 +1420,367 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), - PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(CS6B_CE1B), + GPIO_FN(CS6A_CE2B), + GPIO_FN(CS5B_CE1A), + GPIO_FN(CS5A_CE2A), + GPIO_FN(WE3_ICIOWR), + GPIO_FN(WE2_ICIORD), + GPIO_FN(IOIS16), + GPIO_FN(WAIT), + GPIO_FN(BS), /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), + GPIO_FN(KEYOUT5_IN5), + GPIO_FN(KEYOUT4_IN6), + GPIO_FN(KEYIN4), + GPIO_FN(KEYIN3), + GPIO_FN(KEYIN2), + GPIO_FN(KEYIN1), + GPIO_FN(KEYIN0), + GPIO_FN(KEYOUT3), + GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT1), + GPIO_FN(KEYOUT0), /* ATAPI */ - PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), - PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), - PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), - PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), - PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), - PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), - PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), - PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), - PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), - PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), - PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), - PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), - PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), - PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), - PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), - PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), - PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), - PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), - PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), - PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), - PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), - PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), - PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), - PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), - PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), - PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), - PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), - PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), + GPIO_FN(IDED15), + GPIO_FN(IDED14), + GPIO_FN(IDED13), + GPIO_FN(IDED12), + GPIO_FN(IDED11), + GPIO_FN(IDED10), + GPIO_FN(IDED9), + GPIO_FN(IDED8), + GPIO_FN(IDED7), + GPIO_FN(IDED6), + GPIO_FN(IDED5), + GPIO_FN(IDED4), + GPIO_FN(IDED3), + GPIO_FN(IDED2), + GPIO_FN(IDED1), + GPIO_FN(IDED0), + GPIO_FN(IDEA2), + GPIO_FN(IDEA1), + GPIO_FN(IDEA0), + GPIO_FN(IDEIOWR), + GPIO_FN(IODREQ), + GPIO_FN(IDECS0), + GPIO_FN(IDECS1), + GPIO_FN(IDEIORD), + GPIO_FN(DIRECTION), + GPIO_FN(EXBUF_ENB), + GPIO_FN(IDERST), + GPIO_FN(IODACK), + GPIO_FN(IDEINT), + GPIO_FN(IDEIORDY), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), - PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK), - PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK), + GPIO_FN(TPUTO3), + GPIO_FN(TPUTO2), + GPIO_FN(TPUTO1), + GPIO_FN(TPUTO0), + GPIO_FN(TPUTI3), + GPIO_FN(TPUTI2), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), + GPIO_FN(LCDD23), + GPIO_FN(LCDD22), + GPIO_FN(LCDD21), + GPIO_FN(LCDD20), + GPIO_FN(LCDD19), + GPIO_FN(LCDD18), + GPIO_FN(LCDD17), + GPIO_FN(LCDD16), + GPIO_FN(LCDD15), + GPIO_FN(LCDD14), + GPIO_FN(LCDD13), + GPIO_FN(LCDD12), + GPIO_FN(LCDD11), + GPIO_FN(LCDD10), + GPIO_FN(LCDD9), + GPIO_FN(LCDD8), + GPIO_FN(LCDD7), + GPIO_FN(LCDD6), + GPIO_FN(LCDD5), + GPIO_FN(LCDD4), + GPIO_FN(LCDD3), + GPIO_FN(LCDD2), + GPIO_FN(LCDD1), + GPIO_FN(LCDD0), + GPIO_FN(LCDVSYN), + GPIO_FN(LCDDISP), + GPIO_FN(LCDRS), + GPIO_FN(LCDHSYN), + GPIO_FN(LCDCS), + GPIO_FN(LCDDON), + GPIO_FN(LCDDCK), + GPIO_FN(LCDWR), + GPIO_FN(LCDVEPWC), + GPIO_FN(LCDVCPWC), + GPIO_FN(LCDRD), + GPIO_FN(LCDLCLK), /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + GPIO_FN(SCIF0_TXD), + GPIO_FN(SCIF0_RXD), + GPIO_FN(SCIF0_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + GPIO_FN(SCIF1_SCK), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_TXD), /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK), + GPIO_FN(SCIF2_L_TXD), + GPIO_FN(SCIF2_L_SCK), + GPIO_FN(SCIF2_L_RXD), + GPIO_FN(SCIF2_V_TXD), + GPIO_FN(SCIF2_V_SCK), + GPIO_FN(SCIF2_V_RXD), /* SCIF3 */ - PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK), + GPIO_FN(SCIF3_V_SCK), + GPIO_FN(SCIF3_V_RXD), + GPIO_FN(SCIF3_V_TXD), + GPIO_FN(SCIF3_V_CTS), + GPIO_FN(SCIF3_V_RTS), + GPIO_FN(SCIF3_I_SCK), + GPIO_FN(SCIF3_I_RXD), + GPIO_FN(SCIF3_I_TXD), + GPIO_FN(SCIF3_I_CTS), + GPIO_FN(SCIF3_I_RTS), /* SCIF4 */ - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), + GPIO_FN(SCIF4_SCK), + GPIO_FN(SCIF4_RXD), + GPIO_FN(SCIF4_TXD), /* SCIF5 */ - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), + GPIO_FN(SCIF5_SCK), + GPIO_FN(SCIF5_RXD), + GPIO_FN(SCIF5_TXD), /* FSI */ - PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK), - PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK), - PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK), - PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK), - PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK), - PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK), - PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK), + GPIO_FN(FSIMCKB), + GPIO_FN(FSIMCKA), + GPIO_FN(FSIOASD), + GPIO_FN(FSIIABCK), + GPIO_FN(FSIIALRCK), + GPIO_FN(FSIOABCK), + GPIO_FN(FSIOALRCK), + GPIO_FN(CLKAUDIOAO), + GPIO_FN(FSIIBSD), + GPIO_FN(FSIOBSD), + GPIO_FN(FSIIBBCK), + GPIO_FN(FSIIBLRCK), + GPIO_FN(FSIOBBCK), + GPIO_FN(FSIOBLRCK), + GPIO_FN(CLKAUDIOBO), + GPIO_FN(FSIIASD), /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + GPIO_FN(AUDCK), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), /* VIO */ - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), + GPIO_FN(VIO_CKO), /* VIO0 */ - PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK), + GPIO_FN(VIO0_D15), + GPIO_FN(VIO0_D14), + GPIO_FN(VIO0_D13), + GPIO_FN(VIO0_D12), + GPIO_FN(VIO0_D11), + GPIO_FN(VIO0_D10), + GPIO_FN(VIO0_D9), + GPIO_FN(VIO0_D8), + GPIO_FN(VIO0_D7), + GPIO_FN(VIO0_D6), + GPIO_FN(VIO0_D5), + GPIO_FN(VIO0_D4), + GPIO_FN(VIO0_D3), + GPIO_FN(VIO0_D2), + GPIO_FN(VIO0_D1), + GPIO_FN(VIO0_D0), + GPIO_FN(VIO0_VD), + GPIO_FN(VIO0_CLK), + GPIO_FN(VIO0_FLD), + GPIO_FN(VIO0_HD), /* VIO1 */ - PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK), + GPIO_FN(VIO1_D7), + GPIO_FN(VIO1_D6), + GPIO_FN(VIO1_D5), + GPIO_FN(VIO1_D4), + GPIO_FN(VIO1_D3), + GPIO_FN(VIO1_D2), + GPIO_FN(VIO1_D1), + GPIO_FN(VIO1_D0), + GPIO_FN(VIO1_FLD), + GPIO_FN(VIO1_HD), + GPIO_FN(VIO1_VD), + GPIO_FN(VIO1_CLK), /* Eth */ - PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK), - PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK), - PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK), + GPIO_FN(RMII_RXD0), + GPIO_FN(RMII_RXD1), + GPIO_FN(RMII_TXD0), + GPIO_FN(RMII_TXD1), + GPIO_FN(RMII_REF_CLK), + GPIO_FN(RMII_TX_EN), + GPIO_FN(RMII_RX_ER), + GPIO_FN(RMII_CRS_DV), + GPIO_FN(LNKSTA), + GPIO_FN(MDIO), + GPIO_FN(MDC), /* System */ - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), - PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + GPIO_FN(PDSTATUS), + GPIO_FN(STATUS2), + GPIO_FN(STATUS0), /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + GPIO_FN(DV_D15), + GPIO_FN(DV_D14), + GPIO_FN(DV_D13), + GPIO_FN(DV_D12), + GPIO_FN(DV_D11), + GPIO_FN(DV_D10), + GPIO_FN(DV_D9), + GPIO_FN(DV_D8), + GPIO_FN(DV_D7), + GPIO_FN(DV_D6), + GPIO_FN(DV_D5), + GPIO_FN(DV_D4), + GPIO_FN(DV_D3), + GPIO_FN(DV_D2), + GPIO_FN(DV_D1), + GPIO_FN(DV_D0), + GPIO_FN(DV_CLKI), + GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_HSYNC), /* MSIOF0 */ - PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK), + GPIO_FN(MSIOF0_RXD), + GPIO_FN(MSIOF0_TXD), + GPIO_FN(MSIOF0_MCK), + GPIO_FN(MSIOF0_TSCK), + GPIO_FN(MSIOF0_SS1), + GPIO_FN(MSIOF0_SS2), + GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(MSIOF0_RSCK), + GPIO_FN(MSIOF0_RSYNC), /* MSIOF1 */ - PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), + GPIO_FN(MSIOF1_RXD), + GPIO_FN(MSIOF1_TXD), + GPIO_FN(MSIOF1_MCK), + GPIO_FN(MSIOF1_TSCK), + GPIO_FN(MSIOF1_SS1), + GPIO_FN(MSIOF1_SS2), + GPIO_FN(MSIOF1_TSYNC), + GPIO_FN(MSIOF1_RSCK), + GPIO_FN(MSIOF1_RSYNC), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK), + GPIO_FN(DMAC_DACK0), + GPIO_FN(DMAC_DREQ0), + GPIO_FN(DMAC_DACK1), + GPIO_FN(DMAC_DREQ1), /* SDHI0 */ - PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK), + GPIO_FN(SDHI0CD), + GPIO_FN(SDHI0WP), + GPIO_FN(SDHI0CMD), + GPIO_FN(SDHI0CLK), + GPIO_FN(SDHI0D3), + GPIO_FN(SDHI0D2), + GPIO_FN(SDHI0D1), + GPIO_FN(SDHI0D0), /* SDHI1 */ - PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), + GPIO_FN(SDHI1CD), + GPIO_FN(SDHI1WP), + GPIO_FN(SDHI1CMD), + GPIO_FN(SDHI1CLK), + GPIO_FN(SDHI1D3), + GPIO_FN(SDHI1D2), + GPIO_FN(SDHI1D1), + GPIO_FN(SDHI1D0), /* MMC */ - PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), + GPIO_FN(MMC_D7), + GPIO_FN(MMC_D6), + GPIO_FN(MMC_D5), + GPIO_FN(MMC_D4), + GPIO_FN(MMC_D3), + GPIO_FN(MMC_D2), + GPIO_FN(MMC_D1), + GPIO_FN(MMC_D0), + GPIO_FN(MMC_CLK), + GPIO_FN(MMC_CMD), /* IrDA */ - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), + GPIO_FN(IRDA_OUT), + GPIO_FN(IRDA_IN), /* TSIF */ - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK), + GPIO_FN(TSIF_TS0_SDAT), + GPIO_FN(TSIF_TS0_SCK), + GPIO_FN(TSIF_TS0_SDEN), + GPIO_FN(TSIF_TS0_SPSYNC), /* IRQ */ - PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK), + GPIO_FN(INTC_IRQ7), + GPIO_FN(INTC_IRQ6), + GPIO_FN(INTC_IRQ5), + GPIO_FN(INTC_IRQ4), + GPIO_FN(INTC_IRQ3), + GPIO_FN(INTC_IRQ2), + GPIO_FN(INTC_IRQ1), + GPIO_FN(INTC_IRQ0), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index 5ed74cd0ba99..ffbd8b7ee72e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -1372,354 +1372,354 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), /* PTA (mobule: LBSC, RGMII) */ - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), - PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), - PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), - PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), + GPIO_FN(BS), + GPIO_FN(RDWR), + GPIO_FN(WE1), + GPIO_FN(RDY), + GPIO_FN(ET0_MDC), + GPIO_FN(ET0_MDIO), + GPIO_FN(ET1_MDC), + GPIO_FN(ET1_MDIO), /* PTB (mobule: INTC, ONFI, TMU) */ - PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), - PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), - PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), - PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), - PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), - PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), - PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), - PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), - PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK), - PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK), - PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK), - PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK), - PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK), - PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK), - PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + GPIO_FN(IRQ15), + GPIO_FN(IRQ14), + GPIO_FN(IRQ13), + GPIO_FN(IRQ12), + GPIO_FN(IRQ11), + GPIO_FN(IRQ10), + GPIO_FN(IRQ9), + GPIO_FN(IRQ8), + GPIO_FN(ON_NRE), + GPIO_FN(ON_NWE), + GPIO_FN(ON_NWP), + GPIO_FN(ON_NCE0), + GPIO_FN(ON_R_B0), + GPIO_FN(ON_ALE), + GPIO_FN(ON_CLE), + GPIO_FN(TCLK), /* PTC (mobule: IRQ, PWMU) */ - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK), - PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK), - PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK), - PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK), - PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK), - PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK), + GPIO_FN(IRQ7), + GPIO_FN(IRQ6), + GPIO_FN(IRQ5), + GPIO_FN(IRQ4), + GPIO_FN(IRQ3), + GPIO_FN(IRQ2), + GPIO_FN(IRQ1), + GPIO_FN(IRQ0), + GPIO_FN(PWMU0), + GPIO_FN(PWMU1), + GPIO_FN(PWMU2), + GPIO_FN(PWMU3), + GPIO_FN(PWMU4), + GPIO_FN(PWMU5), /* PTD (mobule: SPI0, DMAC) */ - PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK), - PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + GPIO_FN(SP0_MOSI), + GPIO_FN(SP0_MISO), + GPIO_FN(SP0_SCK), + GPIO_FN(SP0_SCK_FB), + GPIO_FN(SP0_SS0), + GPIO_FN(SP0_SS1), + GPIO_FN(SP0_SS2), + GPIO_FN(SP0_SS3), + GPIO_FN(DREQ0), + GPIO_FN(DACK0), + GPIO_FN(TEND0), /* PTE (mobule: RMII) */ - PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK), + GPIO_FN(RMII0_CRS_DV), + GPIO_FN(RMII0_TXD1), + GPIO_FN(RMII0_TXD0), + GPIO_FN(RMII0_TXEN), + GPIO_FN(RMII0_REFCLK), + GPIO_FN(RMII0_RXD1), + GPIO_FN(RMII0_RXD0), + GPIO_FN(RMII0_RX_ER), /* PTF (mobule: RMII, SerMux) */ - PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), + GPIO_FN(RMII1_CRS_DV), + GPIO_FN(RMII1_TXD1), + GPIO_FN(RMII1_TXD0), + GPIO_FN(RMII1_TXEN), + GPIO_FN(RMII1_REFCLK), + GPIO_FN(RMII1_RXD1), + GPIO_FN(RMII1_RXD0), + GPIO_FN(RMII1_RX_ER), + GPIO_FN(RAC_RI), /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ - PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK), - PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), - PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), - PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), - PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), - PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), + GPIO_FN(BOOTFMS), + GPIO_FN(BOOTWP), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(SERIRQ), + GPIO_FN(WDTOVF), + GPIO_FN(LPCPD), + GPIO_FN(LDRQ), + GPIO_FN(MMCCLK), + GPIO_FN(MMCCMD), /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ - PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), - PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_WP, WP_MARK), - PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), + GPIO_FN(SP1_MOSI), + GPIO_FN(SP1_MISO), + GPIO_FN(SP1_SCK), + GPIO_FN(SP1_SCK_FB), + GPIO_FN(SP1_SS0), + GPIO_FN(SP1_SS1), + GPIO_FN(WP), + GPIO_FN(FMS0), + GPIO_FN(TEND1), + GPIO_FN(DREQ1), + GPIO_FN(DACK1), + GPIO_FN(ADTRG1), + GPIO_FN(ADTRG0), /* PTI (mobule: LBSC, SDHI) */ - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), - PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), - PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), - PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), - PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), - PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), - PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(SD_WP), + GPIO_FN(SD_CD), + GPIO_FN(SD_CLK), + GPIO_FN(SD_CMD), + GPIO_FN(SD_D3), + GPIO_FN(SD_D2), + GPIO_FN(SD_D1), + GPIO_FN(SD_D0), /* PTJ (mobule: SCIF234, SERMUX) */ - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + GPIO_FN(RTS3), + GPIO_FN(CTS3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(RTS4), + GPIO_FN(RXD4), + GPIO_FN(TXD4), /* PTK (mobule: SERMUX, LBSC, SCIF) */ - PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), - PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK), - PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), - PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), - PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), - PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + GPIO_FN(COM2_TXD), + GPIO_FN(COM2_RXD), + GPIO_FN(COM2_RTS), + GPIO_FN(COM2_CTS), + GPIO_FN(COM2_DTR), + GPIO_FN(COM2_DSR), + GPIO_FN(COM2_DCD), + GPIO_FN(CLKOUT), + GPIO_FN(SCK2), + GPIO_FN(SCK4), + GPIO_FN(SCK3), /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ - PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), - PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), - PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), - PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), - PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), - PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), - PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), - PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + GPIO_FN(RAC_RXD), + GPIO_FN(RAC_RTS), + GPIO_FN(RAC_CTS), + GPIO_FN(RAC_DTR), + GPIO_FN(RAC_DSR), + GPIO_FN(RAC_DCD), + GPIO_FN(RAC_TXD), + GPIO_FN(RXD2), + GPIO_FN(CS5), + GPIO_FN(CS6), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDCK), + GPIO_FN(TXD2), /* PTM (mobule: LBSC, IIC) */ - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), - PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), - PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), - PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), + GPIO_FN(CS4), + GPIO_FN(RD), + GPIO_FN(WE0), + GPIO_FN(CS0), + GPIO_FN(SDA6), + GPIO_FN(SCL6), + GPIO_FN(SDA7), + GPIO_FN(SCL7), /* PTN (mobule: USB, JMC, SGPIO, WDT) */ - PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK), - PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK), - PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), - PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), - PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), - PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK), + GPIO_FN(VBUS_EN), + GPIO_FN(VBUS_OC), + GPIO_FN(JMCTCK), + GPIO_FN(JMCTMS), + GPIO_FN(JMCTDO), + GPIO_FN(JMCTDI), + GPIO_FN(JMCTRST), + GPIO_FN(SGPIO1_CLK), + GPIO_FN(SGPIO1_LOAD), + GPIO_FN(SGPIO1_DI), + GPIO_FN(SGPIO1_DO), + GPIO_FN(SUB_CLKIN), /* PTO (mobule: SGPIO, SerMux) */ - PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK), - PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), + GPIO_FN(SGPIO0_CLK), + GPIO_FN(SGPIO0_LOAD), + GPIO_FN(SGPIO0_DI), + GPIO_FN(SGPIO0_DO), + GPIO_FN(SGPIO2_CLK), + GPIO_FN(SGPIO2_LOAD), + GPIO_FN(SGPIO2_DI), + GPIO_FN(SGPIO2_DO), + GPIO_FN(COM1_TXD), + GPIO_FN(COM1_RXD), + GPIO_FN(COM1_RTS), + GPIO_FN(COM1_CTS), /* PTP (mobule: EVC, ADC) */ /* PTQ (mobule: LPC) */ - PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), - PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK), - PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK), - PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK), - PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK), - PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK), - PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK), + GPIO_FN(LAD3), + GPIO_FN(LAD2), + GPIO_FN(LAD1), + GPIO_FN(LAD0), + GPIO_FN(LFRAME), + GPIO_FN(LRESET), + GPIO_FN(LCLK), /* PTR (mobule: GRA, IIC) */ - PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK), - PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK), - PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK), - PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + GPIO_FN(DDC3), + GPIO_FN(DDC2), + GPIO_FN(SDA8), + GPIO_FN(SCL8), + GPIO_FN(SDA2), + GPIO_FN(SCL2), + GPIO_FN(SDA1), + GPIO_FN(SCL1), + GPIO_FN(SDA0), + GPIO_FN(SCL0), /* PTS (mobule: GRA, IIC) */ - PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK), - PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK), - PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK), - PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK), - PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK), - PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK), - PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK), - PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK), - PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), - PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), + GPIO_FN(DDC1), + GPIO_FN(DDC0), + GPIO_FN(SDA9), + GPIO_FN(SCL9), + GPIO_FN(SDA5), + GPIO_FN(SCL5), + GPIO_FN(SDA4), + GPIO_FN(SCL4), + GPIO_FN(SDA3), + GPIO_FN(SCL3), /* PTT (mobule: PWMX, AUD) */ - PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK), - PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK), - PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK), - PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK), - PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK), - PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK), - PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK), - PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + GPIO_FN(PWMX7), + GPIO_FN(PWMX6), + GPIO_FN(PWMX5), + GPIO_FN(PWMX4), + GPIO_FN(PWMX3), + GPIO_FN(PWMX2), + GPIO_FN(PWMX1), + GPIO_FN(PWMX0), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), + GPIO_FN(STATUS1), + GPIO_FN(STATUS0), /* PTU (mobule: LPC, APM) */ - PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), - PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK), - PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK), - PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK), - PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK), - PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK), - PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK), - PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK), - PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK), + GPIO_FN(LGPIO7), + GPIO_FN(LGPIO6), + GPIO_FN(LGPIO5), + GPIO_FN(LGPIO4), + GPIO_FN(LGPIO3), + GPIO_FN(LGPIO2), + GPIO_FN(LGPIO1), + GPIO_FN(LGPIO0), + GPIO_FN(APMONCTL_O), + GPIO_FN(APMPWBTOUT_O), + GPIO_FN(APMSCI_O), + GPIO_FN(APMVDDON), + GPIO_FN(APMSLPBTN), + GPIO_FN(APMPWRBTN), + GPIO_FN(APMS5N), + GPIO_FN(APMS3N), /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A18, A18_MARK), - PINMUX_GPIO(GPIO_FN_A17, A17_MARK), - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK), - PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), - PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A18), + GPIO_FN(A17), + GPIO_FN(A16), + GPIO_FN(COM2_RI), + GPIO_FN(R_SPI_MOSI), + GPIO_FN(R_SPI_MISO), + GPIO_FN(R_SPI_RSPCK), + GPIO_FN(R_SPI_SSL0), + GPIO_FN(R_SPI_SSL1), + GPIO_FN(EVENT7), + GPIO_FN(EVENT6), + GPIO_FN(VBIOS_DI), + GPIO_FN(VBIOS_DO), + GPIO_FN(VBIOS_CLK), + GPIO_FN(VBIOS_CS), /* PTW (mobule: LBSC, EVC, SCIF) */ - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_A15, A15_MARK), - PINMUX_GPIO(GPIO_FN_A14, A14_MARK), - PINMUX_GPIO(GPIO_FN_A13, A13_MARK), - PINMUX_GPIO(GPIO_FN_A12, A12_MARK), - PINMUX_GPIO(GPIO_FN_A11, A11_MARK), - PINMUX_GPIO(GPIO_FN_A10, A10_MARK), - PINMUX_GPIO(GPIO_FN_A9, A9_MARK), - PINMUX_GPIO(GPIO_FN_A8, A8_MARK), - PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), - PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), - PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), - PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), - PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), - PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), - PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), - PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), + GPIO_FN(A16), + GPIO_FN(A15), + GPIO_FN(A14), + GPIO_FN(A13), + GPIO_FN(A12), + GPIO_FN(A11), + GPIO_FN(A10), + GPIO_FN(A9), + GPIO_FN(A8), + GPIO_FN(EVENT5), + GPIO_FN(EVENT4), + GPIO_FN(EVENT3), + GPIO_FN(EVENT2), + GPIO_FN(EVENT1), + GPIO_FN(EVENT0), + GPIO_FN(CTS4), + GPIO_FN(CTS2), /* PTX (mobule: LBSC) */ - PINMUX_GPIO(GPIO_FN_A7, A7_MARK), - PINMUX_GPIO(GPIO_FN_A6, A6_MARK), - PINMUX_GPIO(GPIO_FN_A5, A5_MARK), - PINMUX_GPIO(GPIO_FN_A4, A4_MARK), - PINMUX_GPIO(GPIO_FN_A3, A3_MARK), - PINMUX_GPIO(GPIO_FN_A2, A2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), - PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), - PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + GPIO_FN(A7), + GPIO_FN(A6), + GPIO_FN(A5), + GPIO_FN(A4), + GPIO_FN(A3), + GPIO_FN(A2), + GPIO_FN(A1), + GPIO_FN(A0), + GPIO_FN(RTS2), + GPIO_FN(SIM_D), + GPIO_FN(SIM_CLK), + GPIO_FN(SIM_RST), /* PTY (mobule: LBSC) */ - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), /* PTZ (mobule: eMMC, ONFI) */ - PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK), + GPIO_FN(MMCDAT7), + GPIO_FN(MMCDAT6), + GPIO_FN(MMCDAT5), + GPIO_FN(MMCDAT4), + GPIO_FN(MMCDAT3), + GPIO_FN(MMCDAT2), + GPIO_FN(MMCDAT1), + GPIO_FN(MMCDAT0), + GPIO_FN(ON_DQ7), + GPIO_FN(ON_DQ6), + GPIO_FN(ON_DQ5), + GPIO_FN(ON_DQ4), + GPIO_FN(ON_DQ3), + GPIO_FN(ON_DQ2), + GPIO_FN(ON_DQ1), + GPIO_FN(ON_DQ0), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 3b1825d925bb..2e9d7cbec783 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -847,171 +847,171 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PR0, PR0_DATA), /* FN */ - PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK), - PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK), - PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK), - PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK), - PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK), - PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK), - PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK), - PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK), - PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK), - PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK), - PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK), - PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK), - PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK), - PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK), - PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK), - PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK), - PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK), - PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK), - PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK), - PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK), - PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK), - PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK), - PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK), - PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK), - PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK), - PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK), - PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK), - PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK), - PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK), - PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK), - PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK), - PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK), - PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK), - PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK), - PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK), - PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK), - PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK), - PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK), - PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK), - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), - PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), - PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), - PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK), - PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), - PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK), - PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), - PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK), - PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), - PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK), - PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), - PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), - PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), - PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK), - PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK), - PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK), - PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK), - PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK), - PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK), - PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK), - PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK), - PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK), - PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK), - PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK), - PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK), - PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + GPIO_FN(D63_AD31), + GPIO_FN(D62_AD30), + GPIO_FN(D61_AD29), + GPIO_FN(D60_AD28), + GPIO_FN(D59_AD27), + GPIO_FN(D58_AD26), + GPIO_FN(D57_AD25), + GPIO_FN(D56_AD24), + GPIO_FN(D55_AD23), + GPIO_FN(D54_AD22), + GPIO_FN(D53_AD21), + GPIO_FN(D52_AD20), + GPIO_FN(D51_AD19), + GPIO_FN(D50_AD18), + GPIO_FN(D49_AD17_DB5), + GPIO_FN(D48_AD16_DB4), + GPIO_FN(D47_AD15_DB3), + GPIO_FN(D46_AD14_DB2), + GPIO_FN(D45_AD13_DB1), + GPIO_FN(D44_AD12_DB0), + GPIO_FN(D43_AD11_DG5), + GPIO_FN(D42_AD10_DG4), + GPIO_FN(D41_AD9_DG3), + GPIO_FN(D40_AD8_DG2), + GPIO_FN(D39_AD7_DG1), + GPIO_FN(D38_AD6_DG0), + GPIO_FN(D37_AD5_DR5), + GPIO_FN(D36_AD4_DR4), + GPIO_FN(D35_AD3_DR3), + GPIO_FN(D34_AD2_DR2), + GPIO_FN(D33_AD1_DR1), + GPIO_FN(D32_AD0_DR0), + GPIO_FN(REQ1), + GPIO_FN(REQ2), + GPIO_FN(REQ3), + GPIO_FN(GNT1), + GPIO_FN(GNT2), + GPIO_FN(GNT3), + GPIO_FN(MMCCLK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(SCIF1_SCK), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_TXD), + GPIO_FN(SCIF0_CTS), + GPIO_FN(INTD), + GPIO_FN(FCE), + GPIO_FN(SCIF0_RTS), + GPIO_FN(HSPI_CS), + GPIO_FN(FSE), + GPIO_FN(SCIF0_SCK), + GPIO_FN(HSPI_CLK), + GPIO_FN(FRE), + GPIO_FN(SCIF0_RXD), + GPIO_FN(HSPI_RX), + GPIO_FN(FRB), + GPIO_FN(SCIF0_TXD), + GPIO_FN(HSPI_TX), + GPIO_FN(FWE), + GPIO_FN(SCIF5_TXD), + GPIO_FN(HAC1_SYNC), + GPIO_FN(SSI1_WS), + GPIO_FN(SIOF_TXD_PJ), + GPIO_FN(HAC0_SDOUT), + GPIO_FN(SSI0_SDATA), + GPIO_FN(SIOF_RXD_PJ), + GPIO_FN(HAC0_SDIN), + GPIO_FN(SSI0_SCK), + GPIO_FN(SIOF_SYNC_PJ), + GPIO_FN(HAC0_SYNC), + GPIO_FN(SSI0_WS), + GPIO_FN(SIOF_MCLK_PJ), + GPIO_FN(HAC_RES), + GPIO_FN(SIOF_SCK_PJ), + GPIO_FN(HAC0_BITCLK), + GPIO_FN(SSI0_CLK), + GPIO_FN(HAC1_BITCLK), + GPIO_FN(SSI1_CLK), + GPIO_FN(TCLK), + GPIO_FN(IOIS16), + GPIO_FN(STATUS0), + GPIO_FN(DRAK0_PK3), + GPIO_FN(STATUS1), + GPIO_FN(DRAK1_PK2), + GPIO_FN(DACK2), + GPIO_FN(SCIF2_TXD), + GPIO_FN(MMCCMD), + GPIO_FN(SIOF_TXD_PK), + GPIO_FN(DACK3), + GPIO_FN(SCIF2_SCK), + GPIO_FN(MMCDAT), + GPIO_FN(SIOF_SCK_PK), + GPIO_FN(DREQ0), + GPIO_FN(DREQ1), + GPIO_FN(DRAK0_PK1), + GPIO_FN(DRAK1_PK0), + GPIO_FN(DREQ2), + GPIO_FN(INTB), + GPIO_FN(DREQ3), + GPIO_FN(INTC), + GPIO_FN(DRAK2), + GPIO_FN(CE2A), + GPIO_FN(IRL4), + GPIO_FN(FD4), + GPIO_FN(IRL5), + GPIO_FN(FD5), + GPIO_FN(IRL6), + GPIO_FN(FD6), + GPIO_FN(IRL7), + GPIO_FN(FD7), + GPIO_FN(DRAK3), + GPIO_FN(CE2B), + GPIO_FN(BREQ_BSACK), + GPIO_FN(BACK_BSREQ), + GPIO_FN(SCIF5_RXD), + GPIO_FN(HAC1_SDIN), + GPIO_FN(SSI1_SCK), + GPIO_FN(SCIF5_SCK), + GPIO_FN(HAC1_SDOUT), + GPIO_FN(SSI1_SDATA), + GPIO_FN(SCIF3_TXD), + GPIO_FN(FCLE), + GPIO_FN(SCIF3_RXD), + GPIO_FN(FALE), + GPIO_FN(SCIF3_SCK), + GPIO_FN(FD0), + GPIO_FN(SCIF4_TXD), + GPIO_FN(FD1), + GPIO_FN(SCIF4_RXD), + GPIO_FN(FD2), + GPIO_FN(SCIF4_SCK), + GPIO_FN(FD3), + GPIO_FN(DEVSEL_DCLKOUT), + GPIO_FN(STOP_CDE), + GPIO_FN(LOCK_ODDF), + GPIO_FN(TRDY_DISPL), + GPIO_FN(IRDY_HSYNC), + GPIO_FN(PCIFRAME_VSYNC), + GPIO_FN(INTA), + GPIO_FN(GNT0_GNTIN), + GPIO_FN(REQ0_REQOUT), + GPIO_FN(PERR), + GPIO_FN(SERR), + GPIO_FN(WE7_CBE3), + GPIO_FN(WE6_CBE2), + GPIO_FN(WE5_CBE1), + GPIO_FN(WE4_CBE0), + GPIO_FN(SCIF2_RXD), + GPIO_FN(SIOF_RXD), + GPIO_FN(MRESETOUT), + GPIO_FN(IRQOUT), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 1e18b58f9e5f..c9d8f500a6d3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -507,142 +507,142 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), /* FN */ - PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK), - PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK), - PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK), - PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK), - PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK), - PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK), - PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), - PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), - PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK), - PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK), - PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK), - PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK), - PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), - PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), - PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK), - PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK), - PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK), - PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK), - PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK), - PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), + GPIO_FN(CDE), + GPIO_FN(ETH_MAGIC), + GPIO_FN(DISP), + GPIO_FN(ETH_LINK), + GPIO_FN(DR5), + GPIO_FN(ETH_TX_ER), + GPIO_FN(DR4), + GPIO_FN(ETH_TX_EN), + GPIO_FN(DR3), + GPIO_FN(ETH_TXD3), + GPIO_FN(DR2), + GPIO_FN(ETH_TXD2), + GPIO_FN(DR1), + GPIO_FN(ETH_TXD1), + GPIO_FN(DR0), + GPIO_FN(ETH_TXD0), + GPIO_FN(VSYNC), + GPIO_FN(HSPI_CLK), + GPIO_FN(ODDF), + GPIO_FN(HSPI_CS), + GPIO_FN(DG5), + GPIO_FN(ETH_MDIO), + GPIO_FN(DG4), + GPIO_FN(ETH_RX_CLK), + GPIO_FN(DG3), + GPIO_FN(ETH_MDC), + GPIO_FN(DG2), + GPIO_FN(ETH_COL), + GPIO_FN(DG1), + GPIO_FN(ETH_TX_CLK), + GPIO_FN(DG0), + GPIO_FN(ETH_CRS), + GPIO_FN(DCLKIN), + GPIO_FN(HSPI_RX), + GPIO_FN(HSYNC), + GPIO_FN(HSPI_TX), + GPIO_FN(DB5), + GPIO_FN(ETH_RXD3), + GPIO_FN(DB4), + GPIO_FN(ETH_RXD2), + GPIO_FN(DB3), + GPIO_FN(ETH_RXD1), + GPIO_FN(DB2), + GPIO_FN(ETH_RXD0), + GPIO_FN(DB1), + GPIO_FN(ETH_RX_DV), + GPIO_FN(DB0), + GPIO_FN(ETH_RX_ER), + GPIO_FN(DCLKOUT), + GPIO_FN(SCIF1_SCK), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_TXD), + GPIO_FN(DACK1), + GPIO_FN(BACK), + GPIO_FN(FALE), + GPIO_FN(DACK0), + GPIO_FN(FCLE), + GPIO_FN(DREQ1), + GPIO_FN(BREQ), + GPIO_FN(USB_OVC1), + GPIO_FN(DREQ0), + GPIO_FN(USB_OVC0), + GPIO_FN(USB_PENC1), + GPIO_FN(USB_PENC0), + GPIO_FN(HAC1_SDOUT), + GPIO_FN(SSI1_SDATA), + GPIO_FN(SDIF1CMD), + GPIO_FN(HAC1_SDIN), + GPIO_FN(SSI1_SCK), + GPIO_FN(SDIF1CD), + GPIO_FN(HAC1_SYNC), + GPIO_FN(SSI1_WS), + GPIO_FN(SDIF1WP), + GPIO_FN(HAC1_BITCLK), + GPIO_FN(SSI1_CLK), + GPIO_FN(SDIF1CLK), + GPIO_FN(HAC0_SDOUT), + GPIO_FN(SSI0_SDATA), + GPIO_FN(SDIF1D3), + GPIO_FN(HAC0_SDIN), + GPIO_FN(SSI0_SCK), + GPIO_FN(SDIF1D2), + GPIO_FN(HAC0_SYNC), + GPIO_FN(SSI0_WS), + GPIO_FN(SDIF1D1), + GPIO_FN(HAC0_BITCLK), + GPIO_FN(SSI0_CLK), + GPIO_FN(SDIF1D0), + GPIO_FN(SCIF3_SCK), + GPIO_FN(SSI2_SDATA), + GPIO_FN(SCIF3_RXD), + GPIO_FN(TCLK), + GPIO_FN(SSI2_SCK), + GPIO_FN(SCIF3_TXD), + GPIO_FN(HAC_RES), + GPIO_FN(SSI2_WS), + GPIO_FN(DACK3), + GPIO_FN(SDIF0CMD), + GPIO_FN(DACK2), + GPIO_FN(SDIF0CD), + GPIO_FN(DREQ3), + GPIO_FN(SDIF0WP), + GPIO_FN(SCIF0_CTS), + GPIO_FN(DREQ2), + GPIO_FN(SDIF0CLK), + GPIO_FN(SCIF0_RTS), + GPIO_FN(IRL7), + GPIO_FN(SDIF0D3), + GPIO_FN(SCIF0_SCK), + GPIO_FN(IRL6), + GPIO_FN(SDIF0D2), + GPIO_FN(SCIF0_RXD), + GPIO_FN(IRL5), + GPIO_FN(SDIF0D1), + GPIO_FN(SCIF0_TXD), + GPIO_FN(IRL4), + GPIO_FN(SDIF0D0), + GPIO_FN(SCIF5_SCK), + GPIO_FN(FRB), + GPIO_FN(SCIF5_RXD), + GPIO_FN(IOIS16), + GPIO_FN(SCIF5_TXD), + GPIO_FN(CE2B), + GPIO_FN(DRAK3), + GPIO_FN(CE2A), + GPIO_FN(SCIF4_SCK), + GPIO_FN(DRAK2), + GPIO_FN(SSI3_WS), + GPIO_FN(SCIF4_RXD), + GPIO_FN(DRAK1), + GPIO_FN(SSI3_SDATA), + GPIO_FN(FSTATUS), + GPIO_FN(SCIF4_TXD), + GPIO_FN(DRAK0), + GPIO_FN(SSI3_SCK), + GPIO_FN(FSE), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index ccf6918b03c6..04e89407aecd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -386,68 +386,68 @@ static struct pinmux_gpio shx3_pinmux_gpios[] = { PINMUX_GPIO(GPIO_PH0, PH0_DATA), /* FN */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK), - PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK), - PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), - PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK), - PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK), - PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK), - PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(BACK), + GPIO_FN(BREQ), + GPIO_FN(WE3), + GPIO_FN(WE2), + GPIO_FN(CS6), + GPIO_FN(CS5), + GPIO_FN(CS4), + GPIO_FN(CLKOUTENB), + GPIO_FN(DACK3), + GPIO_FN(DACK2), + GPIO_FN(DACK1), + GPIO_FN(DACK0), + GPIO_FN(DREQ3), + GPIO_FN(DREQ2), + GPIO_FN(DREQ1), + GPIO_FN(DREQ0), + GPIO_FN(IRQ3), + GPIO_FN(IRQ2), + GPIO_FN(IRQ1), + GPIO_FN(IRQ0), + GPIO_FN(DRAK3), + GPIO_FN(DRAK2), + GPIO_FN(DRAK1), + GPIO_FN(DRAK0), + GPIO_FN(SCK3), + GPIO_FN(SCK2), + GPIO_FN(SCK1), + GPIO_FN(SCK0), + GPIO_FN(IRL3), + GPIO_FN(IRL2), + GPIO_FN(IRL1), + GPIO_FN(IRL0), + GPIO_FN(TXD3), + GPIO_FN(TXD2), + GPIO_FN(TXD1), + GPIO_FN(TXD0), + GPIO_FN(RXD3), + GPIO_FN(RXD2), + GPIO_FN(RXD1), + GPIO_FN(RXD0), + GPIO_FN(CE2B), + GPIO_FN(CE2A), + GPIO_FN(IOIS16), + GPIO_FN(STATUS1), + GPIO_FN(STATUS0), + GPIO_FN(IRQOUT), }; static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { From d7a7ca5781fa2ac40319acc7125c487db5b26d91 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 28 Nov 2012 17:51:00 +0100 Subject: [PATCH 068/307] sh-pfc: Replace first_gpio and last_gpio with nr_gpios The SoC information first_gpio field is always equal to 0, and the last_gpio field is the index of the last entry in the pinmux_gpios array. Replace the first_gpio and last_gpio fields by a nr_gpios field, and initialize it to ARRAY_SIZE(pinmux_gpios). Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 2 +- drivers/pinctrl/sh-pfc/gpio.c | 11 ++++------- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7203.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7720.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7722.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7723.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7724.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7734.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7757.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7785.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-sh7786.c | 5 ++--- drivers/pinctrl/sh-pfc/pfc-shx3.c | 3 +-- drivers/pinctrl/sh-pfc/pinctrl.c | 16 +++++----------- drivers/pinctrl/sh-pfc/sh_pfc.h | 4 ++-- 20 files changed, 43 insertions(+), 68 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 970ddff2b0b6..1b86a906a97b 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -260,7 +260,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) struct pinmux_data_reg *drp; int k; - for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++) + for (k = 0; k < pfc->info->nr_gpios; k++) sh_pfc_setup_data_reg(pfc, k); k = 0; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index a535075c8b69..f46f06997b99 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -130,12 +130,10 @@ static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) gc->set = sh_gpio_set; gc->to_irq = sh_gpio_to_irq; - WARN_ON(pfc->info->first_gpio != 0); /* needs testing */ - gc->label = pfc->info->name; gc->owner = THIS_MODULE; - gc->base = pfc->info->first_gpio; - gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1; + gc->base = 0; + gc->ngpio = pfc->info->nr_gpios; } int sh_pfc_register_gpiochip(struct sh_pfc *pfc) @@ -157,9 +155,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) pfc->gpio = chip; - pr_info("%s handling gpio %d -> %d\n", - pfc->info->name, pfc->info->first_gpio, - pfc->info->last_gpio); + pr_info("%s handling gpio 0 -> %u\n", + pfc->info->name, pfc->info->nr_gpios - 1); return 0; } diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 214788c4a606..c189a86fe8d3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2597,10 +2597,9 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = { .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 13feaa0c0eb7..16ec97a31b38 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2612,10 +2612,9 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_SCK4_B, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index 22be49b3bd38..6cc67017e8fe 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -1580,10 +1580,9 @@ struct sh_pfc_soc_info sh7203_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_LCD_DATA0, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index ebe9c7ceb575..c2ecc65ff252 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -2119,10 +2119,9 @@ struct sh_pfc_soc_info sh7264_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA3, - .last_gpio = GPIO_FN_LCD_M_DISP, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 87cb6933e02b..2013f4fa24f2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -2822,10 +2822,9 @@ struct sh_pfc_soc_info sh7269_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA1, - .last_gpio = GPIO_FN_LCD_M_DISP, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index d44e7f02069b..332cf34a867f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -1643,10 +1643,9 @@ struct sh_pfc_soc_info sh7372_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_SDENC_DV_CLKI, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 232731bcdd22..d5ee0f7680af 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2779,10 +2779,9 @@ struct sh_pfc_soc_info sh73a0_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_FSIAISLD_PU, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index e2e4520a14c4..8646237e9dff 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -1223,10 +1223,9 @@ struct sh_pfc_soc_info sh7720_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_STATUS1, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 225fa96b6a21..194ae3de5a05 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -1767,10 +1767,9 @@ struct sh_pfc_soc_info sh7722_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_KEYOUT5_IN5, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 49fd5c82e3cf..f31aa4f6b165 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -1891,10 +1891,9 @@ struct sh_pfc_soc_info sh7723_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_IDEA0, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 054b700a7e01..64b69b709f0f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -2213,10 +2213,9 @@ struct sh_pfc_soc_info sh7724_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_INTC_IRQ0, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index 23d76d262c32..d67a572de822 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -2463,10 +2463,9 @@ struct sh_pfc_soc_info sh7734_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_ST_CLKOUT, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index ffbd8b7ee72e..7fc1310faf9c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -2270,10 +2270,9 @@ struct sh_pfc_soc_info sh7757_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA0, - .last_gpio = GPIO_FN_ON_DQ0, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 2e9d7cbec783..4bde4b56de58 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -1292,10 +1292,9 @@ struct sh_pfc_soc_info sh7785_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_IRQOUT, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index c9d8f500a6d3..9a42d25312d9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -825,10 +825,9 @@ struct sh_pfc_soc_info sh7786_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_IRL4, - .gpios = pinmux_gpios, + .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index 04e89407aecd..b23f5f9a8429 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -572,9 +572,8 @@ struct sh_pfc_soc_info shx3_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_STATUS0, .gpios = shx3_pinmux_gpios, + .nr_gpios = ARRAY_SIZE(shx3_pinmux_gpios), .gpio_data = shx3_pinmux_data, .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), .cfg_regs = shx3_pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 4ce2753cb2df..908b5362b1cd 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -336,7 +336,7 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { int i; - pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1; + pmx->nr_pads = pfc->info->nr_gpios; pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, GFP_KERNEL); @@ -345,17 +345,11 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) return -ENOMEM; } - /* - * We don't necessarily have a 1:1 mapping between pin and linux - * GPIO number, as the latter maps to the associated enum_id. - * Care needs to be taken to translate back to pin space when - * dealing with any pin configurations. - */ for (i = 0; i < pmx->nr_pads; i++) { struct pinctrl_pin_desc *pin = pmx->pads + i; struct pinmux_gpio *gpio = pfc->info->gpios + i; - pin->number = pfc->info->first_gpio + i; + pin->number = i; pin->name = gpio->name; /* XXX */ @@ -421,9 +415,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) pmx->range.name = DRV_NAME, pmx->range.id = 0; - pmx->range.npins = pfc->info->last_gpio - pfc->info->first_gpio + 1; - pmx->range.base = pfc->info->first_gpio; - pmx->range.pin_base = pfc->info->first_gpio; + pmx->range.npins = pfc->info->nr_gpios; + pmx->range.base = 0; + pmx->range.pin_base = 0; pinctrl_add_gpio_range(pmx->pctl, &pmx->range); diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 13049c4c8d30..67fe91b051cb 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -99,9 +99,9 @@ struct sh_pfc_soc_info { struct pinmux_range mark; struct pinmux_range function; - unsigned first_gpio, last_gpio; - struct pinmux_gpio *gpios; + unsigned int nr_gpios; + struct pinmux_cfg_reg *cfg_regs; struct pinmux_data_reg *data_regs; From caa5bac3b4749ae3dca1db33d648280197f91a56 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 29 Nov 2012 12:24:51 +0100 Subject: [PATCH 069/307] sh-pfc: Replace SoC info data and mark ranges with a number of pins The data and mark ranges are only used to check whether a GPIO corresponds to a real pin or a function. As pins come first in the list of GPIOs and in the platform-specific GPIO enumerations, we can replace the data and mark ranges by a number of pins. Add an nr_pins field to struct sh_pfc_soc_info to store the number of pins implemented by the SoC, remove the data and mark range fields and introduce sh_pfc_gpio_is_pin() and sh_pfc_gpio_is_function() functions to replace range-based checks. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 27 +++++++++++++++++++-------- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 5 +---- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7203.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7720.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7722.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7723.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7724.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7734.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7757.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7785.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-sh7786.c | 3 +-- drivers/pinctrl/sh-pfc/pfc-shx3.c | 3 +-- drivers/pinctrl/sh-pfc/sh_pfc.h | 3 +-- 18 files changed, 36 insertions(+), 44 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 1b86a906a97b..e7ad0d93fed4 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -89,6 +89,18 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) return 1; } +static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio) +{ + return (gpio < pfc->info->nr_pins) && + (pfc->info->gpios[gpio].enum_id != 0); +} + +static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio) +{ + return (gpio >= pfc->info->nr_pins) && (gpio < pfc->info->nr_gpios) && + (pfc->info->gpios[gpio].enum_id != 0); +} + static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned long reg_width) { @@ -226,7 +238,7 @@ static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) struct pinmux_data_reg *data_reg; int k, n; - if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) + if (!sh_pfc_gpio_is_pin(pfc, gpio)) return -1; k = 0; @@ -260,7 +272,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) struct pinmux_data_reg *drp; int k; - for (k = 0; k < pfc->info->nr_gpios; k++) + for (k = 0; k < pfc->info->nr_pins; k++) sh_pfc_setup_data_reg(pfc, k); k = 0; @@ -282,7 +294,7 @@ int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; int k, n; - if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) + if (!sh_pfc_gpio_is_pin(pfc, gpio)) return -1; k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; @@ -344,11 +356,10 @@ int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, pinmux_enum_t *data = pfc->info->gpio_data; int k; - if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) { - if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) { - pr_err("non data/mark enum_id for gpio %d\n", gpio); - return -1; - } + if (!sh_pfc_gpio_is_pin(pfc, gpio) && + !sh_pfc_gpio_is_function(pfc, gpio)) { + pr_err("non data/mark enum_id for gpio %d\n", gpio); + return -1; } if (pos) { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index c189a86fe8d3..f1ef9f77dd83 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2582,8 +2582,6 @@ static struct pinmux_irq pinmux_irqs[] = { struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, - PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, @@ -2592,12 +2590,11 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = { PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, - PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PORT211 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 16ec97a31b38..c8018ce0e894 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2606,13 +2606,12 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = { .unlock_reg = 0xfffc0000, /* PMMR */ .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_GP_6_8 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index 6cc67017e8fe..07377e4920a3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -1574,13 +1574,12 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7203_pinmux_info = { .name = "sh7203_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PF0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index c2ecc65ff252..21b5899f32cb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -2113,13 +2113,12 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7264_pinmux_info = { .name = "sh7264_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PK0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 2013f4fa24f2..b722de1e7b28 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -2816,13 +2816,12 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7269_pinmux_info = { .name = "sh7269_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PJ0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 332cf34a867f..0c56f579fc0f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -1635,15 +1635,14 @@ static struct pinmux_irq pinmux_irqs[] = { struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PORT190 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index d5ee0f7680af..6573dbab7b27 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2771,15 +2771,14 @@ static struct pinmux_irq pinmux_irqs[] = { struct sh_pfc_soc_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PORT309 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 8646237e9dff..48771779946c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -1216,14 +1216,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7720_pinmux_info = { .name = "sh7720_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PTV0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 194ae3de5a05..7cedac6e735d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -1759,15 +1759,14 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7722_pinmux_info = { .name = "sh7722_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PTZ1 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index f31aa4f6b165..160edf01c04b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -1884,14 +1884,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7723_pinmux_info = { .name = "sh7723_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PTZ0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 64b69b709f0f..269f33d6eb0a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -2206,14 +2206,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7724_pinmux_info = { .name = "sh7724_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PTZ0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index d67a572de822..be5cca66815e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -2457,13 +2457,12 @@ struct sh_pfc_soc_info sh7734_pinmux_info = { .unlock_reg = 0xFFFC0000, .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_GP_5_11 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index 7fc1310faf9c..d95f5b8ae36f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -2263,14 +2263,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7757_pinmux_info = { .name = "sh7757_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PTZ7 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 4bde4b56de58..0d4c6de2c0be 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -1285,14 +1285,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7785_pinmux_info = { .name = "sh7785_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PR0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 9a42d25312d9..2981d0be82a5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -818,14 +818,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7786_pinmux_info = { .name = "sh7786_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = pinmux_gpios, + .nr_pins = GPIO_PJ0 + 1, .nr_gpios = ARRAY_SIZE(pinmux_gpios), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index b23f5f9a8429..e985099b7777 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -565,14 +565,13 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = { struct sh_pfc_soc_info shx3_pinmux_info = { .name = "shx3_pfc", .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .gpios = shx3_pinmux_gpios, + .nr_pins = GPIO_PH0 + 1, .nr_gpios = ARRAY_SIZE(shx3_pinmux_gpios), .gpio_data = shx3_pinmux_data, .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 67fe91b051cb..c50fb51a7fac 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -91,15 +91,14 @@ struct pinmux_range { struct sh_pfc_soc_info { char *name; pinmux_enum_t reserved_id; - struct pinmux_range data; struct pinmux_range input; struct pinmux_range input_pd; struct pinmux_range input_pu; struct pinmux_range output; - struct pinmux_range mark; struct pinmux_range function; struct pinmux_gpio *gpios; + unsigned int nr_pins; unsigned int nr_gpios; struct pinmux_cfg_reg *cfg_regs; From 53f374b13413c072ec4717703479ef7d5b632f90 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 29 Nov 2012 16:18:24 +0100 Subject: [PATCH 070/307] sh-pfc: Remove unused sh_pfc_soc_info reserved_id field The field is unused, remove it. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 1 - drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7203.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7264.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7269.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7372.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7720.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7722.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7723.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7724.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7734.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7757.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7785.c | 1 - drivers/pinctrl/sh-pfc/pfc-sh7786.c | 1 - drivers/pinctrl/sh-pfc/pfc-shx3.c | 1 - drivers/pinctrl/sh-pfc/sh_pfc.h | 1 - 17 files changed, 17 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index f1ef9f77dd83..957502ebcc5b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2581,7 +2581,6 @@ static struct pinmux_irq pinmux_irqs[] = { struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index c8018ce0e894..bd5a70d5247f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2605,7 +2605,6 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = { .unlock_reg = 0xfffc0000, /* PMMR */ - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index 07377e4920a3..ee972f0bc696 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -1573,7 +1573,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7203_pinmux_info = { .name = "sh7203_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 21b5899f32cb..44066dec1c3f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -2112,7 +2112,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7264_pinmux_info = { .name = "sh7264_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index b722de1e7b28..072c7d5da512 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -2815,7 +2815,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7269_pinmux_info = { .name = "sh7269_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 0c56f579fc0f..c11207442415 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -1634,7 +1634,6 @@ static struct pinmux_irq pinmux_irqs[] = { struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 6573dbab7b27..e41aa21edac0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2770,7 +2770,6 @@ static struct pinmux_irq pinmux_irqs[] = { struct sh_pfc_soc_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 48771779946c..294b75858c9e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -1215,7 +1215,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7720_pinmux_info = { .name = "sh7720_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 7cedac6e735d..e7eadaf8e444 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -1758,7 +1758,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7722_pinmux_info = { .name = "sh7722_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 160edf01c04b..06b1d736001d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -1883,7 +1883,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7723_pinmux_info = { .name = "sh7723_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 269f33d6eb0a..41160a3efb40 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -2205,7 +2205,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7724_pinmux_info = { .name = "sh7724_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index be5cca66815e..df32e71625b1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -2456,7 +2456,6 @@ struct sh_pfc_soc_info sh7734_pinmux_info = { .unlock_reg = 0xFFFC0000, - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index d95f5b8ae36f..dd32f347ce5a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -2262,7 +2262,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7757_pinmux_info = { .name = "sh7757_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 0d4c6de2c0be..447bd921b0ea 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -1284,7 +1284,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7785_pinmux_info = { .name = "sh7785_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 2981d0be82a5..dee3cfbe3bbe 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -817,7 +817,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = { struct sh_pfc_soc_info sh7786_pinmux_info = { .name = "sh7786_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index e985099b7777..e59da7999348 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -564,7 +564,6 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = { struct sh_pfc_soc_info shx3_pinmux_info = { .name = "shx3_pfc", - .reserved_id = PINMUX_RESERVED, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index c50fb51a7fac..2627a89273ee 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -90,7 +90,6 @@ struct pinmux_range { struct sh_pfc_soc_info { char *name; - pinmux_enum_t reserved_id; struct pinmux_range input; struct pinmux_range input_pd; struct pinmux_range input_pu; From 380c2ed92412d519c71d8c270d6b073b2c5bfdec Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 29 Nov 2012 02:23:26 +0100 Subject: [PATCH 071/307] sh-pfc: Initialize pinmux_gpio flags statically All function GPIO entries are initialized with the GPIO_FN macro that expands to the PINMUX_GPIO macro, used to initialize real GPIOs. Create a PINMUX_GPIO_FN macro that duplicates PINMUX_GPIO and sets flags to PINMUX_TYPE_FUNCTION and use it in GPIO_FN, and make PINMUX_GPIO set flags to PINMUX_TYPE_GPIO. This removes the need to initialize GPIO flags at runtime and thus simplifies the code, preparing for the GPIO and functions split. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 19 ++----------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 16 +++++++++++++--- 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 908b5362b1cd..682b3a62b080 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -315,22 +315,6 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = { .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, }; -static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, - struct pinmux_gpio *gpio, unsigned offset) -{ - struct pinmux_data_reg *dummy; - int bit; - - gpio->flags &= ~PINMUX_FLAG_TYPE; - - if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0) - gpio->flags |= PINMUX_TYPE_GPIO; - else { - gpio->flags |= PINMUX_TYPE_FUNCTION; - pmx->nr_functions++; - } -} - /* pinmux ranges -> pinctrl pin descs */ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { @@ -356,7 +340,8 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) if (unlikely(!gpio->enum_id)) continue; - sh_pfc_map_one_gpio(pfc, pmx, gpio, i); + if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) + pmx->nr_functions++; } return 0; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 2627a89273ee..e15039504a1c 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -41,8 +41,18 @@ struct pinmux_gpio { const char *name; }; -#define PINMUX_GPIO(gpio, data_or_mark) \ - [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE } +#define PINMUX_GPIO(gpio, data_or_mark) \ + [gpio] = { \ + .name = __stringify(gpio), \ + .enum_id = data_or_mark, \ + .flags = PINMUX_TYPE_GPIO \ + } +#define PINMUX_GPIO_FN(gpio, data_or_mark) \ + [gpio] = { \ + .name = __stringify(gpio), \ + .enum_id = data_or_mark, \ + .flags = PINMUX_TYPE_FUNCTION \ + } #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 @@ -135,7 +145,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) -#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) +#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, str##_MARK) /* helper macro for pinmux_enum_t */ #define PORT_DATA_I(nr) \ From 051fae4bec226b1b139e70d2416b57ce344dba19 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 28 Nov 2012 19:22:18 +0100 Subject: [PATCH 072/307] sh-pfc: Make struct pinmux_gpio enum_id field const This ensures that the field is not modified, which is a prerequisite for the rest of the PFC refactoring work. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index e15039504a1c..6ed7ab9d56d4 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -36,7 +36,7 @@ enum { #define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) struct pinmux_gpio { - pinmux_enum_t enum_id; + const pinmux_enum_t enum_id; pinmux_flag_t flags; const char *name; }; From 2119f7c9afaf4c5fe88e9ffec1f34c5bc6b02f78 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 29 Nov 2012 13:03:53 +0100 Subject: [PATCH 073/307] sh-pfc: Shrink the pinctrl GPIO range to include real GPIOs only As a step towards GPIO function removal, shorten the GPIO range registered with the pinctrl core. Function GPIOs are now handled in the GPIO handlers directly instead of going through the pinctrl API. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 2 +- drivers/pinctrl/sh-pfc/core.h | 1 + drivers/pinctrl/sh-pfc/gpio.c | 57 ++++++++++++++++++++++++++++++-- drivers/pinctrl/sh-pfc/pinctrl.c | 27 ++------------- 4 files changed, 59 insertions(+), 28 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index e7ad0d93fed4..bed2d23e2464 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -95,7 +95,7 @@ static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio) (pfc->info->gpios[gpio].enum_id != 0); } -static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio) +bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio) { return (gpio >= pfc->info->nr_pins) && (gpio < pfc->info->nr_gpios) && (pfc->info->gpios[gpio].enum_id != 0); diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index ba7c33c33599..dceaec0f6277 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -47,6 +47,7 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, unsigned long value); int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp); +bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio); int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, pinmux_enum_t *enum_idp); int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index f46f06997b99..80a50d8a50e7 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -38,12 +38,51 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) static int sh_gpio_request(struct gpio_chip *gc, unsigned offset) { - return pinctrl_request_gpio(offset); + struct sh_pfc *pfc = gpio_to_pfc(gc); + unsigned long flags; + int ret = -EINVAL; + + if (offset < pfc->info->nr_pins) + return pinctrl_request_gpio(offset); + + pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); + + spin_lock_irqsave(&pfc->lock, flags); + + if (!sh_pfc_gpio_is_function(pfc, offset)) + goto done; + + if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, + GPIO_CFG_DRYRUN)) + goto done; + + if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, + GPIO_CFG_REQ)) + goto done; + + ret = 0; + +done: + spin_unlock_irqrestore(&pfc->lock, flags); + return ret; } static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) { - pinctrl_free_gpio(offset); + struct sh_pfc *pfc = gpio_to_pfc(gc); + unsigned long flags; + int pinmux_type; + + if (offset < pfc->info->nr_pins) + return pinctrl_free_gpio(offset); + + spin_lock_irqsave(&pfc->lock, flags); + + pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; + + sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); + + spin_unlock_irqrestore(&pfc->lock, flags); } static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value) @@ -70,12 +109,26 @@ static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio) static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { + struct sh_pfc *pfc = gpio_to_pfc(gc); + + if (offset >= pfc->info->nr_pins) { + /* Function GPIOs can only be requested, never configured. */ + return -EINVAL; + } + return pinctrl_gpio_direction_input(offset); } static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int value) { + struct sh_pfc *pfc = gpio_to_pfc(gc); + + if (offset >= pfc->info->nr_pins) { + /* Function GPIOs can only be requested, never configured. */ + return -EINVAL; + } + sh_gpio_set_value(gpio_to_pfc(gc), offset, value); return pinctrl_gpio_direction_output(offset); diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 682b3a62b080..747ee6487fd7 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -116,21 +116,6 @@ static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, { } -static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset) -{ - if (sh_pfc_config_gpio(pfc, offset, - PINMUX_TYPE_FUNCTION, - GPIO_CFG_DRYRUN) != 0) - return -EINVAL; - - if (sh_pfc_config_gpio(pfc, offset, - PINMUX_TYPE_FUNCTION, - GPIO_CFG_REQ) != 0) - return -EINVAL; - - return 0; -} - static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, int new_type) { @@ -198,19 +183,11 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; switch (pinmux_type) { - case PINMUX_TYPE_FUNCTION: - pr_notice_once("Use of GPIO API for function requests is " - "deprecated, convert to pinctrl\n"); - /* handle for now */ - ret = sh_pfc_config_function(pfc, offset); - if (unlikely(ret < 0)) - goto err; - - break; case PINMUX_TYPE_GPIO: case PINMUX_TYPE_INPUT: case PINMUX_TYPE_OUTPUT: break; + case PINMUX_TYPE_FUNCTION: default: pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type); ret = -ENOTSUPP; @@ -400,7 +377,7 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) pmx->range.name = DRV_NAME, pmx->range.id = 0; - pmx->range.npins = pfc->info->nr_gpios; + pmx->range.npins = pfc->info->nr_pins; pmx->range.base = 0; pmx->range.pin_base = 0; From 24d6b36e91b0503cd1c88b34fa793c0c65fa767d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 29 Nov 2012 18:00:32 +0100 Subject: [PATCH 074/307] sh-pfc: Don't needlessly check GPIO type in sh_gpio_free() The GPIO type is always PINMUX_TYPE_FUNCTION when freeing a function GPIO. Hardcode the type value. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/gpio.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 80a50d8a50e7..8f01113d0ecb 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -71,16 +71,13 @@ static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); unsigned long flags; - int pinmux_type; if (offset < pfc->info->nr_pins) return pinctrl_free_gpio(offset); spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; - - sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); + sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); spin_unlock_irqrestore(&pfc->lock, flags); } From a373ed0aa229f06e7d699797669b664ef39d97c1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 29 Nov 2012 13:24:07 +0100 Subject: [PATCH 075/307] sh-pfc: Split pins and functions definition tables Split the GPIOs table into a pins table for real GPIOs and a functions table for function GPIOs. Only register pins with the pinctrl core. The function GPIOs remain accessible as GPIOs. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 21 ++++++++------ drivers/pinctrl/sh-pfc/gpio.c | 5 ++-- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 15 ++++++---- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 14 +++++++--- drivers/pinctrl/sh-pfc/pfc-sh7203.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 15 ++++++---- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7720.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7722.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7723.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7724.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7734.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7757.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7785.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-sh7786.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pfc-shx3.c | 13 ++++++--- drivers/pinctrl/sh-pfc/pinctrl.c | 41 ++++++++++++++-------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 19 ++++++++----- 20 files changed, 193 insertions(+), 106 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index bed2d23e2464..9dee3b911283 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -92,13 +92,14 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio) { return (gpio < pfc->info->nr_pins) && - (pfc->info->gpios[gpio].enum_id != 0); + (pfc->info->pins[gpio].enum_id != 0); } bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio) { - return (gpio >= pfc->info->nr_pins) && (gpio < pfc->info->nr_gpios) && - (pfc->info->gpios[gpio].enum_id != 0); + return (gpio >= pfc->info->nr_pins) && + (gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) && + (pfc->info->func_gpios[gpio - pfc->info->nr_pins].enum_id != 0); } static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, @@ -234,7 +235,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) { - struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; + struct pinmux_pin *gpiop = &pfc->info->pins[gpio]; struct pinmux_data_reg *data_reg; int k, n; @@ -291,7 +292,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp) { - struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; + struct pinmux_pin *gpiop = &pfc->info->pins[gpio]; int k, n; if (!sh_pfc_gpio_is_pin(pfc, gpio)) @@ -352,12 +353,16 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, pinmux_enum_t *enum_idp) { - pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id; pinmux_enum_t *data = pfc->info->gpio_data; + pinmux_enum_t enum_id; int k; - if (!sh_pfc_gpio_is_pin(pfc, gpio) && - !sh_pfc_gpio_is_function(pfc, gpio)) { + if (sh_pfc_gpio_is_pin(pfc, gpio)) { + enum_id = pfc->info->pins[gpio].enum_id; + } else if (sh_pfc_gpio_is_function(pfc, gpio)) { + unsigned int offset = gpio - pfc->info->nr_pins; + enum_id = pfc->info->func_gpios[offset].enum_id; + } else { pr_err("non data/mark enum_id for gpio %d\n", gpio); return -1; } diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 8f01113d0ecb..2a99bef281ad 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -183,7 +183,7 @@ static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) gc->label = pfc->info->name; gc->owner = THIS_MODULE; gc->base = 0; - gc->ngpio = pfc->info->nr_gpios; + gc->ngpio = pfc->info->nr_pins + pfc->info->nr_func_gpios; } int sh_pfc_register_gpiochip(struct sh_pfc *pfc) @@ -206,7 +206,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) pfc->gpio = chip; pr_info("%s handling gpio 0 -> %u\n", - pfc->info->name, pfc->info->nr_gpios - 1); + pfc->info->name, + pfc->info->nr_pins + pfc->info->nr_func_gpios - 1); return 0; } diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 957502ebcc5b..a22763e3a32e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -1654,11 +1654,13 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), }; -static struct pinmux_gpio pinmux_gpios[] = { - - /* PORT */ +static struct pinmux_pin pinmux_pins[] = { GPIO_PORT_ALL(), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* IRQ */ GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), GPIO_FN(IRQ1), @@ -2592,9 +2594,10 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = { .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PORT211 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index bd5a70d5247f..f771239f93e4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1450,8 +1450,13 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), @@ -2609,9 +2614,10 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_GP_6_8 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index ee972f0bc696..17e2d06cf7a0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), @@ -815,7 +815,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PF2, PF2_DATA), PINMUX_GPIO(GPIO_PF1, PF1_DATA), PINMUX_GPIO(GPIO_PF0, PF0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* INTC */ GPIO_FN(PINT7_PB), GPIO_FN(PINT6_PB), @@ -1577,9 +1581,10 @@ struct sh_pfc_soc_info sh7203_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PF0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 44066dec1c3f..b927440564b7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SD_D2_MARK, PK0MD_10), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* Port A */ PINMUX_GPIO(GPIO_PA3, PA3_DATA), @@ -1216,7 +1216,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PK2, PK2_DATA), PINMUX_GPIO(GPIO_PK1, PK1_DATA), PINMUX_GPIO(GPIO_PK0, PK0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* INTC */ GPIO_FN(PINT7_PG), GPIO_FN(PINT6_PG), @@ -2116,9 +2120,10 @@ struct sh_pfc_soc_info sh7264_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PK0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 072c7d5da512..8f9b975670c2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PWM1A_MARK, PJ0MD_100), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* Port A */ PINMUX_GPIO(GPIO_PA1, PA1_DATA), PINMUX_GPIO(GPIO_PA0, PA0_DATA), @@ -1613,7 +1613,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* INTC */ GPIO_FN(IRQ7_PG), GPIO_FN(IRQ6_PG), @@ -2819,9 +2823,10 @@ struct sh_pfc_soc_info sh7269_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PJ0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index c11207442415..3a1961b3d902 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -929,11 +929,13 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), }; -static struct pinmux_gpio pinmux_gpios[] = { - - /* PORT */ +static struct pinmux_pin pinmux_pins[] = { GPIO_PORT_ALL(), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* IRQ */ GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), @@ -1640,9 +1642,10 @@ struct sh_pfc_soc_info sh7372_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PORT190 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index e41aa21edac0..02cb1dc6d12e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1539,9 +1539,13 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { GPIO_PORT_ALL(), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* Table 25-1 (Functions 0-7) */ GPIO_FN(VBUS_0), GPIO_FN(GPI0), @@ -2776,9 +2780,10 @@ struct sh_pfc_soc_info sh73a0_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PORT309 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 294b75858c9e..9952a7c2d287 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -759,7 +759,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* BSC */ GPIO_FN(D31), GPIO_FN(D30), @@ -1220,9 +1224,10 @@ struct sh_pfc_soc_info sh7720_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PTV0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index e7eadaf8e444..d561737a385b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -982,7 +982,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ GPIO_FN(SCIF0_TXD), GPIO_FN(SCIF0_RXD), @@ -1764,9 +1768,10 @@ struct sh_pfc_soc_info sh7722_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PTZ1 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 06b1d736001d..60831bfa177a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -1139,7 +1139,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ GPIO_FN(SCIF0_PTT_TXD), GPIO_FN(SCIF0_PTT_RXD), @@ -1888,9 +1892,10 @@ struct sh_pfc_soc_info sh7723_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PTZ0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 41160a3efb40..0b9d16ed3524 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -1418,7 +1418,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* BSC */ GPIO_FN(D31), GPIO_FN(D30), @@ -2210,9 +2214,10 @@ struct sh_pfc_soc_info sh7724_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PTZ0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index df32e71625b1..e3bfeffba392 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -1384,9 +1384,13 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), @@ -2460,9 +2464,10 @@ struct sh_pfc_soc_info sh7734_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_GP_5_11 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index dd32f347ce5a..6e78358bbdef 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -1370,7 +1370,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* PTA (mobule: LBSC, RGMII) */ GPIO_FN(BS), GPIO_FN(RDWR), @@ -2267,9 +2271,10 @@ struct sh_pfc_soc_info sh7757_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PTZ7 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 447bd921b0ea..cce232d47276 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), @@ -845,7 +845,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PR2, PR2_DATA), PINMUX_GPIO(GPIO_PR1, PR1_DATA), PINMUX_GPIO(GPIO_PR0, PR0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* FN */ GPIO_FN(D63_AD31), GPIO_FN(D62_AD30), @@ -1289,9 +1293,10 @@ struct sh_pfc_soc_info sh7785_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PR0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index dee3cfbe3bbe..74a0e1128f22 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static struct pinmux_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), @@ -505,7 +505,11 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static struct pinmux_func pinmux_func_gpios[] = { /* FN */ GPIO_FN(CDE), GPIO_FN(ETH_MAGIC), @@ -822,9 +826,10 @@ struct sh_pfc_soc_info sh7786_pinmux_info = { .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = pinmux_gpios, - .nr_pins = GPIO_PJ0 + 1, - .nr_gpios = ARRAY_SIZE(pinmux_gpios), + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index e59da7999348..eeecffc562c1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, PH0_FN), }; -static struct pinmux_gpio shx3_pinmux_gpios[] = { +static struct pinmux_pin shx3_pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), @@ -384,7 +384,11 @@ static struct pinmux_gpio shx3_pinmux_gpios[] = { PINMUX_GPIO(GPIO_PH2, PH2_DATA), PINMUX_GPIO(GPIO_PH1, PH1_DATA), PINMUX_GPIO(GPIO_PH0, PH0_DATA), +}; +#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins) + +static struct pinmux_func shx3_pinmux_func_gpios[] = { /* FN */ GPIO_FN(D31), GPIO_FN(D30), @@ -569,9 +573,10 @@ struct sh_pfc_soc_info shx3_pinmux_info = { PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .gpios = shx3_pinmux_gpios, - .nr_pins = GPIO_PH0 + 1, - .nr_gpios = ARRAY_SIZE(shx3_pinmux_gpios), + .pins = shx3_pinmux_pins, + .nr_pins = ARRAY_SIZE(shx3_pinmux_pins), + .func_gpios = shx3_pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios), .gpio_data = shx3_pinmux_data, .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), .cfg_regs = shx3_pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 747ee6487fd7..77592900b601 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -32,7 +32,7 @@ struct sh_pfc_pinctrl { struct sh_pfc *pfc; - struct pinmux_gpio **functions; + struct pinmux_func **functions; unsigned int nr_functions; struct pinctrl_pin_desc *pads; @@ -125,7 +125,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; + pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE; /* * See if the present config needs to first be de-configured. @@ -157,8 +157,8 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, GPIO_CFG_REQ) != 0) goto err; - pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE; - pfc->info->gpios[offset].flags |= new_type; + pfc->info->pins[offset].flags &= ~PINMUX_FLAG_TYPE; + pfc->info->pins[offset].flags |= new_type; ret = 0; @@ -168,7 +168,6 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, return ret; } - static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) @@ -180,7 +179,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; + pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE; switch (pinmux_type) { case PINMUX_TYPE_GPIO: @@ -213,7 +212,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; + pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE; sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); @@ -247,7 +246,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE; + *config = pfc->info->pins[pin].flags & PINMUX_FLAG_TYPE; return 0; } @@ -297,7 +296,7 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { int i; - pmx->nr_pads = pfc->info->nr_gpios; + pmx->nr_pads = pfc->info->nr_pins; pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, GFP_KERNEL); @@ -308,17 +307,10 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) for (i = 0; i < pmx->nr_pads; i++) { struct pinctrl_pin_desc *pin = pmx->pads + i; - struct pinmux_gpio *gpio = pfc->info->gpios + i; + struct pinmux_pin *gpio = pfc->info->pins + i; pin->number = i; pin->name = gpio->name; - - /* XXX */ - if (unlikely(!gpio->enum_id)) - continue; - - if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) - pmx->nr_functions++; } return 0; @@ -328,16 +320,23 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { int i, fn; + for (i = 0; i < pfc->info->nr_func_gpios; i++) { + struct pinmux_func *func = pfc->info->func_gpios + i; + + if (func->enum_id) + pmx->nr_functions++; + } + pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * sizeof(*pmx->functions), GFP_KERNEL); if (unlikely(!pmx->functions)) return -ENOMEM; - for (i = fn = 0; i < pmx->nr_pads; i++) { - struct pinmux_gpio *gpio = pfc->info->gpios + i; + for (i = fn = 0; i < pfc->info->nr_func_gpios; i++) { + struct pinmux_func *func = pfc->info->func_gpios + i; - if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) - pmx->functions[fn++] = gpio; + if (func->enum_id) + pmx->functions[fn++] = func; } return 0; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 6ed7ab9d56d4..940170a4c64f 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -35,23 +35,27 @@ enum { #define PINMUX_FLAG_DREG_SHIFT 10 #define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) -struct pinmux_gpio { +struct pinmux_pin { const pinmux_enum_t enum_id; pinmux_flag_t flags; const char *name; }; +struct pinmux_func { + const pinmux_enum_t enum_id; + const char *name; +}; + #define PINMUX_GPIO(gpio, data_or_mark) \ [gpio] = { \ .name = __stringify(gpio), \ .enum_id = data_or_mark, \ .flags = PINMUX_TYPE_GPIO \ } -#define PINMUX_GPIO_FN(gpio, data_or_mark) \ - [gpio] = { \ +#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ + [gpio - (base)] = { \ .name = __stringify(gpio), \ .enum_id = data_or_mark, \ - .flags = PINMUX_TYPE_FUNCTION \ } #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 @@ -106,9 +110,10 @@ struct sh_pfc_soc_info { struct pinmux_range output; struct pinmux_range function; - struct pinmux_gpio *gpios; + struct pinmux_pin *pins; unsigned int nr_pins; - unsigned int nr_gpios; + struct pinmux_func *func_gpios; + unsigned int nr_func_gpios; struct pinmux_cfg_reg *cfg_regs; struct pinmux_data_reg *data_regs; @@ -145,7 +150,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) -#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, str##_MARK) +#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) /* helper macro for pinmux_enum_t */ #define PORT_DATA_I(nr) \ From 16883814eca229506cd2a4e447b2b5a2338fa35e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 6 Dec 2012 14:49:25 +0100 Subject: [PATCH 076/307] sh-pfc: Split pins and functions into separate gpio_chip instances Register two GPIO chips, one for the real GPIOs and one for the function GPIOs. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 2 +- drivers/pinctrl/sh-pfc/core.h | 3 +- drivers/pinctrl/sh-pfc/gpio.c | 239 +++++++++++++++++++--------------- 3 files changed, 138 insertions(+), 106 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 9dee3b911283..6cf39439694f 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -95,7 +95,7 @@ static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio) (pfc->info->pins[gpio].enum_id != 0); } -bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio) +static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio) { return (gpio >= pfc->info->nr_pins) && (gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) && diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index dceaec0f6277..5a0143b27e0b 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -33,6 +33,8 @@ struct sh_pfc { struct sh_pfc_window *window; struct sh_pfc_chip *gpio; + struct sh_pfc_chip *func; + struct sh_pfc_pinctrl *pinctrl; }; @@ -47,7 +49,6 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, unsigned long value); int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp); -bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio); int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, pinmux_enum_t *enum_idp); int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 2a99bef281ad..82fcb5f9faf0 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -36,112 +36,62 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) return gpio_to_pfc_chip(gc)->pfc; } -static int sh_gpio_request(struct gpio_chip *gc, unsigned offset) +/* ----------------------------------------------------------------------------- + * Pin GPIOs + */ + +static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) { - struct sh_pfc *pfc = gpio_to_pfc(gc); - unsigned long flags; - int ret = -EINVAL; - - if (offset < pfc->info->nr_pins) - return pinctrl_request_gpio(offset); - - pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); - - spin_lock_irqsave(&pfc->lock, flags); - - if (!sh_pfc_gpio_is_function(pfc, offset)) - goto done; - - if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, - GPIO_CFG_DRYRUN)) - goto done; - - if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, - GPIO_CFG_REQ)) - goto done; - - ret = 0; - -done: - spin_unlock_irqrestore(&pfc->lock, flags); - return ret; + return pinctrl_request_gpio(offset); } -static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) +static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) { - struct sh_pfc *pfc = gpio_to_pfc(gc); - unsigned long flags; - - if (offset < pfc->info->nr_pins) - return pinctrl_free_gpio(offset); - - spin_lock_irqsave(&pfc->lock, flags); - - sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); - - spin_unlock_irqrestore(&pfc->lock, flags); + return pinctrl_free_gpio(offset); } -static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value) +static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value) { struct pinmux_data_reg *dr = NULL; int bit = 0; - if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) + if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0) BUG(); - else - sh_pfc_write_bit(dr, bit, value); + + sh_pfc_write_bit(dr, bit, value); } -static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio) +static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) { + return pinctrl_gpio_direction_input(offset); +} + +static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, + int value) +{ + gpio_pin_set_value(gpio_to_pfc(gc), offset, value); + + return pinctrl_gpio_direction_output(offset); +} + +static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) +{ + struct sh_pfc *pfc = gpio_to_pfc(gc); struct pinmux_data_reg *dr = NULL; int bit = 0; - if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) + if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0) return -EINVAL; return sh_pfc_read_bit(dr, bit); } -static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) { - struct sh_pfc *pfc = gpio_to_pfc(gc); - - if (offset >= pfc->info->nr_pins) { - /* Function GPIOs can only be requested, never configured. */ - return -EINVAL; - } - - return pinctrl_gpio_direction_input(offset); + gpio_pin_set_value(gpio_to_pfc(gc), offset, value); } -static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset, - int value) -{ - struct sh_pfc *pfc = gpio_to_pfc(gc); - - if (offset >= pfc->info->nr_pins) { - /* Function GPIOs can only be requested, never configured. */ - return -EINVAL; - } - - sh_gpio_set_value(gpio_to_pfc(gc), offset, value); - - return pinctrl_gpio_direction_output(offset); -} - -static int sh_gpio_get(struct gpio_chip *gc, unsigned offset) -{ - return sh_gpio_get_value(gpio_to_pfc(gc), offset); -} - -static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value) -{ - sh_gpio_set_value(gpio_to_pfc(gc), offset, value); -} - -static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); pinmux_enum_t enum_id; @@ -167,60 +117,141 @@ static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset) return -ENOSYS; } -static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) +static void gpio_pin_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; - gc->request = sh_gpio_request; - gc->free = sh_gpio_free; - gc->direction_input = sh_gpio_direction_input; - gc->get = sh_gpio_get; - gc->direction_output = sh_gpio_direction_output; - gc->set = sh_gpio_set; - gc->to_irq = sh_gpio_to_irq; + gc->request = gpio_pin_request; + gc->free = gpio_pin_free; + gc->direction_input = gpio_pin_direction_input; + gc->get = gpio_pin_get; + gc->direction_output = gpio_pin_direction_output; + gc->set = gpio_pin_set; + gc->to_irq = gpio_pin_to_irq; + + gc->label = pfc->info->name; + gc->dev = pfc->dev; + gc->owner = THIS_MODULE; + gc->base = 0; + gc->ngpio = pfc->info->nr_pins; +} + +/* ----------------------------------------------------------------------------- + * Function GPIOs + */ + +static int gpio_function_request(struct gpio_chip *gc, unsigned offset) +{ + struct sh_pfc *pfc = gpio_to_pfc(gc); + unsigned int gpio = gc->base + offset; + unsigned long flags; + int ret = -EINVAL; + + pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); + + if (pfc->info->func_gpios[offset].enum_id == 0) + return ret; + + spin_lock_irqsave(&pfc->lock, flags); + + if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, + GPIO_CFG_DRYRUN)) + goto done; + + if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, + GPIO_CFG_REQ)) + goto done; + + ret = 0; + +done: + spin_unlock_irqrestore(&pfc->lock, flags); + return ret; +} + +static void gpio_function_free(struct gpio_chip *gc, unsigned offset) +{ + struct sh_pfc *pfc = gpio_to_pfc(gc); + unsigned int gpio = gc->base + offset; + unsigned long flags; + + spin_lock_irqsave(&pfc->lock, flags); + + sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); + + spin_unlock_irqrestore(&pfc->lock, flags); +} + +static void gpio_function_setup(struct sh_pfc_chip *chip) +{ + struct sh_pfc *pfc = chip->pfc; + struct gpio_chip *gc = &chip->gpio_chip; + + gc->request = gpio_function_request; + gc->free = gpio_function_free; gc->label = pfc->info->name; gc->owner = THIS_MODULE; - gc->base = 0; - gc->ngpio = pfc->info->nr_pins + pfc->info->nr_func_gpios; + gc->base = pfc->info->nr_pins; + gc->ngpio = pfc->info->nr_func_gpios; } -int sh_pfc_register_gpiochip(struct sh_pfc *pfc) +/* ----------------------------------------------------------------------------- + * Register/unregister + */ + +static struct sh_pfc_chip * +sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *)) { struct sh_pfc_chip *chip; int ret; chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); if (unlikely(!chip)) - return -ENOMEM; + return ERR_PTR(-ENOMEM); chip->pfc = pfc; - sh_pfc_gpio_setup(chip); + setup(chip); ret = gpiochip_add(&chip->gpio_chip); if (unlikely(ret < 0)) - return ret; + return ERR_PTR(ret); + + pr_info("%s handling gpio %u -> %u\n", + chip->gpio_chip.label, chip->gpio_chip.base, + chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); + + return chip; +} + +int sh_pfc_register_gpiochip(struct sh_pfc *pfc) +{ + struct sh_pfc_chip *chip; + + chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); + if (IS_ERR(chip)) + return PTR_ERR(chip); pfc->gpio = chip; - pr_info("%s handling gpio 0 -> %u\n", - pfc->info->name, - pfc->info->nr_pins + pfc->info->nr_func_gpios - 1); + chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + pfc->func = chip; return 0; } int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) { - struct sh_pfc_chip *chip = pfc->gpio; + int err; int ret; - ret = gpiochip_remove(&chip->gpio_chip); - if (unlikely(ret < 0)) - return ret; + ret = gpiochip_remove(&pfc->gpio->gpio_chip); + err = gpiochip_remove(&pfc->func->gpio_chip); - pfc->gpio = NULL; - return 0; + return ret < 0 ? ret : err; } From a3db40a68a5b2f3ed2190f586bdaf3904f4933b2 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 2 Jan 2013 14:53:37 +0100 Subject: [PATCH 077/307] sh-pfc: Rename struct pinmux_pin to struct sh_pfc_pin And drop the pinmux_flag_t typedef. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7203.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7720.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7722.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7723.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7724.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7734.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7757.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7785.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7786.c | 2 +- drivers/pinctrl/sh-pfc/pfc-shx3.c | 2 +- drivers/pinctrl/sh-pfc/pinctrl.c | 2 +- drivers/pinctrl/sh-pfc/sh_pfc.h | 7 +++---- 19 files changed, 22 insertions(+), 23 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 6cf39439694f..f94d80c67ef3 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -235,7 +235,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) { - struct pinmux_pin *gpiop = &pfc->info->pins[gpio]; + struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; struct pinmux_data_reg *data_reg; int k, n; @@ -292,7 +292,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp) { - struct pinmux_pin *gpiop = &pfc->info->pins[gpio]; + struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; int k, n; if (!sh_pfc_gpio_is_pin(pfc, gpio)) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index a22763e3a32e..ccf9161585d1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -1654,7 +1654,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index f771239f93e4..0e536744f3d2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1450,7 +1450,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index 17e2d06cf7a0..fc4a1280accb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index b927440564b7..c03365cd945d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SD_D2_MARK, PK0MD_10), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* Port A */ PINMUX_GPIO(GPIO_PA3, PA3_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 8f9b975670c2..1fa0950519e4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PWM1A_MARK, PJ0MD_100), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* Port A */ PINMUX_GPIO(GPIO_PA1, PA1_DATA), PINMUX_GPIO(GPIO_PA0, PA0_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 3a1961b3d902..b15a16ab388d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -929,7 +929,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 02cb1dc6d12e..ca1e97aa6eda 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1539,7 +1539,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 9952a7c2d287..0b3078b6acdf 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index d561737a385b..3a8d95fd3ed3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 60831bfa177a..d8797ff4339b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 0b9d16ed3524..40f430be71a8 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index e3bfeffba392..20c44dd7001a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -1384,7 +1384,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index 6e78358bbdef..e81ab0ecea8c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index cce232d47276..6049f594d37e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 74a0e1128f22..526e78482d5b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), }; -static struct pinmux_pin pinmux_pins[] = { +static struct sh_pfc_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index eeecffc562c1..93d60cd4c437 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, PH0_FN), }; -static struct pinmux_pin shx3_pinmux_pins[] = { +static struct sh_pfc_pin shx3_pinmux_pins[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 77592900b601..d420d9981725 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -307,7 +307,7 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) for (i = 0; i < pmx->nr_pads; i++) { struct pinctrl_pin_desc *pin = pmx->pads + i; - struct pinmux_pin *gpio = pfc->info->pins + i; + struct sh_pfc_pin *gpio = pfc->info->pins + i; pin->number = i; pin->name = gpio->name; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 940170a4c64f..dae9e155be17 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -15,7 +15,6 @@ #include typedef unsigned short pinmux_enum_t; -typedef unsigned short pinmux_flag_t; enum { PINMUX_TYPE_NONE, @@ -35,9 +34,9 @@ enum { #define PINMUX_FLAG_DREG_SHIFT 10 #define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) -struct pinmux_pin { +struct sh_pfc_pin { const pinmux_enum_t enum_id; - pinmux_flag_t flags; + unsigned short flags; const char *name; }; @@ -110,7 +109,7 @@ struct sh_pfc_soc_info { struct pinmux_range output; struct pinmux_range function; - struct pinmux_pin *pins; + struct sh_pfc_pin *pins; unsigned int nr_pins; struct pinmux_func *func_gpios; unsigned int nr_func_gpios; From c07f54f604b3b458f10452b60fe21c549218bf02 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 14:12:14 +0100 Subject: [PATCH 078/307] sh-pfc: Look up IRQ table entries by GPIO number Instead of converting the GPIO number to an enum_id and looking up IRQ table entries by enum_id, replace the pinmux_irq enum_ids field with a gpios field and lookup entries using the GPIO number. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 4 +- drivers/pinctrl/sh-pfc/core.h | 2 - drivers/pinctrl/sh-pfc/gpio.c | 21 +++------ drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 64 ++++++++++++++-------------- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 64 ++++++++++++++-------------- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 64 ++++++++++++++-------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 4 +- 7 files changed, 106 insertions(+), 117 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index f94d80c67ef3..22f299993a36 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -350,8 +350,8 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, return -1; } -int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, - pinmux_enum_t *enum_idp) +static int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, + pinmux_enum_t *enum_idp) { pinmux_enum_t *data = pfc->info->gpio_data; pinmux_enum_t enum_id; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 5a0143b27e0b..f22d03f1e503 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -49,8 +49,6 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, unsigned long value); int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp); -int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, - pinmux_enum_t *enum_idp); int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, int cfg_mode); diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 82fcb5f9faf0..454c965ea555 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -94,23 +94,14 @@ static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - pinmux_enum_t enum_id; - pinmux_enum_t *enum_ids; - int i, k, pos; + int i, k; - pos = 0; - enum_id = 0; - while (1) { - pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id); - if (pos <= 0 || !enum_id) - break; + for (i = 0; i < pfc->info->gpio_irq_size; i++) { + unsigned short *gpios = pfc->info->gpio_irq[i].gpios; - for (i = 0; i < pfc->info->gpio_irq_size; i++) { - enum_ids = pfc->info->gpio_irq[i].enum_ids; - for (k = 0; enum_ids[k]; k++) { - if (enum_ids[k] == enum_id) - return pfc->info->gpio_irq[i].irq; - } + for (k = 0; gpios[k]; k++) { + if (gpios[k] == offset) + return pfc->info->gpio_irq[i].irq; } } diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index ccf9161585d1..fd91381aaaf3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2547,38 +2547,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = { }; static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ - PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ - PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ - PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ - PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ - PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ - PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ - PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ - PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ - PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ - PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ - PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ - PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ - PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ - PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ - PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ - PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ - PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ - PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ - PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ - PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ - PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ - PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ - PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ - PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ - PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ - PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ - PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ - PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ - PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ - PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ - PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ + PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ + PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20), /* IRQ1A */ + PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ + PINMUX_IRQ(evt2irq(0x0260), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ + PINMUX_IRQ(evt2irq(0x0280), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ + PINMUX_IRQ(evt2irq(0x02A0), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ + PINMUX_IRQ(evt2irq(0x02C0), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ + PINMUX_IRQ(evt2irq(0x02E0), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ + PINMUX_IRQ(evt2irq(0x0300), GPIO_PORT119), /* IRQ8A */ + PINMUX_IRQ(evt2irq(0x0320), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ + PINMUX_IRQ(evt2irq(0x0340), GPIO_PORT19), /* IRQ10A */ + PINMUX_IRQ(evt2irq(0x0360), GPIO_PORT104), /* IRQ11A */ + PINMUX_IRQ(evt2irq(0x0380), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ + PINMUX_IRQ(evt2irq(0x03A0), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ + PINMUX_IRQ(evt2irq(0x03C0), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ + PINMUX_IRQ(evt2irq(0x03E0), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ + PINMUX_IRQ(evt2irq(0x3200), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ + PINMUX_IRQ(evt2irq(0x3220), GPIO_PORT69), /* IRQ17A */ + PINMUX_IRQ(evt2irq(0x3240), GPIO_PORT70), /* IRQ18A */ + PINMUX_IRQ(evt2irq(0x3260), GPIO_PORT71), /* IRQ19A */ + PINMUX_IRQ(evt2irq(0x3280), GPIO_PORT67), /* IRQ20A */ + PINMUX_IRQ(evt2irq(0x32A0), GPIO_PORT202), /* IRQ21A */ + PINMUX_IRQ(evt2irq(0x32C0), GPIO_PORT95), /* IRQ22A */ + PINMUX_IRQ(evt2irq(0x32E0), GPIO_PORT96), /* IRQ23A */ + PINMUX_IRQ(evt2irq(0x3300), GPIO_PORT180), /* IRQ24A */ + PINMUX_IRQ(evt2irq(0x3320), GPIO_PORT38), /* IRQ25A */ + PINMUX_IRQ(evt2irq(0x3340), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ + PINMUX_IRQ(evt2irq(0x3360), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ + PINMUX_IRQ(evt2irq(0x3380), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ + PINMUX_IRQ(evt2irq(0x33A0), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ + PINMUX_IRQ(evt2irq(0x33C0), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ + PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ }; struct sh_pfc_soc_info r8a7740_pinmux_info = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index b15a16ab388d..847e0cd1b748 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -1600,38 +1600,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0), - PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0), - PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0), - PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0), - PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0), - PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0), - PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0), - PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0), - PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0), - PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0), - PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0), - PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0), - PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0), - PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0), - PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0), - PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0), - PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0), - PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0), - PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0), - PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0), - PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0), - PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0), - PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0), - PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0), - PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0), - PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0), - PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0), - PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0), - PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0), - PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0), - PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0), + PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), + PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), + PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), + PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16), + PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163), + PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18), + PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164), + PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167), + PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168), + PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169), + PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65), + PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67), + PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137), + PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145), + PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146), + PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147), + PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170), + PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85), + PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86), + PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87), + PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92), + PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93), + PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94), + PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95), + PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112), + PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119), + PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172), + PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180), + PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181), + PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182), + PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183), + PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), }; struct sh_pfc_soc_info sh7372_pinmux_info = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index ca1e97aa6eda..639b5e21d9bc 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2738,38 +2738,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), - PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), - PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), - PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), - PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), - PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), - PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), - PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), - PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), - PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), - PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), - PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), - PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), - PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), - PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), - PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), - PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), - PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), - PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), - PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), - PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), - PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), - PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), - PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), - PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), - PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), - PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), - PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), - PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), - PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), + PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT9), + PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT10), + PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT11), + PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT13), + PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT14), + PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT15), + PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT26), + PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT27), + PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT28), + PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT40), + PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT53), + PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT54), + PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT56), + PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT115), + PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT116), + PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT117), + PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT118), + PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT147), + PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT149), + PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT150), + PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT156), + PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT159), + PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT164), + PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT223), + PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT224), + PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT227), + PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT234), + PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT238), + PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT239), + PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT249), + PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT251), + PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT308), }; struct sh_pfc_soc_info sh73a0_pinmux_info = { diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index dae9e155be17..f9d448099bcb 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -89,11 +89,11 @@ struct pinmux_data_reg { struct pinmux_irq { int irq; - pinmux_enum_t *enum_ids; + unsigned short *gpios; }; #define PINMUX_IRQ(irq_nr, ids...) \ - { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \ + { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ struct pinmux_range { pinmux_enum_t begin; From 17dffe48d18f9c31ba7499af385e10bc02d7c7d9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Feb 2013 22:09:27 +0100 Subject: [PATCH 079/307] sh-pfc: Share the PORT_10_REV, PORT_32 and PORT_32_REV definitions The macros are defined identically and used in two SoC-specific files, share them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 34 +++++++--------------------- drivers/pinctrl/sh-pfc/pfc-sh7734.c | 31 ++++++------------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 17 ++++++++++++++ 3 files changed, 32 insertions(+), 50 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 0e536744f3d2..e9a7ead139fa 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -23,11 +23,6 @@ #include "sh_pfc.h" -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - #define CPU_32_PORT6(fn, pfx, sfx) \ PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ @@ -36,12 +31,12 @@ PORT_1(fn, pfx##8, sfx) #define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT(fn, pfx##_0_, sfx), \ - CPU_32_PORT(fn, pfx##_1_, sfx), \ - CPU_32_PORT(fn, pfx##_2_, sfx), \ - CPU_32_PORT(fn, pfx##_3_, sfx), \ - CPU_32_PORT(fn, pfx##_4_, sfx), \ - CPU_32_PORT(fn, pfx##_5_, sfx), \ + PORT_32(fn, pfx##_0_, sfx), \ + PORT_32(fn, pfx##_1_, sfx), \ + PORT_32(fn, pfx##_2_, sfx), \ + PORT_32(fn, pfx##_3_, sfx), \ + PORT_32(fn, pfx##_4_, sfx), \ + PORT_32(fn, pfx##_5_, sfx), \ CPU_32_PORT6(fn, pfx##_6_, sfx) #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) @@ -55,21 +50,8 @@ #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) +#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused) #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index 20c44dd7001a..99ea220269ff 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -14,11 +14,6 @@ #include "sh_pfc.h" -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - #define CPU_32_PORT5(fn, pfx, sfx) \ PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ @@ -29,11 +24,11 @@ /* GPSR0 - GPSR5 */ #define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT(fn, pfx##_0_, sfx), \ - CPU_32_PORT(fn, pfx##_1_, sfx), \ - CPU_32_PORT(fn, pfx##_2_, sfx), \ - CPU_32_PORT(fn, pfx##_3_, sfx), \ - CPU_32_PORT(fn, pfx##_4_, sfx), \ + PORT_32(fn, pfx##_0_, sfx), \ + PORT_32(fn, pfx##_1_, sfx), \ + PORT_32(fn, pfx##_2_, sfx), \ + PORT_32(fn, pfx##_3_, sfx), \ + PORT_32(fn, pfx##_4_, sfx), \ CPU_32_PORT5(fn, pfx##_5_, sfx) #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) @@ -47,20 +42,8 @@ #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) +#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused) #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index f9d448099bcb..43c858d98321 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -138,6 +138,23 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define PORT_32(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define PORT_32_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + #define PORT_90(fn, pfx, sfx) \ PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ From a68fdca9b0447a0e7a85ee378510509be8b70d90 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 14 Feb 2013 17:36:56 +0100 Subject: [PATCH 080/307] sh-pfc: Use pinmux identifiers in the pin muxing API The PFC core exposes a sh_pfc_config_gpio() function that configures pinmuxing for a given GPIO (either a real GPIO or a function GPIO). Handling of real and function GPIOs belong to the GPIO layer, move the GPIO number to mark translation to the caller and rename the function to sh_pfc_config_mux(). Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 32 +++++++------------------------- drivers/pinctrl/sh-pfc/core.h | 4 ++-- drivers/pinctrl/sh-pfc/gpio.c | 14 ++++++-------- drivers/pinctrl/sh-pfc/pinctrl.c | 12 ++++++------ 4 files changed, 21 insertions(+), 41 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 22f299993a36..3387f824920b 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -95,13 +95,6 @@ static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio) (pfc->info->pins[gpio].enum_id != 0); } -static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio) -{ - return (gpio >= pfc->info->nr_pins) && - (gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) && - (pfc->info->func_gpios[gpio - pfc->info->nr_pins].enum_id != 0); -} - static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned long reg_width) { @@ -350,41 +343,30 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, return -1; } -static int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, - pinmux_enum_t *enum_idp) +static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, + pinmux_enum_t *enum_idp) { pinmux_enum_t *data = pfc->info->gpio_data; - pinmux_enum_t enum_id; int k; - if (sh_pfc_gpio_is_pin(pfc, gpio)) { - enum_id = pfc->info->pins[gpio].enum_id; - } else if (sh_pfc_gpio_is_function(pfc, gpio)) { - unsigned int offset = gpio - pfc->info->nr_pins; - enum_id = pfc->info->func_gpios[offset].enum_id; - } else { - pr_err("non data/mark enum_id for gpio %d\n", gpio); - return -1; - } - if (pos) { *enum_idp = data[pos + 1]; return pos + 1; } for (k = 0; k < pfc->info->gpio_data_size; k++) { - if (data[k] == enum_id) { + if (data[k] == mark) { *enum_idp = data[k + 1]; return k + 1; } } - pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); + pr_err("cannot locate data/mark enum_id for mark %d\n", mark); return -1; } -int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, - int cfg_mode) +int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, + int cfg_mode) { struct pinmux_cfg_reg *cr = NULL; pinmux_enum_t enum_id; @@ -423,7 +405,7 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, field = 0; value = 0; while (1) { - pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id); + pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); if (pos <= 0) goto out_err; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index f22d03f1e503..ab816b7fddfb 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -49,8 +49,8 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, unsigned long value); int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp); -int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, - int cfg_mode); +int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, + int cfg_mode); extern struct sh_pfc_soc_info r8a7740_pinmux_info; extern struct sh_pfc_soc_info r8a7779_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 454c965ea555..3ad938fd7ecc 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -135,23 +135,21 @@ static void gpio_pin_setup(struct sh_pfc_chip *chip) static int gpio_function_request(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - unsigned int gpio = gc->base + offset; + unsigned int mark = pfc->info->func_gpios[offset].enum_id; unsigned long flags; int ret = -EINVAL; pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); - if (pfc->info->func_gpios[offset].enum_id == 0) + if (mark == 0) return ret; spin_lock_irqsave(&pfc->lock, flags); - if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, - GPIO_CFG_DRYRUN)) + if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN)) goto done; - if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, - GPIO_CFG_REQ)) + if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ)) goto done; ret = 0; @@ -164,12 +162,12 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) static void gpio_function_free(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - unsigned int gpio = gc->base + offset; + unsigned int mark = pfc->info->func_gpios[offset].enum_id; unsigned long flags; spin_lock_irqsave(&pfc->lock, flags); - sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); + sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); spin_unlock_irqrestore(&pfc->lock, flags); } diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index d420d9981725..a83f40070b3b 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -119,6 +119,7 @@ static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, int new_type) { + unsigned int mark = pfc->info->pins[offset].enum_id; unsigned long flags; int pinmux_type; int ret = -EINVAL; @@ -137,7 +138,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, case PINMUX_TYPE_INPUT: case PINMUX_TYPE_INPUT_PULLUP: case PINMUX_TYPE_INPUT_PULLDOWN: - sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); + sh_pfc_config_mux(pfc, mark, pinmux_type, GPIO_CFG_FREE); break; default: goto err; @@ -146,15 +147,13 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, /* * Dry run */ - if (sh_pfc_config_gpio(pfc, offset, new_type, - GPIO_CFG_DRYRUN) != 0) + if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_DRYRUN) != 0) goto err; /* * Request */ - if (sh_pfc_config_gpio(pfc, offset, new_type, - GPIO_CFG_REQ) != 0) + if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0) goto err; pfc->info->pins[offset].flags &= ~PINMUX_FLAG_TYPE; @@ -214,7 +213,8 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE; - sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); + sh_pfc_config_mux(pfc, pfc->info->pins[offset].enum_id, pinmux_type, + GPIO_CFG_FREE); spin_unlock_irqrestore(&pfc->lock, flags); } From 0b73ee5d534cc6dcb96efb9eac4cf96b40910911 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 14 Feb 2013 22:12:11 +0100 Subject: [PATCH 081/307] sh-pfc: Simplify the sh_pfc_gpio_is_pin() logic The function is guaranteed to be called with a gpio number smaller than nr_pins. The condition can the be simplified, and the function inlined. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 29 +++++++++-------------------- drivers/pinctrl/sh-pfc/core.h | 4 ++-- drivers/pinctrl/sh-pfc/gpio.c | 21 +++++++++++---------- 3 files changed, 22 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 3387f824920b..9b5c0319eb77 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -89,12 +89,6 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) return 1; } -static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio) -{ - return (gpio < pfc->info->nr_pins) && - (pfc->info->pins[gpio].enum_id != 0); -} - static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned long reg_width) { @@ -226,15 +220,12 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); } -static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) +static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) { struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; struct pinmux_data_reg *data_reg; int k, n; - if (!sh_pfc_gpio_is_pin(pfc, gpio)) - return -1; - k = 0; while (1) { data_reg = pfc->info->data_regs + k; @@ -250,15 +241,13 @@ static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); gpiop->flags &= ~PINMUX_FLAG_DBIT; gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); - return 0; + return; } } k++; } BUG(); - - return -1; } static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) @@ -266,8 +255,12 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) struct pinmux_data_reg *drp; int k; - for (k = 0; k < pfc->info->nr_pins; k++) + for (k = 0; k < pfc->info->nr_pins; k++) { + if (pfc->info->pins[k].enum_id == 0) + continue; + sh_pfc_setup_data_reg(pfc, k); + } k = 0; while (1) { @@ -282,20 +275,16 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) } } -int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, - struct pinmux_data_reg **drp, int *bitp) +void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, + struct pinmux_data_reg **drp, int *bitp) { struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; int k, n; - if (!sh_pfc_gpio_is_pin(pfc, gpio)) - return -1; - k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; *drp = pfc->info->data_regs + k; *bitp = n; - return 0; } static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index ab816b7fddfb..a3111b73fb94 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -47,8 +47,8 @@ int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos); void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, unsigned long value); -int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, - struct pinmux_data_reg **drp, int *bitp); +void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, + struct pinmux_data_reg **drp, int *bitp); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, int cfg_mode); diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 3ad938fd7ecc..db9af4e548a0 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -42,6 +42,11 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) { + struct sh_pfc *pfc = gpio_to_pfc(gc); + + if (pfc->info->pins[offset].enum_id == 0) + return -EINVAL; + return pinctrl_request_gpio(offset); } @@ -52,12 +57,10 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value) { - struct pinmux_data_reg *dr = NULL; - int bit = 0; - - if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0) - BUG(); + struct pinmux_data_reg *dr; + int bit; + sh_pfc_get_data_reg(pfc, offset, &dr, &bit); sh_pfc_write_bit(dr, bit, value); } @@ -77,12 +80,10 @@ static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - struct pinmux_data_reg *dr = NULL; - int bit = 0; - - if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0) - return -EINVAL; + struct pinmux_data_reg *dr; + int bit; + sh_pfc_get_data_reg(pfc, offset, &dr, &bit); return sh_pfc_read_bit(dr, bit); } From 934cb02bab9003bf65afe73e9146a1ea63b26c40 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 14 Feb 2013 22:35:09 +0100 Subject: [PATCH 082/307] sh-pfc: Add function to retrieve a pin instance from its pin number This prepares support for sparse pin numbering. The function currently just performs and indexed lookup in the pins array. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 7 ++++++- drivers/pinctrl/sh-pfc/core.h | 1 + drivers/pinctrl/sh-pfc/gpio.c | 3 ++- drivers/pinctrl/sh-pfc/pinctrl.c | 23 +++++++++++++---------- 4 files changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 9b5c0319eb77..667db99fb510 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -78,6 +78,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, return (void __iomem *)address; } +struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin) +{ + return &pfc->info->pins[pin]; +} + static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) { if (enum_id < r->begin) @@ -278,7 +283,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp) { - struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; + struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio); int k, n; k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index a3111b73fb94..6ea3d4f3d05e 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -49,6 +49,7 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, unsigned long value); void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, struct pinmux_data_reg **drp, int *bitp); +struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, int cfg_mode); diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index db9af4e548a0..45090d8381a2 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -43,8 +43,9 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); + struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); - if (pfc->info->pins[offset].enum_id == 0) + if (pin->enum_id == 0) return -EINVAL; return pinctrl_request_gpio(offset); diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index a83f40070b3b..78bd277c01d9 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -119,14 +119,15 @@ static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, int new_type) { - unsigned int mark = pfc->info->pins[offset].enum_id; + struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); + unsigned int mark = pin->enum_id; unsigned long flags; int pinmux_type; int ret = -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE; + pinmux_type = pin->flags & PINMUX_FLAG_TYPE; /* * See if the present config needs to first be de-configured. @@ -156,8 +157,8 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0) goto err; - pfc->info->pins[offset].flags &= ~PINMUX_FLAG_TYPE; - pfc->info->pins[offset].flags |= new_type; + pin->flags &= ~PINMUX_FLAG_TYPE; + pin->flags |= new_type; ret = 0; @@ -173,12 +174,13 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; + struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); unsigned long flags; int ret, pinmux_type; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE; + pinmux_type = pin->flags & PINMUX_FLAG_TYPE; switch (pinmux_type) { case PINMUX_TYPE_GPIO: @@ -206,15 +208,15 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; + struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); unsigned long flags; int pinmux_type; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE; + pinmux_type = pin->flags & PINMUX_FLAG_TYPE; - sh_pfc_config_mux(pfc, pfc->info->pins[offset].enum_id, pinmux_type, - GPIO_CFG_FREE); + sh_pfc_config_mux(pfc, pin->enum_id, pinmux_type, GPIO_CFG_FREE); spin_unlock_irqrestore(&pfc->lock, flags); } @@ -240,13 +242,14 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = { .gpio_set_direction = sh_pfc_gpio_set_direction, }; -static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, +static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, unsigned long *config) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; + struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, _pin); - *config = pfc->info->pins[pin].flags & PINMUX_FLAG_TYPE; + *config = pin->flags & PINMUX_FLAG_TYPE; return 0; } From 247127f90ba1fcc234008e00e937537a89eef9ca Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 8 Mar 2013 00:45:12 +0100 Subject: [PATCH 083/307] sh-pfc: Replace pinctrl_add_gpio_range() with gpiochip_add_pin_range() Adding a GPIO range to a pinctrl device logically belongs to the GPIO driver. Switch to the right API. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/gpio.c | 6 ++++++ drivers/pinctrl/sh-pfc/pinctrl.c | 9 --------- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 45090d8381a2..32a9c7870a16 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -220,6 +220,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *)) int sh_pfc_register_gpiochip(struct sh_pfc *pfc) { struct sh_pfc_chip *chip; + int ret; chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); if (IS_ERR(chip)) @@ -227,6 +228,11 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) pfc->gpio = chip; + ret = gpiochip_add_pin_range(&chip->gpio_chip, dev_name(pfc->dev), 0, 0, + chip->gpio_chip.ngpio); + if (ret < 0) + return ret; + chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); if (IS_ERR(chip)) return PTR_ERR(chip); diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 78bd277c01d9..a60c317d988a 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -28,7 +28,6 @@ struct sh_pfc_pinctrl { struct pinctrl_dev *pctl; struct pinctrl_desc pctl_desc; - struct pinctrl_gpio_range range; struct sh_pfc *pfc; @@ -377,14 +376,6 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) if (IS_ERR(pmx->pctl)) return PTR_ERR(pmx->pctl); - pmx->range.name = DRV_NAME, - pmx->range.id = 0; - pmx->range.npins = pfc->info->nr_pins; - pmx->range.base = 0; - pmx->range.pin_base = 0; - - pinctrl_add_gpio_range(pmx->pctl, &pmx->range); - return 0; } From 63d573835f835aab4c44d0e0342cf5976fb14b35 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 15 Feb 2013 01:33:38 +0100 Subject: [PATCH 084/307] sh-pfc: Add support for sparse pin numbers The PFC driver assumes that the value of the GPIO_PORTxxx enumeration names are equal to the port number. This isn't true when the port number space is sparse, as with the SH73A0. Fix the issue by adding support for pin numbers ranges specified through SoC data. When no range is specified the driver considers that the PFC implements a single contiguous range for all pins. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 19 ++++++++++- drivers/pinctrl/sh-pfc/core.h | 2 ++ drivers/pinctrl/sh-pfc/gpio.c | 37 ++++++++++++++++---- drivers/pinctrl/sh-pfc/pinctrl.c | 58 +++++++++++++++++++++----------- drivers/pinctrl/sh-pfc/sh_pfc.h | 2 ++ 5 files changed, 91 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 667db99fb510..798248261f30 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -80,7 +80,24 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin) { - return &pfc->info->pins[pin]; + unsigned int offset; + unsigned int i; + + if (pfc->info->ranges == NULL) + return &pfc->info->pins[pin]; + + for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) { + const struct pinmux_range *range = &pfc->info->ranges[i]; + + if (pin <= range->end) + return pin >= range->begin + ? &pfc->info->pins[offset + pin - range->begin] + : NULL; + + offset += range->end - range->begin + 1; + } + + return NULL; } static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 6ea3d4f3d05e..b8b3e872cc19 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -32,6 +32,8 @@ struct sh_pfc { unsigned int num_windows; struct sh_pfc_window *window; + unsigned int nr_pins; + struct sh_pfc_chip *gpio; struct sh_pfc_chip *func; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 32a9c7870a16..806e2dd62137 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -45,7 +45,7 @@ static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) struct sh_pfc *pfc = gpio_to_pfc(gc); struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); - if (pin->enum_id == 0) + if (pin == NULL || pin->enum_id == 0) return -EINVAL; return pinctrl_request_gpio(offset); @@ -127,7 +127,7 @@ static void gpio_pin_setup(struct sh_pfc_chip *chip) gc->dev = pfc->dev; gc->owner = THIS_MODULE; gc->base = 0; - gc->ngpio = pfc->info->nr_pins; + gc->ngpio = pfc->nr_pins; } /* ----------------------------------------------------------------------------- @@ -184,7 +184,7 @@ static void gpio_function_setup(struct sh_pfc_chip *chip) gc->label = pfc->info->name; gc->owner = THIS_MODULE; - gc->base = pfc->info->nr_pins; + gc->base = pfc->nr_pins; gc->ngpio = pfc->info->nr_func_gpios; } @@ -219,20 +219,43 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *)) int sh_pfc_register_gpiochip(struct sh_pfc *pfc) { + const struct pinmux_range *ranges; + struct pinmux_range def_range; struct sh_pfc_chip *chip; + unsigned int nr_ranges; + unsigned int i; int ret; + /* Register the real GPIOs chip. */ chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); if (IS_ERR(chip)) return PTR_ERR(chip); pfc->gpio = chip; - ret = gpiochip_add_pin_range(&chip->gpio_chip, dev_name(pfc->dev), 0, 0, - chip->gpio_chip.ngpio); - if (ret < 0) - return ret; + /* Register the GPIO to pin mappings. */ + if (pfc->info->ranges == NULL) { + def_range.begin = 0; + def_range.end = pfc->info->nr_pins - 1; + ranges = &def_range; + nr_ranges = 1; + } else { + ranges = pfc->info->ranges; + nr_ranges = pfc->info->nr_ranges; + } + for (i = 0; i < nr_ranges; ++i) { + const struct pinmux_range *range = &ranges[i]; + + ret = gpiochip_add_pin_range(&chip->gpio_chip, + dev_name(pfc->dev), + range->begin, range->begin, + range->end - range->begin + 1); + if (ret < 0) + return ret; + } + + /* Register the function GPIOs chip. */ chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); if (IS_ERR(chip)) return PTR_ERR(chip); diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index a60c317d988a..c9e9a1d95230 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -293,29 +293,48 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = { .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, }; -/* pinmux ranges -> pinctrl pin descs */ -static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) +/* PFC ranges -> pinctrl pin descs */ +static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { - int i; + const struct pinmux_range *ranges; + struct pinmux_range def_range; + unsigned int nr_ranges; + unsigned int nr_pins; + unsigned int i; - pmx->nr_pads = pfc->info->nr_pins; + if (pfc->info->ranges == NULL) { + def_range.begin = 0; + def_range.end = pfc->info->nr_pins - 1; + ranges = &def_range; + nr_ranges = 1; + } else { + ranges = pfc->info->ranges; + nr_ranges = pfc->info->nr_ranges; + } - pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, + pmx->pads = devm_kzalloc(pfc->dev, + sizeof(*pmx->pads) * pfc->info->nr_pins, GFP_KERNEL); - if (unlikely(!pmx->pads)) { - pmx->nr_pads = 0; + if (unlikely(!pmx->pads)) return -ENOMEM; + + for (i = 0, nr_pins = 0; i < nr_ranges; ++i) { + const struct pinmux_range *range = &ranges[i]; + unsigned int number; + + for (number = range->begin; number <= range->end; + number++, nr_pins++) { + struct pinctrl_pin_desc *pin = &pmx->pads[nr_pins]; + struct sh_pfc_pin *info = &pfc->info->pins[nr_pins]; + + pin->number = number; + pin->name = info->name; + } } - for (i = 0; i < pmx->nr_pads; i++) { - struct pinctrl_pin_desc *pin = pmx->pads + i; - struct sh_pfc_pin *gpio = pfc->info->pins + i; + pfc->nr_pins = ranges[nr_ranges-1].end + 1; - pin->number = i; - pin->name = gpio->name; - } - - return 0; + return nr_ranges; } static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) @@ -347,6 +366,7 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) int sh_pfc_register_pinctrl(struct sh_pfc *pfc) { struct sh_pfc_pinctrl *pmx; + int nr_ranges; int ret; pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); @@ -356,9 +376,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) pmx->pfc = pfc; pfc->pinctrl = pmx; - ret = sh_pfc_map_gpios(pfc, pmx); - if (unlikely(ret != 0)) - return ret; + nr_ranges = sh_pfc_map_pins(pfc, pmx); + if (unlikely(nr_ranges < 0)) + return nr_ranges; ret = sh_pfc_map_functions(pfc, pmx); if (unlikely(ret != 0)) @@ -370,7 +390,7 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; pmx->pctl_desc.pins = pmx->pads; - pmx->pctl_desc.npins = pmx->nr_pads; + pmx->pctl_desc.npins = pfc->info->nr_pins; pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); if (IS_ERR(pmx->pctl)) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 43c858d98321..dbcaa600ccc6 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -111,6 +111,8 @@ struct sh_pfc_soc_info { struct sh_pfc_pin *pins; unsigned int nr_pins; + const struct pinmux_range *ranges; + unsigned int nr_ranges; struct pinmux_func *func_gpios; unsigned int nr_func_gpios; From b58e5fac96e4f24fc9d5bce8692506ada3e244ca Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 12 Feb 2013 16:50:02 +0100 Subject: [PATCH 085/307] ARM: shmobile: sh73a0: Support sparse GPIO numbers The SH73A0 SoC has sparse GPIO numbers. Declare the pin numbers ranges in the PFC SoC data and use the pin numbers in the GPIO API. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- arch/arm/mach-shmobile/board-ag5evm.c | 26 +++---- arch/arm/mach-shmobile/board-kota2.c | 42 +++++------ arch/arm/mach-shmobile/board-kzm9g.c | 14 ++-- arch/arm/mach-shmobile/include/mach/sh73a0.h | 2 +- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 75 +++++++++++--------- 5 files changed, 84 insertions(+), 75 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index 8ff53a19c48c..a4ac46a89b27 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -304,9 +304,9 @@ static int lcd_backlight_set_brightness(int brightness) if (brightness == 0) { /* Reset the chip */ - gpio_set_value(GPIO_PORT235, 0); + gpio_set_value(235, 0); mdelay(24); - gpio_set_value(GPIO_PORT235, 1); + gpio_set_value(235, 1); return 0; } @@ -406,7 +406,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED, .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, - .cd_gpio = GPIO_PORT251, + .cd_gpio = 251, }; static struct resource sdhi0_resources[] = { @@ -461,7 +461,7 @@ static struct regulator_init_data cn4_power_init_data = { static struct fixed_voltage_config cn4_power_info = { .supply_name = "CN4 SD/MMC Vdd", .microvolts = 3300000, - .gpio = GPIO_PORT114, + .gpio = 114, .enable_high = 1, .init_data = &cn4_power_init_data, }; @@ -479,10 +479,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state) static int power_gpio = -EINVAL; if (power_gpio < 0) { - int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW, + int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW, "sdhi1_power"); if (!ret) - power_gpio = GPIO_PORT114; + power_gpio = 114; } /* @@ -493,7 +493,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state) * regulator driver. We have to live with the race in case the driver * gets unloaded and the GPIO freed between these two steps. */ - gpio_set_value(GPIO_PORT114, state); + gpio_set_value(114, state); } static struct sh_mobile_sdhi_info sh_sdhi1_info = { @@ -603,11 +603,11 @@ static void __init ag5evm_init(void) gpio_request(GPIO_FN_MMCD0_5_PU, NULL); gpio_request(GPIO_FN_MMCD0_6_PU, NULL); gpio_request(GPIO_FN_MMCD0_7_PU, NULL); - gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ + gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ /* enable SMSC911X */ - gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */ - gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ + gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ + gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ /* FSI A */ gpio_request(GPIO_FN_FSIACK, NULL); @@ -622,13 +622,13 @@ static void __init ag5evm_init(void) gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL); /* LCD panel */ - gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ + gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ mdelay(1); - gpio_set_value(GPIO_PORT217, 1); + gpio_set_value(217, 1); mdelay(100); /* LCD backlight controller */ - gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ + gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ lcd_backlight_set_brightness(0); /* enable SDHI0 on CN15 [SD I/F] */ diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c index 2ccc860403ef..b6f051573b4a 100644 --- a/arch/arm/mach-shmobile/board-kota2.c +++ b/arch/arm/mach-shmobile/board-kota2.c @@ -135,17 +135,17 @@ static struct platform_device keysc_device = { #define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */ - GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */ - GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */ - GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */ - GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */ - GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */ - GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */ - GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */ - /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */ - GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */ - /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */ + GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */ + GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */ + GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */ + GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */ + GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */ + GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */ + GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */ + GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */ + /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */ + GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */ + /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */ }; static struct gpio_keys_platform_data gpio_key_info = { @@ -165,9 +165,9 @@ static struct platform_device gpio_keys_device = { #define GPIO_LED(n, g) { .name = n, .gpio = g } static struct gpio_led gpio_leds[] = { - GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */ - GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */ - GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */ + GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */ + GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */ + GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */ }; static struct gpio_led_platform_data gpio_leds_info = { @@ -187,7 +187,7 @@ static struct platform_device gpio_leds_device = { static struct led_renesas_tpu_config led_renesas_tpu12_pdata = { .name = "V2513", .pin_gpio_fn = GPIO_FN_TPU1TO2, - .pin_gpio = GPIO_PORT153, + .pin_gpio = 153, .channel_offset = 0x90, .timer_bit = 2, .max_brightness = 1000, @@ -215,7 +215,7 @@ static struct platform_device leds_tpu12_device = { static struct led_renesas_tpu_config led_renesas_tpu41_pdata = { .name = "V2514", .pin_gpio_fn = GPIO_FN_TPU4TO1, - .pin_gpio = GPIO_PORT199, + .pin_gpio = 199, .channel_offset = 0x50, .timer_bit = 1, .max_brightness = 1000, @@ -243,7 +243,7 @@ static struct platform_device leds_tpu41_device = { static struct led_renesas_tpu_config led_renesas_tpu21_pdata = { .name = "V2515", .pin_gpio_fn = GPIO_FN_TPU2TO1, - .pin_gpio = GPIO_PORT197, + .pin_gpio = 197, .channel_offset = 0x50, .timer_bit = 1, .max_brightness = 1000, @@ -271,7 +271,7 @@ static struct platform_device leds_tpu21_device = { static struct led_renesas_tpu_config led_renesas_tpu30_pdata = { .name = "KEYLED", .pin_gpio_fn = GPIO_FN_TPU3TO0, - .pin_gpio = GPIO_PORT163, + .pin_gpio = 163, .channel_offset = 0x10, .timer_bit = 0, .max_brightness = 1000, @@ -474,8 +474,8 @@ static void __init kota2_init(void) gpio_request(GPIO_FN_D15_NAF15, NULL); gpio_request(GPIO_FN_CS5A_, NULL); gpio_request(GPIO_FN_WE0__FWE, NULL); - gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */ - gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ + gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ + gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ /* KEYSC */ gpio_request(GPIO_FN_KEYIN0_PU, NULL); @@ -507,7 +507,7 @@ static void __init kota2_init(void) gpio_request(GPIO_FN_MMCD0_6, NULL); gpio_request(GPIO_FN_MMCD0_7, NULL); gpio_request(GPIO_FN_MMCCMD0, NULL); - gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ + gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ /* SDHI0 (microSD) */ gpio_request(GPIO_FN_SDHICD0_PU, NULL); diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 7f3a6b7e7b7c..65a5e0b80f06 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -433,7 +433,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = { TMIO_MMC_WRPROTECT_DISABLE, .tmio_caps = MMC_CAP_SD_HIGHSPEED, .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, - .cd_gpio = GPIO_PORT13, + .cd_gpio = 13, }; static struct resource sdhi2_resources[] = { @@ -672,7 +672,7 @@ static void __init kzm_init(void) gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */ /* SMSC */ - gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */ + gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */ /* LCDC */ gpio_request(GPIO_FN_LCDD23, NULL); @@ -702,11 +702,11 @@ static void __init kzm_init(void) gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); - gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */ - gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */ + gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */ + gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */ /* Touchscreen */ - gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */ + gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ /* enable MMCIF */ gpio_request(GPIO_FN_MMCCLK0, NULL); @@ -730,7 +730,7 @@ static void __init kzm_init(void) gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ /* enable Micro SD */ gpio_request(GPIO_FN_SDHID2_0, NULL); @@ -739,7 +739,7 @@ static void __init kzm_init(void) gpio_request(GPIO_FN_SDHID2_3, NULL); gpio_request(GPIO_FN_SDHICMD2, NULL); gpio_request(GPIO_FN_SDHICLK2, NULL); - gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ /* I2C 3 */ gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 606d31d02a4e..4dca135f3aa8 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -94,7 +94,7 @@ enum { GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, /* Table 25-1 (Function 0-7) */ - GPIO_FN_VBUS_0, + GPIO_FN_VBUS_0 = 310, GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPI2, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 639b5e21d9bc..9cef0d8b8ccd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1543,7 +1543,14 @@ static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static struct pinmux_range pinmux_ranges[] = { + {.begin = 0, .end = 118,}, + {.begin = 128, .end = 164,}, + {.begin = 192, .end = 282,}, + {.begin = 288, .end = 309,}, +}; + +#define PINMUX_FN_BASE GPIO_FN_VBUS_0 static struct pinmux_func pinmux_func_gpios[] = { /* Table 25-1 (Functions 0-7) */ @@ -2738,38 +2745,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT9), - PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT10), - PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT11), - PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT13), - PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT14), - PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT15), - PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT26), - PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT27), - PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT28), - PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT40), - PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT53), - PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT54), - PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT56), - PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT115), - PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT116), - PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT117), - PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT118), - PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT147), - PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT149), - PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT150), - PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT156), - PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT159), - PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT164), - PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT223), - PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT224), - PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT227), - PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT234), - PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT238), - PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT239), - PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT249), - PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT251), - PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT308), + PINMUX_IRQ(EXT_IRQ16H(19), 9), + PINMUX_IRQ(EXT_IRQ16L(1), 10), + PINMUX_IRQ(EXT_IRQ16L(0), 11), + PINMUX_IRQ(EXT_IRQ16H(18), 13), + PINMUX_IRQ(EXT_IRQ16H(20), 14), + PINMUX_IRQ(EXT_IRQ16H(21), 15), + PINMUX_IRQ(EXT_IRQ16H(31), 26), + PINMUX_IRQ(EXT_IRQ16H(30), 27), + PINMUX_IRQ(EXT_IRQ16H(29), 28), + PINMUX_IRQ(EXT_IRQ16H(22), 40), + PINMUX_IRQ(EXT_IRQ16H(23), 53), + PINMUX_IRQ(EXT_IRQ16L(10), 54), + PINMUX_IRQ(EXT_IRQ16L(9), 56), + PINMUX_IRQ(EXT_IRQ16H(26), 115), + PINMUX_IRQ(EXT_IRQ16H(27), 116), + PINMUX_IRQ(EXT_IRQ16H(28), 117), + PINMUX_IRQ(EXT_IRQ16H(24), 118), + PINMUX_IRQ(EXT_IRQ16L(6), 147), + PINMUX_IRQ(EXT_IRQ16L(2), 149), + PINMUX_IRQ(EXT_IRQ16L(7), 150), + PINMUX_IRQ(EXT_IRQ16L(12), 156), + PINMUX_IRQ(EXT_IRQ16L(4), 159), + PINMUX_IRQ(EXT_IRQ16H(25), 164), + PINMUX_IRQ(EXT_IRQ16L(8), 223), + PINMUX_IRQ(EXT_IRQ16L(3), 224), + PINMUX_IRQ(EXT_IRQ16L(5), 227), + PINMUX_IRQ(EXT_IRQ16H(17), 234), + PINMUX_IRQ(EXT_IRQ16L(11), 238), + PINMUX_IRQ(EXT_IRQ16L(13), 239), + PINMUX_IRQ(EXT_IRQ16H(16), 249), + PINMUX_IRQ(EXT_IRQ16L(14), 251), + PINMUX_IRQ(EXT_IRQ16L(9), 308), }; struct sh_pfc_soc_info sh73a0_pinmux_info = { @@ -2782,6 +2789,8 @@ struct sh_pfc_soc_info sh73a0_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), + .ranges = pinmux_ranges, + .nr_ranges = ARRAY_SIZE(pinmux_ranges), .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), From be2edfcc2874bebfddaf270726e72b53c8017df9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 07:38:50 +0100 Subject: [PATCH 086/307] ARM: shmobile: ap4-evb: Replace GPIO_PORTx enum with GPIO port numbers The PFC GPIO API implementation moved to using port numbers. Replace all GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx enum values are identical to the port number on this platform. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- arch/arm/mach-shmobile/board-ap4evb.c | 36 +++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 38f1259a0daf..0a2b6e435b65 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -273,11 +273,11 @@ static struct platform_device smc911x_device = { /* * The card detect pin of the top SD/MMC slot (CN7) is active low and is - * connected to GPIO A22 of SH7372 (GPIO_PORT41). + * connected to GPIO A22 of SH7372 (GPIO 41). */ static int slot_cn7_get_cd(struct platform_device *pdev) { - return !gpio_get_value(GPIO_PORT41); + return !gpio_get_value(41); } /* MERAM */ static struct sh_mobile_meram_info meram_info = { @@ -838,22 +838,22 @@ static struct platform_device fsi_hdmi_device = { static struct gpio_led ap4evb_leds[] = { { .name = "led4", - .gpio = GPIO_PORT185, + .gpio = 185, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led2", - .gpio = GPIO_PORT186, + .gpio = 186, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led3", - .gpio = GPIO_PORT187, + .gpio = 187, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led1", - .gpio = GPIO_PORT188, + .gpio = 188, .default_state = LEDS_GPIO_DEFSTATE_ON, } }; @@ -1026,10 +1026,10 @@ static void __init hdmi_init_pm_clock(void) /* TouchScreen */ #ifdef CONFIG_AP4EVB_QHD # define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 -# define GPIO_TSC_PORT GPIO_PORT123 +# define GPIO_TSC_PORT 123 #else /* WVGA */ # define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 -# define GPIO_TSC_PORT GPIO_PORT40 +# define GPIO_TSC_PORT 40 #endif #define IRQ28 evt2irq(0x3380) /* IRQ28A */ @@ -1121,10 +1121,10 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_IRQ6_39, NULL); /* enable Debug switch (S6) */ - gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL); /* SDHI0 */ gpio_request(GPIO_FN_SDHICD0, NULL); @@ -1172,15 +1172,15 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_FSIAILR, NULL); gpio_request(GPIO_FN_FSIAISLD, NULL); gpio_request(GPIO_FN_FSIAOSLD, NULL); - gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ + gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ - gpio_request(GPIO_PORT9, NULL); - gpio_request(GPIO_PORT10, NULL); + gpio_request(9, NULL); + gpio_request(10, NULL); gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ /* card detect pin for MMC slot (CN7) */ - gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL); + gpio_request_one(41, GPIOF_IN, NULL); /* setup FSI2 port B (HDMI) */ gpio_request(GPIO_FN_FSIBCK, NULL); @@ -1268,8 +1268,8 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); - gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ - gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ + gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ lcdc_info.clock_source = LCDC_CLK_BUS; lcdc_info.ch[0].interface_type = RGB18; From ead10fed8b4b421c6871de74eb3983d0180224df Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 07:38:50 +0100 Subject: [PATCH 087/307] ARM: shmobile: armadillo: Replace GPIO_PORTx enum with GPIO port numbers The PFC GPIO API implementation moved to using port numbers. Replace all GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx enum values are identical to the port number on this platform. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- .../arm/mach-shmobile/board-armadillo800eva.c | 58 +++++++++---------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index f2ec0777cfbe..92d799138835 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -227,7 +227,7 @@ static void usbhsf_power_ctrl(struct platform_device *pdev, static int usbhsf_get_vbus(struct platform_device *pdev) { - return gpio_get_value(GPIO_PORT209); + return gpio_get_value(209); } static irqreturn_t usbhsf_interrupt(int irq, void *data) @@ -535,10 +535,10 @@ static struct platform_device hdmi_lcdc_device = { { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1), - GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"), - GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"), - GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"), + GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1), + GPIO_KEY(KEY_BACK, 100, "SW4"), + GPIO_KEY(KEY_MENU, 97, "SW5"), + GPIO_KEY(KEY_HOME, 98, "SW6"), }; static struct gpio_keys_platform_data gpio_key_info = { @@ -708,9 +708,9 @@ static int mt9t111_power(struct device *dev, int mode) /* video1 (= CON1 camera) expect 24MHz */ clk_set_rate(mclk, clk_round_rate(mclk, 24000000)); clk_enable(mclk); - gpio_set_value(GPIO_PORT158, 1); + gpio_set_value(158, 1); } else { - gpio_set_value(GPIO_PORT158, 0); + gpio_set_value(158, 0); clk_disable(mclk); } @@ -864,8 +864,8 @@ static struct platform_device fsi_hdmi_device = { /* RTC: RTC connects i2c-gpio. */ static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = GPIO_PORT208, - .scl_pin = GPIO_PORT91, + .sda_pin = 208, + .scl_pin = 91, .udelay = 5, /* 100 kHz */ }; @@ -1000,12 +1000,12 @@ static void __init eva_init(void) gpio_request(GPIO_FN_LCD0_DISP, NULL); gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); - gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ - gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ + gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ /* Touchscreen */ gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ - gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ + gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ /* GETHER */ gpio_request(GPIO_FN_ET_CRS, NULL); @@ -1028,12 +1028,12 @@ static void __init eva_init(void) gpio_request(GPIO_FN_ET_RX_DV, NULL); gpio_request(GPIO_FN_ET_RX_CLK, NULL); - gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ + gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ /* USB */ - gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ + gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ - if (gpio_get_value(GPIO_PORT159)) { + if (gpio_get_value(159)) { /* USB Host */ } else { /* USB Func */ @@ -1042,10 +1042,10 @@ static void __init eva_init(void) * OTOH, usbhs interrupt needs its value (HI/LOW) to decide * USB connection/disconnection (usbhsf_get_vbus()). * This means we needs to select GPIO_FN_IRQ7_PORT209 first, - * and select GPIO_PORT209 here + * and select GPIO 209 here */ gpio_request(GPIO_FN_IRQ7_PORT209, NULL); - gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL); + gpio_request_one(209, GPIOF_IN, NULL); platform_device_register(&usbhsf_device); usb = &usbhsf_device; @@ -1060,9 +1060,9 @@ static void __init eva_init(void) gpio_request(GPIO_FN_SDHI0_D3, NULL); gpio_request(GPIO_FN_SDHI0_WP, NULL); - gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */ - gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */ - gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */ + gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */ + gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */ + gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */ /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */ @@ -1099,10 +1099,10 @@ static void __init eva_init(void) gpio_request(GPIO_FN_VIO_CKO, NULL); /* CON1/CON15 Camera */ - gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ - gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ + gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ + gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ /* see mt9t111_power() */ - gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ + gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ /* FSI-WM8978 */ gpio_request(GPIO_FN_FSIAIBT, NULL); @@ -1111,8 +1111,8 @@ static void __init eva_init(void) gpio_request(GPIO_FN_FSIAOSLD, NULL); gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); - gpio_request(GPIO_PORT7, NULL); - gpio_request(GPIO_PORT8, NULL); + gpio_request(7, NULL); + gpio_request(8, NULL); gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ @@ -1129,14 +1129,14 @@ static void __init eva_init(void) * DBGMD/LCDC0/FSIA MUX * DBGMD_SELECT_B should be set after setting PFC Function. */ - gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL); + gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL); /* * We can switch CON8/CON14 by SW1.5, * but it needs after DBGMD_SELECT_B */ - gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL); - if (gpio_get_value(GPIO_PORT6)) { + gpio_request_one(6, GPIOF_IN, NULL); + if (gpio_get_value(6)) { /* CON14 enable */ } else { /* CON8 (SDHI1) enable */ @@ -1150,7 +1150,7 @@ static void __init eva_init(void) gpio_request(GPIO_FN_SDHI1_WP, NULL); /* SDSLOT2_PON */ - gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL); + gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL); platform_device_register(&sdhi1_device); } From 8c2a141eece6196ee5f236cf0ac13c6e2828b0a8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 07:38:50 +0100 Subject: [PATCH 088/307] ARM: shmobile: bonito: Replace GPIO_PORTx enum with GPIO port numbers The PFC GPIO API implementation moved to using port numbers. Replace all GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx enum values are identical to the port number on this platform. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- arch/arm/mach-shmobile/board-bonito.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c index e50f86691539..d363526450ac 100644 --- a/arch/arm/mach-shmobile/board-bonito.c +++ b/arch/arm/mach-shmobile/board-bonito.c @@ -392,8 +392,8 @@ static void __init bonito_init(void) /* * base board settings */ - gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL); - if (!gpio_get_value(GPIO_PORT176)) { + gpio_request_one(176, GPIOF_IN, NULL); + if (!gpio_get_value(176)) { u16 bsw2; u16 bsw3; u16 bsw4; @@ -461,7 +461,7 @@ static void __init bonito_init(void) gpio_request(GPIO_FN_LCD0_DISP, NULL); gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); - gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, + gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ /* backlight on */ From 6d170aa0116ed9f43d765fea47daeb7afb3a87fe Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 07:38:50 +0100 Subject: [PATCH 089/307] ARM: shmobile: mackerel: Replace GPIO_PORTx enum with GPIO port numbers The PFC GPIO API implementation moved to using port numbers. Replace all GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx enum values are identical to the port number on this platform. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- arch/arm/mach-shmobile/board-mackerel.c | 34 ++++++++++++------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index db968a585ff0..172d47216c91 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -363,7 +363,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = { static int mackerel_set_brightness(int brightness) { - gpio_set_value(GPIO_PORT31, brightness); + gpio_set_value(31, brightness); return 0; } @@ -819,22 +819,22 @@ static struct platform_device usbhs1_device = { static struct gpio_led mackerel_leds[] = { { .name = "led0", - .gpio = GPIO_PORT0, + .gpio = 0, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led1", - .gpio = GPIO_PORT1, + .gpio = 1, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led2", - .gpio = GPIO_PORT2, + .gpio = 2, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led3", - .gpio = GPIO_PORT159, + .gpio = 159, .default_state = LEDS_GPIO_DEFSTATE_ON, } }; @@ -964,11 +964,11 @@ static struct platform_device nand_flash_device = { /* * The card detect pin of the top SD/MMC slot (CN7) is active low and is - * connected to GPIO A22 of SH7372 (GPIO_PORT41). + * connected to GPIO A22 of SH7372 (GPIO 41). */ static int slot_cn7_get_cd(struct platform_device *pdev) { - return !gpio_get_value(GPIO_PORT41); + return !gpio_get_value(41); } /* SDHI0 */ @@ -977,7 +977,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, .tmio_flags = TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, - .cd_gpio = GPIO_PORT172, + .cd_gpio = 172, }; static struct resource sdhi0_resources[] = { @@ -1060,11 +1060,11 @@ static struct platform_device sdhi1_device = { /* * The card detect pin of the top SD/MMC slot (CN23) is active low and is - * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162). + * connected to GPIO SCIFB_SCK of SH7372 (162). */ static int slot_cn23_get_cd(struct platform_device *pdev) { - return !gpio_get_value(GPIO_PORT162); + return !gpio_get_value(162); } /* SDHI2 */ @@ -1403,9 +1403,9 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_LCDDCK, NULL); /* backlight, off by default */ - gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL); + gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL); - gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ /* USBHS0 */ gpio_request(GPIO_FN_VBUS0_0, NULL); @@ -1421,10 +1421,10 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_FSIAILR, NULL); gpio_request(GPIO_FN_FSIAISLD, NULL); gpio_request(GPIO_FN_FSIAOSLD, NULL); - gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ + gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ - gpio_request(GPIO_PORT9, NULL); - gpio_request(GPIO_PORT10, NULL); + gpio_request(9, NULL); + gpio_request(10, NULL); gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ @@ -1475,7 +1475,7 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_SDHID1_0, NULL); #endif /* card detect pin for MMC slot (CN7) */ - gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL); + gpio_request_one(41, GPIOF_IN, NULL); /* enable SDHI2 */ gpio_request(GPIO_FN_SDHICMD2, NULL); @@ -1486,7 +1486,7 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_SDHID2_0, NULL); /* card detect pin for microSD slot (CN23) */ - gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL); + gpio_request_one(162, GPIOF_IN, NULL); /* MMCIF */ gpio_request(GPIO_FN_MMCD0_0, NULL); From 3d8d9f1df93362f319cf60b9ad10721a059b058f Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 14:33:13 +0100 Subject: [PATCH 090/307] sh-pfc: Expose real groups and functions in pinctrl/pinmux operations The sh-pfc driver exposes one fake group and function per GPIO pin. As the pinctrl and pinmux APIs are not used by any SuperH and SH Mobile board or driver, drop the fake groups and functions and replace them by a real pinctrl and pinmux implementation. Groups and functions must now be explicitly provided by PFC SoC-specific data. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 114 ++++++++++++++++--------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 35 ++++++++++ 2 files changed, 93 insertions(+), 56 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index c9e9a1d95230..c7f3c406f9de 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -31,18 +31,14 @@ struct sh_pfc_pinctrl { struct sh_pfc *pfc; - struct pinmux_func **functions; - unsigned int nr_functions; - - struct pinctrl_pin_desc *pads; - unsigned int nr_pads; + struct pinctrl_pin_desc *pins; }; static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->nr_pads; + return pmx->pfc->info->nr_groups; } static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, @@ -50,16 +46,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->pads[selector].name; + return pmx->pfc->info->groups[selector].name; } -static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, +static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - *pins = &pmx->pads[group].number; - *num_pins = 1; + *pins = pmx->pfc->info->groups[selector].pins; + *num_pins = pmx->pfc->info->groups[selector].nr_pins; return 0; } @@ -81,7 +77,7 @@ static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->nr_functions; + return pmx->pfc->info->nr_functions; } static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, @@ -89,30 +85,67 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->functions[selector]->name; + return pmx->pfc->info->functions[selector].name; } -static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func, +static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **groups, unsigned * const num_groups) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - *groups = &pmx->functions[func]->name; - *num_groups = 1; + *groups = pmx->pfc->info->functions[selector].groups; + *num_groups = pmx->pfc->info->functions[selector].nr_groups; return 0; } -static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func, +static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { - return 0; + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; + unsigned long flags; + unsigned int i; + int ret = -EINVAL; + + spin_lock_irqsave(&pfc->lock, flags); + + for (i = 0; i < grp->nr_pins; ++i) { + if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION, + GPIO_CFG_DRYRUN)) + goto done; + + if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION, + GPIO_CFG_REQ)) + goto done; + } + + ret = 0; + +done: + spin_unlock_irqrestore(&pfc->lock, flags); + return ret; } -static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, +static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; + unsigned long flags; + unsigned int i; + + spin_lock_irqsave(&pfc->lock, flags); + + for (i = 0; i < grp->nr_pins; ++i) + sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION, + GPIO_CFG_FREE); + + spin_unlock_irqrestore(&pfc->lock, flags); } static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, @@ -234,8 +267,8 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = { .get_functions_count = sh_pfc_get_functions_count, .get_function_name = sh_pfc_get_function_name, .get_function_groups = sh_pfc_get_function_groups, - .enable = sh_pfc_noop_enable, - .disable = sh_pfc_noop_disable, + .enable = sh_pfc_func_enable, + .disable = sh_pfc_func_disable, .gpio_request_enable = sh_pfc_gpio_request_enable, .gpio_disable_free = sh_pfc_gpio_disable_free, .gpio_set_direction = sh_pfc_gpio_set_direction, @@ -312,10 +345,10 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) nr_ranges = pfc->info->nr_ranges; } - pmx->pads = devm_kzalloc(pfc->dev, - sizeof(*pmx->pads) * pfc->info->nr_pins, + pmx->pins = devm_kzalloc(pfc->dev, + sizeof(*pmx->pins) * pfc->info->nr_pins, GFP_KERNEL); - if (unlikely(!pmx->pads)) + if (unlikely(!pmx->pins)) return -ENOMEM; for (i = 0, nr_pins = 0; i < nr_ranges; ++i) { @@ -324,7 +357,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) for (number = range->begin; number <= range->end; number++, nr_pins++) { - struct pinctrl_pin_desc *pin = &pmx->pads[nr_pins]; + struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins]; struct sh_pfc_pin *info = &pfc->info->pins[nr_pins]; pin->number = number; @@ -337,37 +370,10 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) return nr_ranges; } -static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) -{ - int i, fn; - - for (i = 0; i < pfc->info->nr_func_gpios; i++) { - struct pinmux_func *func = pfc->info->func_gpios + i; - - if (func->enum_id) - pmx->nr_functions++; - } - - pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * - sizeof(*pmx->functions), GFP_KERNEL); - if (unlikely(!pmx->functions)) - return -ENOMEM; - - for (i = fn = 0; i < pfc->info->nr_func_gpios; i++) { - struct pinmux_func *func = pfc->info->func_gpios + i; - - if (func->enum_id) - pmx->functions[fn++] = func; - } - - return 0; -} - int sh_pfc_register_pinctrl(struct sh_pfc *pfc) { struct sh_pfc_pinctrl *pmx; int nr_ranges; - int ret; pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); if (unlikely(!pmx)) @@ -380,16 +386,12 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) if (unlikely(nr_ranges < 0)) return nr_ranges; - ret = sh_pfc_map_functions(pfc, pmx); - if (unlikely(ret != 0)) - return ret; - pmx->pctl_desc.name = DRV_NAME; pmx->pctl_desc.owner = THIS_MODULE; pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; - pmx->pctl_desc.pins = pmx->pads; + pmx->pctl_desc.pins = pmx->pins; pmx->pctl_desc.npins = pfc->info->nr_pins; pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index dbcaa600ccc6..028e29ae0727 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -16,6 +16,8 @@ typedef unsigned short pinmux_enum_t; +#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1) + enum { PINMUX_TYPE_NONE, @@ -40,6 +42,34 @@ struct sh_pfc_pin { const char *name; }; +#define SH_PFC_PIN_GROUP(n) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .mux = n##_mux, \ + .nr_pins = ARRAY_SIZE(n##_pins), \ + } + +struct sh_pfc_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int *mux; + unsigned int nr_pins; +}; + +#define SH_PFC_FUNCTION(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .nr_groups = ARRAY_SIZE(n##_groups), \ + } + +struct sh_pfc_function { + const char *name; + const char * const *groups; + unsigned int nr_groups; +}; + struct pinmux_func { const pinmux_enum_t enum_id; const char *name; @@ -113,6 +143,11 @@ struct sh_pfc_soc_info { unsigned int nr_pins; const struct pinmux_range *ranges; unsigned int nr_ranges; + const struct sh_pfc_pin_group *groups; + unsigned int nr_groups; + const struct sh_pfc_function *functions; + unsigned int nr_functions; + struct pinmux_func *func_gpios; unsigned int nr_func_gpios; From 631b09d1150fd66b3815253ed6e6c30ac5040efc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 091/307] sh: sh7203: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c index 96c6c2634cb4..eef17dcc3a41 100644 --- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c @@ -8,12 +8,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7203_pfc_resources[] = { + [0] = { + .start = 0xfffe3800, + .end = 0xfffe3a9f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7203", NULL, 0); + return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources, + ARRAY_SIZE(sh7203_pfc_resources)); } arch_initcall(plat_pinmux_setup); From b9bcda43bfa463630b8f60c74246f66489b7726a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 092/307] sh: sh7264: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c index b1b7c1bae127..569decbd6d93 100644 --- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c @@ -8,12 +8,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7264_pfc_resources[] = { + [0] = { + .start = 0xfffe3800, + .end = 0xfffe393f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7264", NULL, 0); + return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources, + ARRAY_SIZE(sh7264_pfc_resources)); } arch_initcall(plat_pinmux_setup); From a3475f0072a16c8c3e2be2f737315f021e7ace64 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 093/307] sh: sh7269: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c index dc2a86830456..1825b0bd523d 100644 --- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c @@ -13,8 +13,17 @@ #include #include +static struct resource sh7269_pfc_resources[] = { + [0] = { + .start = 0xfffe3800, + .end = 0xfffe391f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7269", NULL, 0); + return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources, + ARRAY_SIZE(sh7269_pfc_resources)); } arch_initcall(plat_pinmux_setup); From 6e6d9ba0d1ea224a877826fc1cc0f42878b60384 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 094/307] sh: sh7720: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh3/pinmux-sh7720.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c index 7d3744ac7b08..26e90a66ebb7 100644 --- a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c @@ -8,13 +8,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7720_pfc_resources[] = { + [0] = { + .start = 0xa4050100, + .end = 0xa405016f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7720", NULL, 0); + return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources, + ARRAY_SIZE(sh7720_pfc_resources)); } - arch_initcall(plat_pinmux_setup); From 6ca1fa5ce7b464ee8e8a398985c84ae629ec6964 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 095/307] sh: sh7722: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c index d9bcc4290997..271bbc864929 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c @@ -1,10 +1,20 @@ +#include #include #include +#include #include +static struct resource sh7722_pfc_resources[] = { + [0] = { + .start = 0xa4050100, + .end = 0xa405018f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7722", NULL, 0); + return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources, + ARRAY_SIZE(sh7722_pfc_resources)); } - arch_initcall(plat_pinmux_setup); From 6b4644f54b0922ecb6cd2d74f7d6c518b4d4f2c9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 096/307] sh: sh7723: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c index bcec7ad7f783..99c637d5bf7a 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c @@ -8,13 +8,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7723_pfc_resources[] = { + [0] = { + .start = 0xa4050100, + .end = 0xa405016f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7723", NULL, 0); + return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources, + ARRAY_SIZE(sh7723_pfc_resources)); } - arch_initcall(plat_pinmux_setup); From 42954cff85a3f489c39571c0ddcd702d1988adca Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 097/307] sh: sh7724: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c index 5c3541d6aed8..63be4749e341 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c @@ -13,12 +13,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7724_pfc_resources[] = { + [0] = { + .start = 0xa4050100, + .end = 0xa405016f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7724", NULL, 0); + return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources, + ARRAY_SIZE(sh7724_pfc_resources)); } arch_initcall(plat_pinmux_setup); From 0f4ad41e8323541ffc2b6dc0eb7b5c352291a249 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 098/307] sh: sh7757: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c index cda6bd177b8c..567745d44221 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c @@ -13,12 +13,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7757_pfc_resources[] = { + [0] = { + .start = 0xffec0000, + .end = 0xffec008f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7757", NULL, 0); + return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources, + ARRAY_SIZE(sh7757_pfc_resources)); } arch_initcall(plat_pinmux_setup); From 6b1a26379da9539a8770ec597c1f4c96581d783d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 099/307] sh: sh7785: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c index 01055b809f64..e336ab8b5125 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c @@ -8,13 +8,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7785_pfc_resources[] = { + [0] = { + .start = 0xffe70000, + .end = 0xffe7008f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7785", NULL, 0); + return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources, + ARRAY_SIZE(sh7785_pfc_resources)); } - arch_initcall(plat_pinmux_setup); From a9fb0503d809f7ac2670ff3f57862393d345fc39 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 100/307] sh: sh7786: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c index 3061778d55da..9a459556a2f7 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c @@ -13,13 +13,23 @@ * for more details. */ +#include #include #include +#include #include +static struct resource sh7786_pfc_resources[] = { + [0] = { + .start = 0xffcc0000, + .end = 0xffcc008f, + .flags = IORESOURCE_MEM, + }, +}; + static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7786", NULL, 0); + return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources, + ARRAY_SIZE(sh7786_pfc_resources)); } - arch_initcall(plat_pinmux_setup); From a4b5a5e134c81660bd04914daec470fb72ee332b Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 19:23:58 +0100 Subject: [PATCH 101/307] sh: shx3: Add pin control resources Add memory resources for the pin control platform device to let the sh-pfc driver ioremap() registers properly instead of evily casting register physical addresses to virtual addresses. The memory resource address range has been extracted from the config and data registes lists in the sh-pfc driver. Signed-off-by: Laurent Pinchart --- arch/sh/kernel/cpu/sh4a/pinmux-shx3.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c index ace84acc55ea..444bf25c60fa 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c @@ -7,12 +7,23 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ +#include #include #include +#include #include -static int __init shx3_pinmux_setup(void) +static struct resource shx3_pfc_resources[] = { + [0] = { + .start = 0xffc70000, + .end = 0xffc7001f, + .flags = IORESOURCE_MEM, + }, +}; + +static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-shx3", NULL, 0); + return sh_pfc_register("pfc-shx3", shx3_pfc_resources, + ARRAY_SIZE(shx3_pfc_resources)); } -arch_initcall(shx3_pinmux_setup); +arch_initcall(plat_pinmux_setup); From fd9d05b0fdb0a8a2bbe2451b9e520547813d0562 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Mon, 11 Mar 2013 22:08:12 +0800 Subject: [PATCH 102/307] sh-pfc: Fix return value check in sh_pfc_register_pinctrl() In case of error, the function pinctrl_register() returns NULL not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index c7f3c406f9de..3e49bf0eac25 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -395,8 +395,8 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) pmx->pctl_desc.npins = pfc->info->nr_pins; pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); - if (IS_ERR(pmx->pctl)) - return PTR_ERR(pmx->pctl); + if (pmx->pctl == NULL) + return -EINVAL; return 0; } From 41f1219fae987f97787677d3a91c2f33ca9bab98 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 15 Feb 2013 02:04:55 +0100 Subject: [PATCH 103/307] sh-pfc: Move GPIO registers access functions to gpio.c Move the sh_pfc_setup_data_regs(), sh_pfc_setup_data_reg(), sh_pfc_get_data_reg(), sh_pfc_read_bit() and sh_pfc_write_bit() function to gpio.c as they belong to the GPIO implementation. Inline sh_pfc_read_bit() and sh_pfc_write_bit() in their only call location. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 110 ++-------------------------------- drivers/pinctrl/sh-pfc/core.h | 11 ++-- drivers/pinctrl/sh-pfc/gpio.c | 92 ++++++++++++++++++++++++++-- 3 files changed, 97 insertions(+), 116 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 798248261f30..49fde283decd 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -55,8 +55,7 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) return 0; } -static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, - unsigned long address) +void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address) { struct sh_pfc_window *window; int k; @@ -111,8 +110,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) return 1; } -static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width) +unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, + unsigned long reg_width) { switch (reg_width) { case 8: @@ -127,8 +126,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, return 0; } -static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width, unsigned long data) +void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, + unsigned long data) { switch (reg_width) { case 8: @@ -145,37 +144,6 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, BUG(); } -int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos) -{ - unsigned long pos; - - pos = dr->reg_width - (in_pos + 1); - - pr_debug("read_bit: addr = %lx, pos = %ld, " - "r_width = %ld\n", dr->reg, pos, dr->reg_width); - - return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; -} - -void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, - unsigned long value) -{ - unsigned long pos; - - pos = dr->reg_width - (in_pos + 1); - - pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " - "r_width = %ld\n", - dr->reg, !!value, pos, dr->reg_width); - - if (value) - set_bit(pos, &dr->reg_shadow); - else - clear_bit(pos, &dr->reg_shadow); - - sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); -} - static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, struct pinmux_cfg_reg *crp, unsigned long in_pos, @@ -242,73 +210,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); } -static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) -{ - struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; - struct pinmux_data_reg *data_reg; - int k, n; - - k = 0; - while (1) { - data_reg = pfc->info->data_regs + k; - - if (!data_reg->reg_width) - break; - - data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); - - for (n = 0; n < data_reg->reg_width; n++) { - if (data_reg->enum_ids[n] == gpiop->enum_id) { - gpiop->flags &= ~PINMUX_FLAG_DREG; - gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); - gpiop->flags &= ~PINMUX_FLAG_DBIT; - gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); - return; - } - } - k++; - } - - BUG(); -} - -static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) -{ - struct pinmux_data_reg *drp; - int k; - - for (k = 0; k < pfc->info->nr_pins; k++) { - if (pfc->info->pins[k].enum_id == 0) - continue; - - sh_pfc_setup_data_reg(pfc, k); - } - - k = 0; - while (1) { - drp = pfc->info->data_regs + k; - - if (!drp->reg_width) - break; - - drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, - drp->reg_width); - k++; - } -} - -void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, - struct pinmux_data_reg **drp, int *bitp) -{ - struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio); - int k, n; - - k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; - n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; - *drp = pfc->info->data_regs + k; - *bitp = n; -} - static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, struct pinmux_cfg_reg **crp, int *fieldp, int *valuep, unsigned long **cntp) @@ -518,7 +419,6 @@ static int sh_pfc_probe(struct platform_device *pdev) spin_lock_init(&pfc->lock); pinctrl_provide_dummies(); - sh_pfc_setup_data_regs(pfc); /* * Initialize pinctrl bindings first diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index b8b3e872cc19..434b62868764 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -46,11 +46,12 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc); int sh_pfc_register_pinctrl(struct sh_pfc *pfc); int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); -int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos); -void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, - unsigned long value); -void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, - struct pinmux_data_reg **drp, int *bitp); +void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address); +unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, + unsigned long reg_width); +void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, + unsigned long data); + struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, int cfg_mode); diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 806e2dd62137..027c77762d8f 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -36,6 +36,71 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) return gpio_to_pfc_chip(gc)->pfc; } +static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio, + struct pinmux_data_reg **dr, unsigned int *bit) +{ + struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio); + + *dr = pfc->info->data_regs + + ((gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT); + *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; +} + +static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) +{ + struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; + struct pinmux_data_reg *data_reg; + int k, n; + + k = 0; + while (1) { + data_reg = pfc->info->data_regs + k; + + if (!data_reg->reg_width) + break; + + data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); + + for (n = 0; n < data_reg->reg_width; n++) { + if (data_reg->enum_ids[n] == gpiop->enum_id) { + gpiop->flags &= ~PINMUX_FLAG_DREG; + gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); + gpiop->flags &= ~PINMUX_FLAG_DBIT; + gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); + return; + } + } + k++; + } + + BUG(); +} + +static void gpio_setup_data_regs(struct sh_pfc *pfc) +{ + struct pinmux_data_reg *drp; + int k; + + for (k = 0; k < pfc->info->nr_pins; k++) { + if (pfc->info->pins[k].enum_id == 0) + continue; + + gpio_setup_data_reg(pfc, k); + } + + k = 0; + while (1) { + drp = pfc->info->data_regs + k; + + if (!drp->reg_width) + break; + + drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, + drp->reg_width); + k++; + } +} + /* ----------------------------------------------------------------------------- * Pin GPIOs */ @@ -59,10 +124,19 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value) { struct pinmux_data_reg *dr; - int bit; + unsigned long pos; + unsigned int bit; - sh_pfc_get_data_reg(pfc, offset, &dr, &bit); - sh_pfc_write_bit(dr, bit, value); + gpio_get_data_reg(pfc, offset, &dr, &bit); + + pos = dr->reg_width - (bit + 1); + + if (value) + set_bit(pos, &dr->reg_shadow); + else + clear_bit(pos, &dr->reg_shadow); + + sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); } static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) @@ -82,10 +156,14 @@ static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); struct pinmux_data_reg *dr; - int bit; + unsigned long pos; + unsigned int bit; - sh_pfc_get_data_reg(pfc, offset, &dr, &bit); - return sh_pfc_read_bit(dr, bit); + gpio_get_data_reg(pfc, offset, &dr, &bit); + + pos = dr->reg_width - (bit + 1); + + return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; } static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) @@ -226,6 +304,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) unsigned int i; int ret; + gpio_setup_data_regs(pfc); + /* Register the real GPIOs chip. */ chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); if (IS_ERR(chip)) From e51d5343ffc4b81172178e51e6ca2ee00da67045 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 17 Feb 2013 00:26:33 +0100 Subject: [PATCH 104/307] sh-pfc: Don't map data registers individually All data registers are located in the same memory resource. Locate the mapped resource at initializat time and use it directly instead of computing a mapped address for each register. This gets rid of the mapped_reg field of the pinmux_data_reg structure. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 3 +- drivers/pinctrl/sh-pfc/core.h | 1 - drivers/pinctrl/sh-pfc/gpio.c | 136 +++++++++++++++++++------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 1 - 4 files changed, 85 insertions(+), 56 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 49fde283decd..e847d1683546 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -55,7 +55,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) return 0; } -void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address) +static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, + unsigned long address) { struct sh_pfc_window *window; int k; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 434b62868764..1c3816d60b4d 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -46,7 +46,6 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc); int sh_pfc_register_pinctrl(struct sh_pfc *pfc); int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); -void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address); unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned long reg_width); void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 027c77762d8f..b370d2865041 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -24,6 +24,8 @@ struct sh_pfc_chip { struct sh_pfc *pfc; struct gpio_chip gpio_chip; + + struct sh_pfc_window *mem; }; static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) @@ -46,59 +48,77 @@ static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio, *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; } +static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, + const struct pinmux_data_reg *dreg) +{ + void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; + + return sh_pfc_read_raw_reg(mem, dreg->reg_width); +} + +static void gpio_write_data_reg(struct sh_pfc_chip *chip, + const struct pinmux_data_reg *dreg, + unsigned long value) +{ + void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; + + sh_pfc_write_raw_reg(mem, dreg->reg_width, value); +} + static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) { struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; - struct pinmux_data_reg *data_reg; - int k, n; + const struct pinmux_data_reg *dreg; + unsigned int bit; + unsigned int i; - k = 0; - while (1) { - data_reg = pfc->info->data_regs + k; - - if (!data_reg->reg_width) - break; - - data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); - - for (n = 0; n < data_reg->reg_width; n++) { - if (data_reg->enum_ids[n] == gpiop->enum_id) { + for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { + for (bit = 0; bit < dreg->reg_width; bit++) { + if (dreg->enum_ids[bit] == gpiop->enum_id) { gpiop->flags &= ~PINMUX_FLAG_DREG; - gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); + gpiop->flags |= i << PINMUX_FLAG_DREG_SHIFT; gpiop->flags &= ~PINMUX_FLAG_DBIT; - gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); + gpiop->flags |= bit << PINMUX_FLAG_DBIT_SHIFT; return; } } - k++; } BUG(); } -static void gpio_setup_data_regs(struct sh_pfc *pfc) +static int gpio_setup_data_regs(struct sh_pfc_chip *chip) { - struct pinmux_data_reg *drp; - int k; + struct sh_pfc *pfc = chip->pfc; + unsigned long addr = pfc->info->data_regs[0].reg; + struct pinmux_data_reg *dreg; + unsigned int i; - for (k = 0; k < pfc->info->nr_pins; k++) { - if (pfc->info->pins[k].enum_id == 0) + /* Find the window that contain the GPIO registers. */ + for (i = 0; i < pfc->num_windows; ++i) { + struct sh_pfc_window *window = &pfc->window[i]; + + if (addr >= window->phys && addr < window->phys + window->size) + break; + } + + if (i == pfc->num_windows) + return -EINVAL; + + /* GPIO data registers must be in the first memory resource. */ + chip->mem = &pfc->window[i]; + + for (dreg = pfc->info->data_regs; dreg->reg; ++dreg) + dreg->reg_shadow = gpio_read_data_reg(chip, dreg); + + for (i = 0; i < pfc->info->nr_pins; i++) { + if (pfc->info->pins[i].enum_id == 0) continue; - gpio_setup_data_reg(pfc, k); + gpio_setup_data_reg(pfc, i); } - k = 0; - while (1) { - drp = pfc->info->data_regs + k; - - if (!drp->reg_width) - break; - - drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, - drp->reg_width); - k++; - } + return 0; } /* ----------------------------------------------------------------------------- @@ -121,22 +141,23 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) return pinctrl_free_gpio(offset); } -static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value) +static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, + int value) { - struct pinmux_data_reg *dr; + struct pinmux_data_reg *dreg; unsigned long pos; unsigned int bit; - gpio_get_data_reg(pfc, offset, &dr, &bit); + gpio_get_data_reg(chip->pfc, offset, &dreg, &bit); - pos = dr->reg_width - (bit + 1); + pos = dreg->reg_width - (bit + 1); if (value) - set_bit(pos, &dr->reg_shadow); + set_bit(pos, &dreg->reg_shadow); else - clear_bit(pos, &dr->reg_shadow); + clear_bit(pos, &dreg->reg_shadow); - sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); + gpio_write_data_reg(chip, dreg, dreg->reg_shadow); } static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) @@ -147,28 +168,28 @@ static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, int value) { - gpio_pin_set_value(gpio_to_pfc(gc), offset, value); + gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); return pinctrl_gpio_direction_output(offset); } static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) { - struct sh_pfc *pfc = gpio_to_pfc(gc); - struct pinmux_data_reg *dr; + struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); + struct pinmux_data_reg *dreg; unsigned long pos; unsigned int bit; - gpio_get_data_reg(pfc, offset, &dr, &bit); + gpio_get_data_reg(chip->pfc, offset, &dreg, &bit); - pos = dr->reg_width - (bit + 1); + pos = dreg->reg_width - (bit + 1); - return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; + return (gpio_read_data_reg(chip, dreg) >> pos) & 1; } static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) { - gpio_pin_set_value(gpio_to_pfc(gc), offset, value); + gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); } static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) @@ -188,10 +209,15 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) return -ENOSYS; } -static void gpio_pin_setup(struct sh_pfc_chip *chip) +static int gpio_pin_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; + int ret; + + ret = gpio_setup_data_regs(chip); + if (ret < 0) + return ret; gc->request = gpio_pin_request; gc->free = gpio_pin_free; @@ -206,6 +232,8 @@ static void gpio_pin_setup(struct sh_pfc_chip *chip) gc->owner = THIS_MODULE; gc->base = 0; gc->ngpio = pfc->nr_pins; + + return 0; } /* ----------------------------------------------------------------------------- @@ -252,7 +280,7 @@ static void gpio_function_free(struct gpio_chip *gc, unsigned offset) spin_unlock_irqrestore(&pfc->lock, flags); } -static void gpio_function_setup(struct sh_pfc_chip *chip) +static int gpio_function_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; @@ -264,6 +292,8 @@ static void gpio_function_setup(struct sh_pfc_chip *chip) gc->owner = THIS_MODULE; gc->base = pfc->nr_pins; gc->ngpio = pfc->info->nr_func_gpios; + + return 0; } /* ----------------------------------------------------------------------------- @@ -271,7 +301,7 @@ static void gpio_function_setup(struct sh_pfc_chip *chip) */ static struct sh_pfc_chip * -sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *)) +sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *)) { struct sh_pfc_chip *chip; int ret; @@ -282,7 +312,9 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *)) chip->pfc = pfc; - setup(chip); + ret = setup(chip); + if (ret < 0) + return ERR_PTR(ret); ret = gpiochip_add(&chip->gpio_chip); if (unlikely(ret < 0)) @@ -304,8 +336,6 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) unsigned int i; int ret; - gpio_setup_data_regs(pfc); - /* Register the real GPIOs chip. */ chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); if (IS_ERR(chip)) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 028e29ae0727..ba3697dac869 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -110,7 +110,6 @@ struct pinmux_cfg_reg { struct pinmux_data_reg { unsigned long reg, reg_width, reg_shadow; pinmux_enum_t *enum_ids; - void __iomem *mapped_reg; }; #define PINMUX_DATA_REG(name, r, r_width) \ From bee9f22ba196b0fa3b07507f685eb92b2075e1d1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 23:39:07 +0100 Subject: [PATCH 105/307] sh-pfc: Drop unused support for 1:1 physical to virtual memory mappings Now that all PFC platform devices provide memory resources support for registers without an associated memory resource isn't used anymore. Drop it. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index e847d1683546..cadfb376cb21 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -30,10 +30,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) struct resource *res; int k; - if (pdev->num_resources == 0) { - pfc->num_windows = 0; - return 0; - } + if (pdev->num_resources == 0) + return -EINVAL; pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * sizeof(*pfc->window), GFP_NOWAIT); @@ -59,11 +57,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address) { struct sh_pfc_window *window; - int k; + unsigned int i; /* scan through physical windows and convert address */ - for (k = 0; k < pfc->num_windows; k++) { - window = pfc->window + k; + for (i = 0; i < pfc->num_windows; i++) { + window = pfc->window + i; if (address < window->phys) continue; @@ -74,8 +72,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, return window->virt + (address - window->phys); } - /* no windows defined, register must be 1:1 mapped virt:phys */ - return (void __iomem *)address; + BUG(); } struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin) From 51cb226b359bc48fed4a92b9bbd9af34640b1be8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 18:34:32 +0100 Subject: [PATCH 106/307] sh-pfc: Don't modify pinmux_data_reg SoC data The pinmux_data_reg structure supplied in SoC data contains information about data registers. It's abused to store per-device mapped iomem and shadow values. Move those fields out of the pinmux_data_reg structure into the per-device sh_pfc_chip structure. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/gpio.c | 58 +++++++++++++++++++++++---------- drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +- 2 files changed, 41 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index b370d2865041..55eaf75decff 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -21,11 +21,17 @@ #include "core.h" +struct sh_pfc_gpio_data_reg { + const struct pinmux_data_reg *info; + unsigned long shadow; +}; + struct sh_pfc_chip { struct sh_pfc *pfc; struct gpio_chip gpio_chip; struct sh_pfc_window *mem; + struct sh_pfc_gpio_data_reg *regs; }; static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) @@ -38,13 +44,16 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) return gpio_to_pfc_chip(gc)->pfc; } -static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio, - struct pinmux_data_reg **dr, unsigned int *bit) +static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio, + struct sh_pfc_gpio_data_reg **reg, + unsigned int *bit) { - struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio); + struct sh_pfc_pin *gpiop = sh_pfc_get_pin(chip->pfc, gpio); + unsigned int reg_idx; - *dr = pfc->info->data_regs - + ((gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT); + reg_idx = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; + + *reg = &chip->regs[reg_idx]; *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; } @@ -91,7 +100,7 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; unsigned long addr = pfc->info->data_regs[0].reg; - struct pinmux_data_reg *dreg; + const struct pinmux_data_reg *dreg; unsigned int i; /* Find the window that contain the GPIO registers. */ @@ -108,8 +117,21 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip) /* GPIO data registers must be in the first memory resource. */ chip->mem = &pfc->window[i]; - for (dreg = pfc->info->data_regs; dreg->reg; ++dreg) - dreg->reg_shadow = gpio_read_data_reg(chip, dreg); + /* Count the number of data registers, allocate memory and initialize + * them. + */ + for (i = 0; pfc->info->data_regs[i].reg_width; ++i) + ; + + chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs), + GFP_KERNEL); + if (chip->regs == NULL) + return -ENOMEM; + + for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { + chip->regs[i].info = dreg; + chip->regs[i].shadow = gpio_read_data_reg(chip, dreg); + } for (i = 0; i < pfc->info->nr_pins; i++) { if (pfc->info->pins[i].enum_id == 0) @@ -144,20 +166,20 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, int value) { - struct pinmux_data_reg *dreg; + struct sh_pfc_gpio_data_reg *reg; unsigned long pos; unsigned int bit; - gpio_get_data_reg(chip->pfc, offset, &dreg, &bit); + gpio_get_data_reg(chip, offset, ®, &bit); - pos = dreg->reg_width - (bit + 1); + pos = reg->info->reg_width - (bit + 1); if (value) - set_bit(pos, &dreg->reg_shadow); + set_bit(pos, ®->shadow); else - clear_bit(pos, &dreg->reg_shadow); + clear_bit(pos, ®->shadow); - gpio_write_data_reg(chip, dreg, dreg->reg_shadow); + gpio_write_data_reg(chip, reg->info, reg->shadow); } static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) @@ -176,15 +198,15 @@ static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) { struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); - struct pinmux_data_reg *dreg; + struct sh_pfc_gpio_data_reg *reg; unsigned long pos; unsigned int bit; - gpio_get_data_reg(chip->pfc, offset, &dreg, &bit); + gpio_get_data_reg(chip, offset, ®, &bit); - pos = dreg->reg_width - (bit + 1); + pos = reg->info->reg_width - (bit + 1); - return (gpio_read_data_reg(chip, dreg) >> pos) & 1; + return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; } static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index ba3697dac869..e6a51a9e47ba 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -108,7 +108,7 @@ struct pinmux_cfg_reg { .enum_ids = (pinmux_enum_t []) struct pinmux_data_reg { - unsigned long reg, reg_width, reg_shadow; + unsigned long reg, reg_width; pinmux_enum_t *enum_ids; }; From 1a0039dce269317a843d4fc85c4a3430b484bc2d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 8 Mar 2013 17:43:54 +0100 Subject: [PATCH 107/307] sh-pfc: Don't modify sh_pfc_pin SoC data The sh_pfc_pin structure supplied in SoC data contains information about pin configuration and name. It's abused to store GPIO data registers information and pin config type. Move those fields out of the pinmux_data_reg structure into the new sh_pfc_gpio_pin and sh_pfc_pin_config structures. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 14 +++----- drivers/pinctrl/sh-pfc/core.h | 2 +- drivers/pinctrl/sh-pfc/gpio.c | 49 +++++++++++++++----------- drivers/pinctrl/sh-pfc/pinctrl.c | 59 +++++++++++++++++++------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 7 ---- 5 files changed, 69 insertions(+), 62 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index cadfb376cb21..19735012ffb4 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -75,26 +75,25 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, BUG(); } -struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin) +int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) { unsigned int offset; unsigned int i; if (pfc->info->ranges == NULL) - return &pfc->info->pins[pin]; + return pin; for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) { const struct pinmux_range *range = &pfc->info->ranges[i]; if (pin <= range->end) return pin >= range->begin - ? &pfc->info->pins[offset + pin - range->begin] - : NULL; + ? offset + pin - range->begin : -1; offset += range->end - range->begin + 1; } - return NULL; + return -1; } static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) @@ -393,11 +392,6 @@ static int sh_pfc_probe(struct platform_device *pdev) struct sh_pfc *pfc; int ret; - /* - * Ensure that the type encoding fits - */ - BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1)); - info = pdev->id_entry->driver_data ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; if (info == NULL) diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 1c3816d60b4d..6db54aa083f2 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -51,7 +51,7 @@ unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, unsigned long data); -struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin); +int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, int cfg_mode); diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 55eaf75decff..ce074b22f426 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -26,12 +26,18 @@ struct sh_pfc_gpio_data_reg { unsigned long shadow; }; -struct sh_pfc_chip { - struct sh_pfc *pfc; - struct gpio_chip gpio_chip; +struct sh_pfc_gpio_pin { + u8 dbit; + u8 dreg; +}; - struct sh_pfc_window *mem; +struct sh_pfc_chip { + struct sh_pfc *pfc; + struct gpio_chip gpio_chip; + + struct sh_pfc_window *mem; struct sh_pfc_gpio_data_reg *regs; + struct sh_pfc_gpio_pin *pins; }; static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) @@ -48,13 +54,11 @@ static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio, struct sh_pfc_gpio_data_reg **reg, unsigned int *bit) { - struct sh_pfc_pin *gpiop = sh_pfc_get_pin(chip->pfc, gpio); - unsigned int reg_idx; + int idx = sh_pfc_get_pin_index(chip->pfc, gpio); + struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; - reg_idx = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; - - *reg = &chip->regs[reg_idx]; - *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; + *reg = &chip->regs[gpio_pin->dreg]; + *bit = gpio_pin->dbit; } static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, @@ -74,20 +78,20 @@ static void gpio_write_data_reg(struct sh_pfc_chip *chip, sh_pfc_write_raw_reg(mem, dreg->reg_width, value); } -static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) +static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio) { - struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; + struct sh_pfc *pfc = chip->pfc; + struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio]; + struct sh_pfc_pin *pin = &pfc->info->pins[gpio]; const struct pinmux_data_reg *dreg; unsigned int bit; unsigned int i; for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { for (bit = 0; bit < dreg->reg_width; bit++) { - if (dreg->enum_ids[bit] == gpiop->enum_id) { - gpiop->flags &= ~PINMUX_FLAG_DREG; - gpiop->flags |= i << PINMUX_FLAG_DREG_SHIFT; - gpiop->flags &= ~PINMUX_FLAG_DBIT; - gpiop->flags |= bit << PINMUX_FLAG_DBIT_SHIFT; + if (dreg->enum_ids[bit] == pin->enum_id) { + gpio_pin->dreg = i; + gpio_pin->dbit = bit; return; } } @@ -137,7 +141,7 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip) if (pfc->info->pins[i].enum_id == 0) continue; - gpio_setup_data_reg(pfc, i); + gpio_setup_data_reg(chip, i); } return 0; @@ -150,9 +154,9 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip) static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); + int idx = sh_pfc_get_pin_index(pfc, offset); - if (pin == NULL || pin->enum_id == 0) + if (idx < 0 || pfc->info->pins[idx].enum_id == 0) return -EINVAL; return pinctrl_request_gpio(offset); @@ -237,6 +241,11 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) struct gpio_chip *gc = &chip->gpio_chip; int ret; + chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins), + GFP_KERNEL); + if (chip->pins == NULL) + return -ENOMEM; + ret = gpio_setup_data_regs(chip); if (ret < 0) return ret; diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 3e49bf0eac25..ef5cf5d8298f 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -25,6 +25,10 @@ #include "core.h" +struct sh_pfc_pin_config { + u32 type; +}; + struct sh_pfc_pinctrl { struct pinctrl_dev *pctl; struct pinctrl_desc pctl_desc; @@ -32,6 +36,7 @@ struct sh_pfc_pinctrl { struct sh_pfc *pfc; struct pinctrl_pin_desc *pins; + struct sh_pfc_pin_config *configs; }; static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) @@ -148,30 +153,30 @@ static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, spin_unlock_irqrestore(&pfc->lock, flags); } -static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, +static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset, int new_type) { - struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); + struct sh_pfc *pfc = pmx->pfc; + int idx = sh_pfc_get_pin_index(pfc, offset); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + struct sh_pfc_pin *pin = &pfc->info->pins[idx]; unsigned int mark = pin->enum_id; unsigned long flags; - int pinmux_type; int ret = -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pin->flags & PINMUX_FLAG_TYPE; - /* * See if the present config needs to first be de-configured. */ - switch (pinmux_type) { + switch (cfg->type) { case PINMUX_TYPE_GPIO: break; case PINMUX_TYPE_OUTPUT: case PINMUX_TYPE_INPUT: case PINMUX_TYPE_INPUT_PULLUP: case PINMUX_TYPE_INPUT_PULLDOWN: - sh_pfc_config_mux(pfc, mark, pinmux_type, GPIO_CFG_FREE); + sh_pfc_config_mux(pfc, mark, cfg->type, GPIO_CFG_FREE); break; default: goto err; @@ -189,8 +194,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0) goto err; - pin->flags &= ~PINMUX_FLAG_TYPE; - pin->flags |= new_type; + cfg->type = new_type; ret = 0; @@ -206,22 +210,21 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); + int idx = sh_pfc_get_pin_index(pfc, offset); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; - int ret, pinmux_type; + int ret; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pin->flags & PINMUX_FLAG_TYPE; - - switch (pinmux_type) { + switch (cfg->type) { case PINMUX_TYPE_GPIO: case PINMUX_TYPE_INPUT: case PINMUX_TYPE_OUTPUT: break; case PINMUX_TYPE_FUNCTION: default: - pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type); + pr_err("Unsupported mux type (%d), bailing...\n", cfg->type); ret = -ENOTSUPP; goto err; } @@ -240,15 +243,14 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); + int idx = sh_pfc_get_pin_index(pfc, offset); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + struct sh_pfc_pin *pin = &pfc->info->pins[idx]; unsigned long flags; - int pinmux_type; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pin->flags & PINMUX_FLAG_TYPE; - - sh_pfc_config_mux(pfc, pin->enum_id, pinmux_type, GPIO_CFG_FREE); + sh_pfc_config_mux(pfc, pin->enum_id, cfg->type, GPIO_CFG_FREE); spin_unlock_irqrestore(&pfc->lock, flags); } @@ -260,7 +262,7 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; - return sh_pfc_reconfig_pin(pmx->pfc, offset, type); + return sh_pfc_reconfig_pin(pmx, offset, type); } static const struct pinmux_ops sh_pfc_pinmux_ops = { @@ -279,9 +281,10 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, _pin); + int idx = sh_pfc_get_pin_index(pfc, _pin); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - *config = pin->flags & PINMUX_FLAG_TYPE; + *config = cfg->type; return 0; } @@ -295,7 +298,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, if (config >= PINMUX_FLAG_TYPE) return -EINVAL; - return sh_pfc_reconfig_pin(pmx->pfc, pin, config); + return sh_pfc_reconfig_pin(pmx, pin, config); } static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, @@ -351,17 +354,25 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) if (unlikely(!pmx->pins)) return -ENOMEM; + pmx->configs = devm_kzalloc(pfc->dev, + sizeof(*pmx->configs) * pfc->info->nr_pins, + GFP_KERNEL); + if (unlikely(!pmx->configs)) + return -ENOMEM; + for (i = 0, nr_pins = 0; i < nr_ranges; ++i) { const struct pinmux_range *range = &ranges[i]; unsigned int number; for (number = range->begin; number <= range->end; number++, nr_pins++) { + struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins]; struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins]; struct sh_pfc_pin *info = &pfc->info->pins[nr_pins]; pin->number = number; pin->name = info->name; + cfg->type = PINMUX_TYPE_GPIO; } } diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index e6a51a9e47ba..6a4a62fd39ec 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -31,14 +31,8 @@ enum { PINMUX_FLAG_TYPE, /* must be last */ }; -#define PINMUX_FLAG_DBIT_SHIFT 5 -#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) -#define PINMUX_FLAG_DREG_SHIFT 10 -#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) - struct sh_pfc_pin { const pinmux_enum_t enum_id; - unsigned short flags; const char *name; }; @@ -79,7 +73,6 @@ struct pinmux_func { [gpio] = { \ .name = __stringify(gpio), \ .enum_id = data_or_mark, \ - .flags = PINMUX_TYPE_GPIO \ } #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ [gpio - (base)] = { \ From 861601de101215494e2cc7918e8633d63da490ef Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 15:29:14 +0100 Subject: [PATCH 108/307] sh-pfc: Remove configuration dry-run and free The purpose of the dry-run is to ensure that a pin about to be configured isn't in use. However, the current implementation is a no-op. This proves that the dry-run isn't essential. Remove it. Freeing configuration then becomes a no-op as well. Remove it. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 50 +++++--------------------------- drivers/pinctrl/sh-pfc/core.h | 3 +- drivers/pinctrl/sh-pfc/gpio.c | 14 +-------- drivers/pinctrl/sh-pfc/pinctrl.c | 48 ++---------------------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 5 +--- 5 files changed, 12 insertions(+), 108 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 19735012ffb4..e2864ec900f4 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -163,22 +163,6 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, } } -static int sh_pfc_read_config_reg(struct sh_pfc *pfc, - struct pinmux_cfg_reg *crp, - unsigned long field) -{ - void __iomem *mapped_reg; - unsigned long mask, pos; - - sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); - - pr_debug("read_reg: addr = %lx, field = %ld, " - "r_width = %ld, f_width = %ld\n", - crp->reg, field, crp->reg_width, crp->field_width); - - return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; -} - static void sh_pfc_write_config_reg(struct sh_pfc *pfc, struct pinmux_cfg_reg *crp, unsigned long field, unsigned long value) @@ -209,7 +193,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, struct pinmux_cfg_reg **crp, int *fieldp, - int *valuep, unsigned long **cntp) + int *valuep) { struct pinmux_cfg_reg *config_reg; unsigned long r_width, f_width, curr_width, ncomb; @@ -239,7 +223,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, *crp = config_reg; *fieldp = m; *valuep = n; - *cntp = &config_reg->cnt[m]; return 0; } } @@ -274,14 +257,12 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, return -1; } -int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, - int cfg_mode) +int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) { struct pinmux_cfg_reg *cr = NULL; pinmux_enum_t enum_id; struct pinmux_range *range; int in_range, pos, field, value; - unsigned long *cntp; switch (pinmux_type) { @@ -306,7 +287,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, break; default: - goto out_err; + return -1; } pos = 0; @@ -316,7 +297,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, while (1) { pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); if (pos <= 0) - goto out_err; + return -1; if (!enum_id) break; @@ -360,30 +341,13 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, continue; if (sh_pfc_get_config_reg(pfc, enum_id, &cr, - &field, &value, &cntp) != 0) - goto out_err; + &field, &value) != 0) + return -1; - switch (cfg_mode) { - case GPIO_CFG_DRYRUN: - if (!*cntp || - (sh_pfc_read_config_reg(pfc, cr, field) != value)) - continue; - break; - - case GPIO_CFG_REQ: - sh_pfc_write_config_reg(pfc, cr, field, value); - *cntp = *cntp + 1; - break; - - case GPIO_CFG_FREE: - *cntp = *cntp - 1; - break; - } + sh_pfc_write_config_reg(pfc, cr, field, value); } return 0; - out_err: - return -1; } static int sh_pfc_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 6db54aa083f2..7b2b4f0accfc 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -52,8 +52,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, unsigned long data); int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); -int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, - int cfg_mode); +int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); extern struct sh_pfc_soc_info r8a7740_pinmux_info; extern struct sh_pfc_soc_info r8a7779_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index ce074b22f426..761a0dad0450 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -285,10 +285,7 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) spin_lock_irqsave(&pfc->lock, flags); - if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN)) - goto done; - - if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ)) + if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION)) goto done; ret = 0; @@ -300,15 +297,6 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) static void gpio_function_free(struct gpio_chip *gc, unsigned offset) { - struct sh_pfc *pfc = gpio_to_pfc(gc); - unsigned int mark = pfc->info->func_gpios[offset].enum_id; - unsigned long flags; - - spin_lock_irqsave(&pfc->lock, flags); - - sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); - - spin_unlock_irqrestore(&pfc->lock, flags); } static int gpio_function_setup(struct sh_pfc_chip *chip) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index ef5cf5d8298f..9978ad1818fd 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -119,12 +119,7 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, spin_lock_irqsave(&pfc->lock, flags); for (i = 0; i < grp->nr_pins; ++i) { - if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION, - GPIO_CFG_DRYRUN)) - goto done; - - if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION, - GPIO_CFG_REQ)) + if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION)) goto done; } @@ -138,19 +133,6 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; - unsigned long flags; - unsigned int i; - - spin_lock_irqsave(&pfc->lock, flags); - - for (i = 0; i < grp->nr_pins; ++i) - sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION, - GPIO_CFG_FREE); - - spin_unlock_irqrestore(&pfc->lock, flags); } static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset, @@ -166,32 +148,18 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset, spin_lock_irqsave(&pfc->lock, flags); - /* - * See if the present config needs to first be de-configured. - */ switch (cfg->type) { case PINMUX_TYPE_GPIO: - break; case PINMUX_TYPE_OUTPUT: case PINMUX_TYPE_INPUT: case PINMUX_TYPE_INPUT_PULLUP: case PINMUX_TYPE_INPUT_PULLDOWN: - sh_pfc_config_mux(pfc, mark, cfg->type, GPIO_CFG_FREE); break; default: goto err; } - /* - * Dry run - */ - if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_DRYRUN) != 0) - goto err; - - /* - * Request - */ - if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0) + if (sh_pfc_config_mux(pfc, mark, new_type) != 0) goto err; cfg->type = new_type; @@ -241,18 +209,6 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - int idx = sh_pfc_get_pin_index(pfc, offset); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - unsigned long flags; - - spin_lock_irqsave(&pfc->lock, flags); - - sh_pfc_config_mux(pfc, pin->enum_id, cfg->type, GPIO_CFG_FREE); - - spin_unlock_irqrestore(&pfc->lock, flags); } static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 6a4a62fd39ec..19da3b7c57f1 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -84,19 +84,16 @@ struct pinmux_func { struct pinmux_cfg_reg { unsigned long reg, reg_width, field_width; - unsigned long *cnt; pinmux_enum_t *enum_ids; unsigned long *var_field_width; }; #define PINMUX_CFG_REG(name, r, r_width, f_width) \ .reg = r, .reg_width = r_width, .field_width = f_width, \ - .cnt = (unsigned long [r_width / f_width]) {}, \ .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ .reg = r, .reg_width = r_width, \ - .cnt = (unsigned long [r_width]) {}, \ .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ .enum_ids = (pinmux_enum_t []) @@ -155,7 +152,7 @@ struct sh_pfc_soc_info { unsigned long unlock_reg; }; -enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; +enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; /* helper macro for port */ #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) From cd3c1beecfeb757b16904386ea474d3c272de4ee Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 16 Feb 2013 18:47:05 +0100 Subject: [PATCH 109/307] sh-pfc: Constify all SoC data None of the SoC data need to be modified. Constify it. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 19 ++++++++-------- drivers/pinctrl/sh-pfc/core.h | 34 ++++++++++++++-------------- drivers/pinctrl/sh-pfc/gpio.c | 2 +- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 12 +++++----- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7203.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 12 +++++----- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 14 ++++++------ drivers/pinctrl/sh-pfc/pfc-sh7720.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7722.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7723.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7724.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7734.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7757.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7785.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-sh7786.c | 10 ++++---- drivers/pinctrl/sh-pfc/pfc-shx3.c | 10 ++++---- drivers/pinctrl/sh-pfc/pinctrl.c | 5 ++-- drivers/pinctrl/sh-pfc/sh_pfc.h | 20 ++++++++-------- 21 files changed, 125 insertions(+), 123 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index e2864ec900f4..3a949465e88e 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -96,7 +96,8 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) return -1; } -static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) +static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, + const struct pinmux_range *r) { if (enum_id < r->begin) return 0; @@ -142,7 +143,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, } static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, - struct pinmux_cfg_reg *crp, + const struct pinmux_cfg_reg *crp, unsigned long in_pos, void __iomem **mapped_regp, unsigned long *maskp, @@ -164,7 +165,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, } static void sh_pfc_write_config_reg(struct sh_pfc *pfc, - struct pinmux_cfg_reg *crp, + const struct pinmux_cfg_reg *crp, unsigned long field, unsigned long value) { void __iomem *mapped_reg; @@ -192,10 +193,10 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, } static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, - struct pinmux_cfg_reg **crp, int *fieldp, + const struct pinmux_cfg_reg **crp, int *fieldp, int *valuep) { - struct pinmux_cfg_reg *config_reg; + const struct pinmux_cfg_reg *config_reg; unsigned long r_width, f_width, curr_width, ncomb; int k, m, n, pos, bit_pos; @@ -238,7 +239,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, pinmux_enum_t *enum_idp) { - pinmux_enum_t *data = pfc->info->gpio_data; + const pinmux_enum_t *data = pfc->info->gpio_data; int k; if (pos) { @@ -259,9 +260,9 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) { - struct pinmux_cfg_reg *cr = NULL; + const struct pinmux_cfg_reg *cr = NULL; pinmux_enum_t enum_id; - struct pinmux_range *range; + const struct pinmux_range *range; int in_range, pos, field, value; switch (pinmux_type) { @@ -352,7 +353,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) static int sh_pfc_probe(struct platform_device *pdev) { - struct sh_pfc_soc_info *info; + const struct sh_pfc_soc_info *info; struct sh_pfc *pfc; int ret; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 7b2b4f0accfc..763d717ca979 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -26,7 +26,7 @@ struct sh_pfc_pinctrl; struct sh_pfc { struct device *dev; - struct sh_pfc_soc_info *info; + const struct sh_pfc_soc_info *info; spinlock_t lock; unsigned int num_windows; @@ -54,21 +54,21 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); -extern struct sh_pfc_soc_info r8a7740_pinmux_info; -extern struct sh_pfc_soc_info r8a7779_pinmux_info; -extern struct sh_pfc_soc_info sh7203_pinmux_info; -extern struct sh_pfc_soc_info sh7264_pinmux_info; -extern struct sh_pfc_soc_info sh7269_pinmux_info; -extern struct sh_pfc_soc_info sh7372_pinmux_info; -extern struct sh_pfc_soc_info sh73a0_pinmux_info; -extern struct sh_pfc_soc_info sh7720_pinmux_info; -extern struct sh_pfc_soc_info sh7722_pinmux_info; -extern struct sh_pfc_soc_info sh7723_pinmux_info; -extern struct sh_pfc_soc_info sh7724_pinmux_info; -extern struct sh_pfc_soc_info sh7734_pinmux_info; -extern struct sh_pfc_soc_info sh7757_pinmux_info; -extern struct sh_pfc_soc_info sh7785_pinmux_info; -extern struct sh_pfc_soc_info sh7786_pinmux_info; -extern struct sh_pfc_soc_info shx3_pinmux_info; +extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7779_pinmux_info; +extern const struct sh_pfc_soc_info sh7203_pinmux_info; +extern const struct sh_pfc_soc_info sh7264_pinmux_info; +extern const struct sh_pfc_soc_info sh7269_pinmux_info; +extern const struct sh_pfc_soc_info sh7372_pinmux_info; +extern const struct sh_pfc_soc_info sh73a0_pinmux_info; +extern const struct sh_pfc_soc_info sh7720_pinmux_info; +extern const struct sh_pfc_soc_info sh7722_pinmux_info; +extern const struct sh_pfc_soc_info sh7723_pinmux_info; +extern const struct sh_pfc_soc_info sh7724_pinmux_info; +extern const struct sh_pfc_soc_info sh7734_pinmux_info; +extern const struct sh_pfc_soc_info sh7757_pinmux_info; +extern const struct sh_pfc_soc_info sh7785_pinmux_info; +extern const struct sh_pfc_soc_info sh7786_pinmux_info; +extern const struct sh_pfc_soc_info shx3_pinmux_info; #endif /* __SH_PFC_CORE_H__ */ diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 761a0dad0450..480beae2ee67 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -82,7 +82,7 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio) { struct sh_pfc *pfc = chip->pfc; struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio]; - struct sh_pfc_pin *pin = &pfc->info->pins[gpio]; + const struct sh_pfc_pin *pin = &pfc->info->pins[gpio]; const struct pinmux_data_reg *dreg; unsigned int bit; unsigned int i; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index fd91381aaaf3..de13348be5c0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -577,7 +577,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ /* I/O and Pull U/D */ @@ -1660,7 +1660,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* IRQ */ GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), GPIO_FN(IRQ1), @@ -2128,7 +2128,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(TRACEAUD_FROM_MEMC), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ PORTCR(2, 0xe6050002), /* PORT2CR */ @@ -2442,7 +2442,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, @@ -2546,7 +2546,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -static struct pinmux_irq pinmux_irqs[] = { +static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20), /* IRQ1A */ PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ @@ -2581,7 +2581,7 @@ static struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ }; -struct sh_pfc_soc_info r8a7740_pinmux_info = { +const struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index e9a7ead139fa..eb5685848b68 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -631,7 +631,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ PINMUX_DATA(AVS1_MARK, FN_AVS1), @@ -1438,7 +1438,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), @@ -1710,7 +1710,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { GP_0_31_FN, FN_IP3_31_29, GP_0_30_FN, FN_IP3_26_24, @@ -2571,7 +2571,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } }, { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } }, { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } }, @@ -2587,7 +2587,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info r8a7779_pinmux_info = { +const struct sh_pfc_soc_info r8a7779_pinmux_info = { .name = "r8a7779_pfc", .unlock_reg = 0xfffc0000, /* PMMR */ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index fc4a1280accb..f63d51dc3f4c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -272,7 +272,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PA */ PINMUX_DATA(PA7_DATA, PA7_IN), @@ -819,7 +819,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ GPIO_FN(PINT7_PB), GPIO_FN(PINT6_PB), @@ -1077,7 +1077,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(LCD_DATA0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { 0, 0, 0, 0, @@ -1529,7 +1529,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { 0, 0, 0, 0, 0, 0, 0, 0, @@ -1575,7 +1575,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7203_pinmux_info = { +const struct sh_pfc_soc_info sh7203_pinmux_info = { .name = "sh7203_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index c03365cd945d..284675249ed9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -604,7 +604,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* Port A */ PINMUX_DATA(PA3_DATA, PA3_IN), @@ -1220,7 +1220,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ GPIO_FN(PINT7_PG), GPIO_FN(PINT6_PG), @@ -1470,7 +1470,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(LCD_M_DISP), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2036,7 +2036,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) { 0, 0, 0, 0, 0, 0, 0, PA3_DATA, 0, 0, 0, 0, 0, 0, 0, PA2_DATA } @@ -2114,7 +2114,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { } }; -struct sh_pfc_soc_info sh7264_pinmux_info = { +const struct sh_pfc_soc_info sh7264_pinmux_info = { .name = "sh7264_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 1fa0950519e4..4c401a74acd5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -781,7 +781,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* Port A */ PINMUX_DATA(PA1_DATA, PA1_IN), @@ -1617,7 +1617,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ GPIO_FN(IRQ7_PG), GPIO_FN(IRQ6_PG), @@ -1949,7 +1949,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(LCD_M_DISP), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ /* where Field_Width is 1 for single mode registers or 4 for upto 16 @@ -2738,7 +2738,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { 0, 0, 0, 0, 0, 0, 0, PA1_DATA, 0, 0, 0, 0, 0, 0, 0, PA0_DATA } @@ -2817,7 +2817,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { } }; -struct sh_pfc_soc_info sh7269_pinmux_info = { +const struct sh_pfc_soc_info sh7269_pinmux_info = { .name = "sh7269_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 847e0cd1b748..6b5634454956 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -368,7 +368,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), @@ -935,7 +935,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* IRQ */ GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), @@ -1202,7 +1202,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SDENC_DV_CLKI), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xE6051000), /* PORT0CR */ PORTCR(1, 0xE6051001), /* PORT1CR */ PORTCR(2, 0xE6051002), /* PORT2CR */ @@ -1474,7 +1474,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, @@ -1599,7 +1599,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) -static struct pinmux_irq pinmux_irqs[] = { +static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), @@ -1634,7 +1634,7 @@ static struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), }; -struct sh_pfc_soc_info sh7372_pinmux_info = { +const struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 9cef0d8b8ccd..3200fc2f34b1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -509,7 +509,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ /* Table 25-1 (I/O and Pull U/D) */ @@ -1543,7 +1543,7 @@ static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; -static struct pinmux_range pinmux_ranges[] = { +static const struct pinmux_range pinmux_ranges[] = { {.begin = 0, .end = 118,}, {.begin = 128, .end = 164,}, {.begin = 192, .end = 282,}, @@ -1552,7 +1552,7 @@ static struct pinmux_range pinmux_ranges[] = { #define PINMUX_FN_BASE GPIO_FN_VBUS_0 -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* Table 25-1 (Functions 0-7) */ GPIO_FN(VBUS_0), GPIO_FN(GPI0), @@ -2228,7 +2228,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(FSIAISLD_PU), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ PORTCR(2, 0xe6050002), /* PORT2CR */ @@ -2636,7 +2636,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, @@ -2744,7 +2744,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) #define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) -static struct pinmux_irq pinmux_irqs[] = { +static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16H(19), 9), PINMUX_IRQ(EXT_IRQ16L(1), 10), PINMUX_IRQ(EXT_IRQ16L(0), 11), @@ -2779,7 +2779,7 @@ static struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16L(9), 308), }; -struct sh_pfc_soc_info sh73a0_pinmux_info = { +const struct sh_pfc_soc_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 0b3078b6acdf..52e9f6be665f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -262,7 +262,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), @@ -763,7 +763,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* BSC */ GPIO_FN(D31), GPIO_FN(D30), @@ -957,7 +957,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(STATUS1), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, @@ -1141,7 +1141,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050140, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1217,7 +1217,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7720_pinmux_info = { +const struct sh_pfc_soc_info sh7720_pinmux_info = { .name = "sh7720_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 3a8d95fd3ed3..32034387477b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -296,7 +296,7 @@ enum { PINMUX_FUNCTION_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PTA */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), @@ -986,7 +986,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ GPIO_FN(SCIF0_TXD), GPIO_FN(SCIF0_RXD), @@ -1268,7 +1268,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(KEYOUT5_IN5), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, @@ -1664,7 +1664,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1760,7 +1760,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7722_pinmux_info = { +const struct sh_pfc_soc_info sh7722_pinmux_info = { .name = "sh7722_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index d8797ff4339b..07ad1d8d6c8b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -350,7 +350,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), @@ -1143,7 +1143,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ GPIO_FN(SCIF0_PTT_TXD), GPIO_FN(SCIF0_PTT_RXD), @@ -1515,7 +1515,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(IDEA0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { PTA7_FN, PTA7_OUT, 0, PTA7_IN, PTA6_FN, PTA6_OUT, 0, PTA6_IN, @@ -1789,7 +1789,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1885,7 +1885,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7723_pinmux_info = { +const struct sh_pfc_soc_info sh7723_pinmux_info = { .name = "sh7723_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 40f430be71a8..35e551609805 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -572,7 +572,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), @@ -1422,7 +1422,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* BSC */ GPIO_FN(D31), GPIO_FN(D30), @@ -1787,7 +1787,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(INTC_IRQ0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, @@ -2111,7 +2111,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -2207,7 +2207,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7724_pinmux_info = { +const struct sh_pfc_soc_info sh7724_pinmux_info = { .name = "sh7724_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index 99ea220269ff..2fd5b7d4cb94 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -592,7 +592,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), @@ -1373,7 +1373,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), @@ -1652,7 +1652,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { GP_0_31_FN, FN_IP2_2_0, GP_0_30_FN, FN_IP1_31_29, @@ -2421,7 +2421,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { /* GPIO 0 - 5*/ { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, @@ -2438,7 +2438,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7734_pinmux_info = { +const struct sh_pfc_soc_info sh7734_pinmux_info = { .name = "sh7734_pfc", .unlock_reg = 0xFFFC0000, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index e81ab0ecea8c..e074230e6243 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -526,7 +526,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), @@ -1374,7 +1374,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* PTA (mobule: LBSC, RGMII) */ GPIO_FN(BS), GPIO_FN(RDWR), @@ -1726,7 +1726,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(ON_DQ0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, @@ -2156,7 +2156,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffec0034, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -2264,7 +2264,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7757_pinmux_info = { +const struct sh_pfc_soc_info sh7757_pinmux_info = { .name = "sh7757_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 6049f594d37e..c176b794f240 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -355,7 +355,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PA GPIO */ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), @@ -849,7 +849,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* FN */ GPIO_FN(D63_AD31), GPIO_FN(D62_AD30), @@ -1018,7 +1018,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(IRQOUT), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, @@ -1218,7 +1218,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } @@ -1286,7 +1286,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7785_pinmux_info = { +const struct sh_pfc_soc_info sh7785_pinmux_info = { .name = "sh7785_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 526e78482d5b..8ae0e32844e9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -191,7 +191,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const pinmux_enum_t pinmux_data[] = { /* PA GPIO */ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), @@ -509,7 +509,7 @@ static struct sh_pfc_pin pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static struct pinmux_func pinmux_func_gpios[] = { +static const struct pinmux_func pinmux_func_gpios[] = { /* FN */ GPIO_FN(CDE), GPIO_FN(ETH_MAGIC), @@ -649,7 +649,7 @@ static struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(FSE), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, @@ -779,7 +779,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) { PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } @@ -819,7 +819,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7786_pinmux_info = { +const struct sh_pfc_soc_info sh7786_pinmux_info = { .name = "sh7786_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index 93d60cd4c437..6594c8c48747 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -147,7 +147,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t shx3_pinmux_data[] = { +static const pinmux_enum_t shx3_pinmux_data[] = { /* PA GPIO */ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), @@ -388,7 +388,7 @@ static struct sh_pfc_pin shx3_pinmux_pins[] = { #define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins) -static struct pinmux_func shx3_pinmux_func_gpios[] = { +static const struct pinmux_func shx3_pinmux_func_gpios[] = { /* FN */ GPIO_FN(D31), GPIO_FN(D30), @@ -454,7 +454,7 @@ static struct pinmux_func shx3_pinmux_func_gpios[] = { GPIO_FN(IRQOUT), }; -static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { +static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, @@ -530,7 +530,7 @@ static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg shx3_pinmux_data_regs[] = { +static const struct pinmux_data_reg shx3_pinmux_data_regs[] = { { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 0, 0, 0, 0, 0, 0, 0, 0, PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, @@ -566,7 +566,7 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info shx3_pinmux_info = { +const struct sh_pfc_soc_info shx3_pinmux_info = { .name = "shx3_pfc", .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 9978ad1818fd..b4960df6aa2d 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -141,7 +141,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset, struct sh_pfc *pfc = pmx->pfc; int idx = sh_pfc_get_pin_index(pfc, offset); struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; unsigned int mark = pin->enum_id; unsigned long flags; int ret = -EINVAL; @@ -324,7 +324,8 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) number++, nr_pins++) { struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins]; struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins]; - struct sh_pfc_pin *info = &pfc->info->pins[nr_pins]; + const struct sh_pfc_pin *info = + &pfc->info->pins[nr_pins]; pin->number = number; pin->name = info->name; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 19da3b7c57f1..b250dacaf8dd 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -84,8 +84,8 @@ struct pinmux_func { struct pinmux_cfg_reg { unsigned long reg, reg_width, field_width; - pinmux_enum_t *enum_ids; - unsigned long *var_field_width; + const pinmux_enum_t *enum_ids; + const unsigned long *var_field_width; }; #define PINMUX_CFG_REG(name, r, r_width, f_width) \ @@ -99,7 +99,7 @@ struct pinmux_cfg_reg { struct pinmux_data_reg { unsigned long reg, reg_width; - pinmux_enum_t *enum_ids; + const pinmux_enum_t *enum_ids; }; #define PINMUX_DATA_REG(name, r, r_width) \ @@ -121,14 +121,14 @@ struct pinmux_range { }; struct sh_pfc_soc_info { - char *name; + const char *name; struct pinmux_range input; struct pinmux_range input_pd; struct pinmux_range input_pu; struct pinmux_range output; struct pinmux_range function; - struct sh_pfc_pin *pins; + const struct sh_pfc_pin *pins; unsigned int nr_pins; const struct pinmux_range *ranges; unsigned int nr_ranges; @@ -137,16 +137,16 @@ struct sh_pfc_soc_info { const struct sh_pfc_function *functions; unsigned int nr_functions; - struct pinmux_func *func_gpios; + const struct pinmux_func *func_gpios; unsigned int nr_func_gpios; - struct pinmux_cfg_reg *cfg_regs; - struct pinmux_data_reg *data_regs; + const struct pinmux_cfg_reg *cfg_regs; + const struct pinmux_data_reg *data_regs; - pinmux_enum_t *gpio_data; + const pinmux_enum_t *gpio_data; unsigned int gpio_data_size; - struct pinmux_irq *gpio_irq; + const struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size; unsigned long unlock_reg; From b705c054255ae3264aa02d46347e9cfbcf26523a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 16:38:23 +0100 Subject: [PATCH 110/307] sh-pfc: Use proper error codes Return proper error codes instead of -1, and propagate the error codes. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 19 ++++++++++--------- drivers/pinctrl/sh-pfc/gpio.c | 13 ++++--------- drivers/pinctrl/sh-pfc/pinctrl.c | 24 +++++++++++------------- 3 files changed, 25 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 3a949465e88e..a04c497deccd 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -93,7 +93,7 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) offset += range->end - range->begin + 1; } - return -1; + return -EINVAL; } static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, @@ -233,7 +233,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, k++; } - return -1; + return -EINVAL; } static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, @@ -255,7 +255,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, } pr_err("cannot locate data/mark enum_id for mark %d\n", mark); - return -1; + return -EINVAL; } int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) @@ -264,6 +264,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) pinmux_enum_t enum_id; const struct pinmux_range *range; int in_range, pos, field, value; + int ret; switch (pinmux_type) { @@ -288,7 +289,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) break; default: - return -1; + return -EINVAL; } pos = 0; @@ -297,8 +298,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) value = 0; while (1) { pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); - if (pos <= 0) - return -1; + if (pos < 0) + return pos; if (!enum_id) break; @@ -341,9 +342,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) if (!in_range) continue; - if (sh_pfc_get_config_reg(pfc, enum_id, &cr, - &field, &value) != 0) - return -1; + ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); + if (ret < 0) + return ret; sh_pfc_write_config_reg(pfc, cr, field, value); } diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 480beae2ee67..e299f14bc50a 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -276,22 +276,17 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) struct sh_pfc *pfc = gpio_to_pfc(gc); unsigned int mark = pfc->info->func_gpios[offset].enum_id; unsigned long flags; - int ret = -EINVAL; + int ret; pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); if (mark == 0) - return ret; + return -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - - if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION)) - goto done; - - ret = 0; - -done: + ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION); spin_unlock_irqrestore(&pfc->lock, flags); + return ret; } diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index b4960df6aa2d..c15091096f65 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -114,18 +114,16 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; unsigned long flags; unsigned int i; - int ret = -EINVAL; + int ret = 0; spin_lock_irqsave(&pfc->lock, flags); for (i = 0; i < grp->nr_pins; ++i) { - if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION)) - goto done; + ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); + if (ret < 0) + break; } - ret = 0; - -done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; } @@ -144,7 +142,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset, const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; unsigned int mark = pin->enum_id; unsigned long flags; - int ret = -EINVAL; + int ret; spin_lock_irqsave(&pfc->lock, flags); @@ -156,17 +154,17 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset, case PINMUX_TYPE_INPUT_PULLDOWN: break; default: - goto err; + ret = -EINVAL; + goto done; } - if (sh_pfc_config_mux(pfc, mark, new_type) != 0) - goto err; + ret = sh_pfc_config_mux(pfc, mark, new_type); + if (ret < 0) + goto done; cfg->type = new_type; - ret = 0; - -err: +done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; From c58d9c1b26e3ab2933abc7d5444e945ddad44809 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 16:44:02 +0100 Subject: [PATCH 111/307] sh-pfc: Implement generic pinconf support The existing PFC pinconf implementation, tied to the PFC-specific pin types, isn't used by drivers or boards. Replace it with the generic pinconf types to implement bias (pull-up/down) setup. Other pin configuration options can be implemented later if needed. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/Kconfig | 1 + drivers/pinctrl/sh-pfc/pinctrl.c | 119 +++++++++++++++++++++++-------- drivers/pinctrl/sh-pfc/sh_pfc.h | 16 +++++ 3 files changed, 108 insertions(+), 28 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index c3340f54d2ad..af16f8f6ab6c 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -10,6 +10,7 @@ config PINCTRL_SH_PFC select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB select PINMUX select PINCONF + select GENERIC_PINCONF def_bool y help This enables pin control drivers for SH and SH Mobile platforms diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index c15091096f65..79fa170b4872 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -24,6 +24,8 @@ #include #include "core.h" +#include "../core.h" +#include "../pinconf.h" struct sh_pfc_pin_config { u32 type; @@ -230,57 +232,118 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = { .gpio_set_direction = sh_pfc_gpio_set_direction, }; +/* Check whether the requested parameter is supported for a pin. */ +static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, + enum pin_config_param param) +{ + int idx = sh_pfc_get_pin_index(pfc, _pin); + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + return true; + + case PIN_CONFIG_BIAS_PULL_UP: + return pin->configs & SH_PFC_PIN_CFG_PULL_UP; + + case PIN_CONFIG_BIAS_PULL_DOWN: + return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; + + default: + return false; + } +} + static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, unsigned long *config) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - int idx = sh_pfc_get_pin_index(pfc, _pin); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; + unsigned int bias; - *config = cfg->type; + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) + return -ENOTSUPP; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!pfc->info->ops || !pfc->info->ops->get_bias) + return -ENOTSUPP; + + spin_lock_irqsave(&pfc->lock, flags); + bias = pfc->info->ops->get_bias(pfc, _pin); + spin_unlock_irqrestore(&pfc->lock, flags); + + if (bias != param) + return -EINVAL; + + *config = 0; + break; + + default: + return -ENOTSUPP; + } return 0; } -static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, +static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, unsigned long config) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + enum pin_config_param param = pinconf_to_config_param(config); + unsigned long flags; - /* Validate the new type */ - if (config >= PINMUX_FLAG_TYPE) - return -EINVAL; + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) + return -ENOTSUPP; - return sh_pfc_reconfig_pin(pmx, pin, config); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + if (!pfc->info->ops || !pfc->info->ops->set_bias) + return -ENOTSUPP; + + spin_lock_irqsave(&pfc->lock, flags); + pfc->info->ops->set_bias(pfc, _pin, param); + spin_unlock_irqrestore(&pfc->lock, flags); + + break; + + default: + return -ENOTSUPP; + } + + return 0; } -static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin) +static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long config) { - const char *pinmux_type_str[] = { - [PINMUX_TYPE_NONE] = "none", - [PINMUX_TYPE_FUNCTION] = "function", - [PINMUX_TYPE_GPIO] = "gpio", - [PINMUX_TYPE_OUTPUT] = "output", - [PINMUX_TYPE_INPUT] = "input", - [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up", - [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down", - }; - unsigned long config; - int rc; + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins; + unsigned int num_pins; + unsigned int i; - rc = sh_pfc_pinconf_get(pctldev, pin, &config); - if (unlikely(rc != 0)) - return; + pins = pmx->pfc->info->groups[group].pins; + num_pins = pmx->pfc->info->groups[group].nr_pins; - seq_printf(s, " %s", pinmux_type_str[config]); + for (i = 0; i < num_pins; ++i) + sh_pfc_pinconf_set(pctldev, pins[i], config); + + return 0; } static const struct pinconf_ops sh_pfc_pinconf_ops = { - .pin_config_get = sh_pfc_pinconf_get, - .pin_config_set = sh_pfc_pinconf_set, - .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, + .is_generic = true, + .pin_config_get = sh_pfc_pinconf_get, + .pin_config_set = sh_pfc_pinconf_set, + .pin_config_group_set = sh_pfc_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, }; /* PFC ranges -> pinctrl pin descs */ diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index b250dacaf8dd..3b785fc428d5 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -31,9 +31,15 @@ enum { PINMUX_FLAG_TYPE, /* must be last */ }; +#define SH_PFC_PIN_CFG_INPUT (1 << 0) +#define SH_PFC_PIN_CFG_OUTPUT (1 << 1) +#define SH_PFC_PIN_CFG_PULL_UP (1 << 2) +#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) + struct sh_pfc_pin { const pinmux_enum_t enum_id; const char *name; + unsigned int configs; }; #define SH_PFC_PIN_GROUP(n) \ @@ -120,8 +126,18 @@ struct pinmux_range { pinmux_enum_t force; }; +struct sh_pfc; + +struct sh_pfc_soc_operations { + unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); + void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); +}; + struct sh_pfc_soc_info { const char *name; + const struct sh_pfc_soc_operations *ops; + struct pinmux_range input; struct pinmux_range input_pd; struct pinmux_range input_pu; From 0d00f00a1077ae89fb0ecbbba8da4c2c6bc93446 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 16:55:19 +0100 Subject: [PATCH 112/307] sh-pfc: Merge sh_pfc_reconfig_pin() into sh_pfc_gpio_set_direction() The sh_pfc_reconfig_pin() is only called from a single location. Merge it into its call site to make the code easier to follow. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 71 ++++++++++++++------------------ 1 file changed, 32 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 79fa170b4872..36f08f826a5e 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -135,43 +135,6 @@ static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, { } -static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset, - int new_type) -{ - struct sh_pfc *pfc = pmx->pfc; - int idx = sh_pfc_get_pin_index(pfc, offset); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - unsigned int mark = pin->enum_id; - unsigned long flags; - int ret; - - spin_lock_irqsave(&pfc->lock, flags); - - switch (cfg->type) { - case PINMUX_TYPE_GPIO: - case PINMUX_TYPE_OUTPUT: - case PINMUX_TYPE_INPUT: - case PINMUX_TYPE_INPUT_PULLUP: - case PINMUX_TYPE_INPUT_PULLDOWN: - break; - default: - ret = -EINVAL; - goto done; - } - - ret = sh_pfc_config_mux(pfc, mark, new_type); - if (ret < 0) - goto done; - - cfg->type = new_type; - -done: - spin_unlock_irqrestore(&pfc->lock, flags); - - return ret; -} - static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) @@ -216,9 +179,39 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, unsigned offset, bool input) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; + struct sh_pfc *pfc = pmx->pfc; + int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; + int idx = sh_pfc_get_pin_index(pfc, offset); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + unsigned int mark = pin->enum_id; + unsigned long flags; + int ret; - return sh_pfc_reconfig_pin(pmx, offset, type); + spin_lock_irqsave(&pfc->lock, flags); + + switch (cfg->type) { + case PINMUX_TYPE_GPIO: + case PINMUX_TYPE_OUTPUT: + case PINMUX_TYPE_INPUT: + case PINMUX_TYPE_INPUT_PULLUP: + case PINMUX_TYPE_INPUT_PULLDOWN: + break; + default: + ret = -EINVAL; + goto done; + } + + ret = sh_pfc_config_mux(pfc, mark, new_type); + if (ret < 0) + goto done; + + cfg->type = new_type; + +done: + spin_unlock_irqrestore(&pfc->lock, flags); + + return ret; } static const struct pinmux_ops sh_pfc_pinmux_ops = { From 9fddc4a589c6d1bd9c935d445b1a1d216b1457ab Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 17:25:29 +0100 Subject: [PATCH 113/307] sh-pfc: Clean up pin configuration type handling Set pin configuration type to - PINMUX_TYPE_NONE at initialization time and when disabling a function or freeing a GPIO - PINMUX_TYPE_FUNCTION when enabling a function - PINMUX_TYPE_INPUT or PINMUX_TYPE_OUTPUT when setting the GPIO direction Verify that the type is PINMUX_TYPE_NONE when enabling a function or requesting a GPIO and return -EBUSY if it isn't. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 74 ++++++++++++++++++++------------ 1 file changed, 46 insertions(+), 28 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 36f08f826a5e..82e4fb21853e 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -120,12 +120,23 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, spin_lock_irqsave(&pfc->lock, flags); + for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + if (cfg->type != PINMUX_TYPE_NONE) { + ret = -EBUSY; + goto done; + } + } + for (i = 0; i < grp->nr_pins; ++i) { ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); if (ret < 0) break; } +done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; } @@ -133,6 +144,22 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; + unsigned long flags; + unsigned int i; + + spin_lock_irqsave(&pfc->lock, flags); + + for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + cfg->type = PINMUX_TYPE_NONE; + } + + spin_unlock_irqrestore(&pfc->lock, flags); } static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, @@ -148,21 +175,17 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - switch (cfg->type) { - case PINMUX_TYPE_GPIO: - case PINMUX_TYPE_INPUT: - case PINMUX_TYPE_OUTPUT: - break; - case PINMUX_TYPE_FUNCTION: - default: - pr_err("Unsupported mux type (%d), bailing...\n", cfg->type); - ret = -ENOTSUPP; - goto err; + if (cfg->type != PINMUX_TYPE_NONE) { + pr_err("Pin %u is busy, can't configure it as GPIO.\n", offset); + ret = -EBUSY; + goto done; } + cfg->type = PINMUX_TYPE_GPIO; + ret = 0; -err: +done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; @@ -172,6 +195,15 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + int idx = sh_pfc_get_pin_index(pfc, offset); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + unsigned long flags; + + spin_lock_irqsave(&pfc->lock, flags); + cfg->type = PINMUX_TYPE_NONE; + spin_unlock_irqrestore(&pfc->lock, flags); } static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -182,27 +214,14 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, struct sh_pfc *pfc = pmx->pfc; int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; int idx = sh_pfc_get_pin_index(pfc, offset); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - unsigned int mark = pin->enum_id; + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; int ret; spin_lock_irqsave(&pfc->lock, flags); - switch (cfg->type) { - case PINMUX_TYPE_GPIO: - case PINMUX_TYPE_OUTPUT: - case PINMUX_TYPE_INPUT: - case PINMUX_TYPE_INPUT_PULLUP: - case PINMUX_TYPE_INPUT_PULLDOWN: - break; - default: - ret = -EINVAL; - goto done; - } - - ret = sh_pfc_config_mux(pfc, mark, new_type); + ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); if (ret < 0) goto done; @@ -210,7 +229,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, done: spin_unlock_irqrestore(&pfc->lock, flags); - return ret; } @@ -383,7 +401,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) pin->number = number; pin->name = info->name; - cfg->type = PINMUX_TYPE_GPIO; + cfg->type = PINMUX_TYPE_NONE; } } From 9a643c9a11259955ec6961f9a2509604c6df1cd9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 18:00:02 +0100 Subject: [PATCH 114/307] sh-pfc: Convert message printing from pr_* to dev_* Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 14 +++++++------- drivers/pinctrl/sh-pfc/gpio.c | 16 ++++++++++------ drivers/pinctrl/sh-pfc/pinctrl.c | 5 +++-- 3 files changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index a04c497deccd..feef89792568 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -10,7 +10,6 @@ */ #define DRV_NAME "sh-pfc" -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include #include @@ -173,9 +172,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); - pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " - "r_width = %ld, f_width = %ld\n", - crp->reg, value, field, crp->reg_width, crp->field_width); + dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, " + "r_width = %ld, f_width = %ld\n", + crp->reg, value, field, crp->reg_width, crp->field_width); mask = ~(mask << pos); value = value << pos; @@ -254,7 +253,8 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, } } - pr_err("cannot locate data/mark enum_id for mark %d\n", mark); + dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", + mark); return -EINVAL; } @@ -396,13 +396,13 @@ static int sh_pfc_probe(struct platform_device *pdev) * PFC state as it is, given that there are already * extant users of it that have succeeded by this point. */ - pr_notice("failed to init GPIO chip, ignoring...\n"); + dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); } #endif platform_set_drvdata(pdev, pfc); - pr_info("%s support registered\n", info->name); + dev_info(pfc->dev, "%s support registered\n", info->name); return 0; } diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index e299f14bc50a..d7acb06d888c 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -9,8 +9,6 @@ * for more details. */ -#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt - #include #include #include @@ -273,12 +271,18 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) static int gpio_function_request(struct gpio_chip *gc, unsigned offset) { + static bool __print_once; struct sh_pfc *pfc = gpio_to_pfc(gc); unsigned int mark = pfc->info->func_gpios[offset].enum_id; unsigned long flags; int ret; - pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); + if (!__print_once) { + dev_notice(pfc->dev, + "Use of GPIO API for function requests is deprecated." + " Convert to pinctrl\n"); + __print_once = true; + } if (mark == 0) return -EINVAL; @@ -334,9 +338,9 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *)) if (unlikely(ret < 0)) return ERR_PTR(ret); - pr_info("%s handling gpio %u -> %u\n", - chip->gpio_chip.label, chip->gpio_chip.base, - chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); + dev_info(pfc->dev, "%s handling gpio %u -> %u\n", + chip->gpio_chip.label, chip->gpio_chip.base, + chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); return chip; } diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 82e4fb21853e..52179bbcf6b4 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -9,7 +9,6 @@ */ #define DRV_NAME "sh-pfc" -#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt #include #include @@ -176,7 +175,9 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); if (cfg->type != PINMUX_TYPE_NONE) { - pr_err("Pin %u is busy, can't configure it as GPIO.\n", offset); + dev_err(pfc->dev, + "Pin %u is busy, can't configure it as GPIO.\n", + offset); ret = -EBUSY; goto done; } From 6dc9b4550a74cad7daed0be192030983dad44755 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:18:30 +0100 Subject: [PATCH 115/307] sh-pfc: Return an error if a pin doesn't support the requested direction When setting a pin direction verify that the requested direction is supported, and return an error if it isn't. This requires pin configuration information to be supplied by SoC data. The check is a no-op if the information is not supplied. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pinctrl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 52179bbcf6b4..aef268bc17ba 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -218,8 +218,18 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; + unsigned int dir; int ret; + /* Check if the requested direction is supported by the pin. Not all SoC + * provide pin config data, so perform the check conditionally. + */ + if (pin->configs) { + dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; + if (!(pin->configs & dir)) + return -EINVAL; + } + spin_lock_irqsave(&pfc->lock, flags); ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); From 55f11f0ec1bad183440ab4717f6e1a142c062613 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 23 Jan 2013 17:37:45 +0100 Subject: [PATCH 116/307] sh-pfc: sh7372: Add SDHCI and MMCIF pin groups and functions Add pin groups for all three SDHI interfaces and two alternative pin groups for the MMCIF interface on the sh7372 SoC. Signed-off-by: Guennadi Liakhovetski Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 206 ++++++++++++++++++++++++++++ 1 file changed, 206 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 6b5634454956..cef4d6a598dd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -933,6 +933,207 @@ static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ + 84, +}; +static const unsigned int mmc0_data1_0_mux[] = { + MMCD0_0_MARK, +}; +static const unsigned int mmc0_data4_0_pins[] = { + /* D[0:3] */ + 84, 85, 86, 87, +}; +static const unsigned int mmc0_data4_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, +}; +static const unsigned int mmc0_data8_0_pins[] = { + /* D[0:7] */ + 84, 85, 86, 87, 88, 89, 90, 91, +}; +static const unsigned int mmc0_data8_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, +}; +static const unsigned int mmc0_ctrl_0_pins[] = { + /* CMD, CLK */ + 92, 99, +}; +static const unsigned int mmc0_ctrl_0_mux[] = { + MMCCMD0_MARK, MMCCLK0_MARK, +}; + +static const unsigned int mmc0_data1_1_pins[] = { + /* D[0] */ + 54, +}; +static const unsigned int mmc0_data1_1_mux[] = { + MMCD1_0_MARK, +}; +static const unsigned int mmc0_data4_1_pins[] = { + /* D[0:3] */ + 54, 55, 56, 57, +}; +static const unsigned int mmc0_data4_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, +}; +static const unsigned int mmc0_data8_1_pins[] = { + /* D[0:7] */ + 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int mmc0_data8_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, +}; +static const unsigned int mmc0_ctrl_1_pins[] = { + /* CMD, CLK */ + 67, 66, +}; +static const unsigned int mmc0_ctrl_1_mux[] = { + MMCCMD1_MARK, MMCCLK1_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 173, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHID0_0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 173, 174, 175, 176, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + 177, 171, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHICMD0_MARK, SDHICLK0_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 172, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHICD0_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 178, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHIWP0_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 180, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHID1_0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 180, 181, 182, 183, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + 184, 179, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHICMD1_MARK, SDHICLK1_MARK, +}; + +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 186, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHID2_0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 186, 187, 188, 189, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + 190, 185, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHICMD2_MARK, SDHICLK2_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), + SH_PFC_PIN_GROUP(mmc0_ctrl_0), + SH_PFC_PIN_GROUP(mmc0_data1_1), + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), +}; + +static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", + "mmc0_data8_0", + "mmc0_ctrl_0", + "mmc0_data1_1", + "mmc0_data4_1", + "mmc0_data8_1", + "mmc0_ctrl_1", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), +}; + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) static const struct pinmux_func pinmux_func_gpios[] = { @@ -1644,6 +1845,11 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), From b8238993ed2ba222a456bcdf53370ff7fe1fe501 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 01:31:23 +0100 Subject: [PATCH 117/307] sh-pfc: sh73a0: Add bias (pull-up/down) pinconf support Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 351 +++++++++++++++++++++++++++- 1 file changed, 350 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 3200fc2f34b1..f31adfc687fa 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -18,10 +18,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include +#include + #include #include +#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ @@ -1539,8 +1543,300 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), }; +#define SH73A0_PIN(pin, cfgs) \ + { \ + .name = __stringify(PORT##pin), \ + .enum_id = PORT##pin##_DATA, \ + .configs = cfgs, \ + } + +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD) +#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU) +#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD) +#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO) +#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD) +#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU) +#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD) +#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O) + static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), + /* Table 25-1 (I/O and Pull U/D) */ + SH73A0_PIN_I_PD(0), + SH73A0_PIN_I_PU(1), + SH73A0_PIN_I_PU(2), + SH73A0_PIN_I_PU(3), + SH73A0_PIN_I_PU(4), + SH73A0_PIN_I_PU(5), + SH73A0_PIN_I_PU(6), + SH73A0_PIN_I_PU(7), + SH73A0_PIN_I_PU(8), + SH73A0_PIN_I_PD(9), + SH73A0_PIN_I_PD(10), + SH73A0_PIN_I_PU_PD(11), + SH73A0_PIN_IO_PU_PD(12), + SH73A0_PIN_IO_PU_PD(13), + SH73A0_PIN_IO_PU_PD(14), + SH73A0_PIN_IO_PU_PD(15), + SH73A0_PIN_IO_PD(16), + SH73A0_PIN_IO_PD(17), + SH73A0_PIN_IO_PU(18), + SH73A0_PIN_IO_PU(19), + SH73A0_PIN_O(20), + SH73A0_PIN_O(21), + SH73A0_PIN_O(22), + SH73A0_PIN_O(23), + SH73A0_PIN_O(24), + SH73A0_PIN_I_PD(25), + SH73A0_PIN_I_PD(26), + SH73A0_PIN_IO_PU(27), + SH73A0_PIN_IO_PU(28), + SH73A0_PIN_IO_PD(29), + SH73A0_PIN_IO_PD(30), + SH73A0_PIN_IO_PU(31), + SH73A0_PIN_IO_PD(32), + SH73A0_PIN_I_PU_PD(33), + SH73A0_PIN_IO_PD(34), + SH73A0_PIN_I_PU_PD(35), + SH73A0_PIN_IO_PD(36), + SH73A0_PIN_IO(37), + SH73A0_PIN_O(38), + SH73A0_PIN_I_PU(39), + SH73A0_PIN_I_PU_PD(40), + SH73A0_PIN_O(41), + SH73A0_PIN_IO_PD(42), + SH73A0_PIN_IO_PU_PD(43), + SH73A0_PIN_IO_PU_PD(44), + SH73A0_PIN_IO_PD(45), + SH73A0_PIN_IO_PD(46), + SH73A0_PIN_IO_PD(47), + SH73A0_PIN_I_PD(48), + SH73A0_PIN_IO_PU_PD(49), + SH73A0_PIN_IO_PD(50), + SH73A0_PIN_IO_PD(51), + SH73A0_PIN_O(52), + SH73A0_PIN_IO_PU_PD(53), + SH73A0_PIN_IO_PU_PD(54), + SH73A0_PIN_IO_PD(55), + SH73A0_PIN_I_PU_PD(56), + SH73A0_PIN_IO(57), + SH73A0_PIN_IO(58), + SH73A0_PIN_IO(59), + SH73A0_PIN_IO(60), + SH73A0_PIN_IO(61), + SH73A0_PIN_IO_PD(62), + SH73A0_PIN_IO_PD(63), + SH73A0_PIN_IO_PU_PD(64), + SH73A0_PIN_IO_PD(65), + SH73A0_PIN_IO_PU_PD(66), + SH73A0_PIN_IO_PU_PD(67), + SH73A0_PIN_IO_PU_PD(68), + SH73A0_PIN_IO_PU_PD(69), + SH73A0_PIN_IO_PU_PD(70), + SH73A0_PIN_IO_PU_PD(71), + SH73A0_PIN_IO_PU_PD(72), + SH73A0_PIN_I_PU_PD(73), + SH73A0_PIN_IO_PU(74), + SH73A0_PIN_IO_PU(75), + SH73A0_PIN_IO_PU(76), + SH73A0_PIN_IO_PU(77), + SH73A0_PIN_IO_PU(78), + SH73A0_PIN_IO_PU(79), + SH73A0_PIN_IO_PU(80), + SH73A0_PIN_IO_PU(81), + SH73A0_PIN_IO_PU(82), + SH73A0_PIN_IO_PU(83), + SH73A0_PIN_IO_PU(84), + SH73A0_PIN_IO_PU(85), + SH73A0_PIN_IO_PU(86), + SH73A0_PIN_IO_PU(87), + SH73A0_PIN_IO_PU(88), + SH73A0_PIN_IO_PU(89), + SH73A0_PIN_O(90), + SH73A0_PIN_IO_PU(91), + SH73A0_PIN_O(92), + SH73A0_PIN_IO_PU(93), + SH73A0_PIN_O(94), + SH73A0_PIN_I_PU_PD(95), + SH73A0_PIN_IO(96), + SH73A0_PIN_IO(97), + SH73A0_PIN_IO(98), + SH73A0_PIN_I_PU(99), + SH73A0_PIN_O(100), + SH73A0_PIN_O(101), + SH73A0_PIN_I_PU(102), + SH73A0_PIN_IO_PD(103), + SH73A0_PIN_I_PU_PD(104), + SH73A0_PIN_I_PD(105), + SH73A0_PIN_I_PD(106), + SH73A0_PIN_I_PU_PD(107), + SH73A0_PIN_I_PU_PD(108), + SH73A0_PIN_IO_PD(109), + SH73A0_PIN_IO_PD(110), + SH73A0_PIN_IO_PU_PD(111), + SH73A0_PIN_IO_PU_PD(112), + SH73A0_PIN_IO_PU_PD(113), + SH73A0_PIN_IO_PD(114), + SH73A0_PIN_IO_PU(115), + SH73A0_PIN_IO_PU(116), + SH73A0_PIN_IO_PU_PD(117), + SH73A0_PIN_IO_PU_PD(118), + SH73A0_PIN_IO_PD(128), + SH73A0_PIN_IO_PD(129), + SH73A0_PIN_IO_PU_PD(130), + SH73A0_PIN_IO_PD(131), + SH73A0_PIN_IO_PD(132), + SH73A0_PIN_IO_PD(133), + SH73A0_PIN_IO_PU_PD(134), + SH73A0_PIN_IO_PU_PD(135), + SH73A0_PIN_IO_PU_PD(136), + SH73A0_PIN_IO_PU_PD(137), + SH73A0_PIN_IO_PD(138), + SH73A0_PIN_IO_PD(139), + SH73A0_PIN_IO_PD(140), + SH73A0_PIN_IO_PD(141), + SH73A0_PIN_IO_PD(142), + SH73A0_PIN_IO_PD(143), + SH73A0_PIN_IO_PU_PD(144), + SH73A0_PIN_IO_PD(145), + SH73A0_PIN_IO_PU_PD(146), + SH73A0_PIN_IO_PU_PD(147), + SH73A0_PIN_IO_PU_PD(148), + SH73A0_PIN_IO_PU_PD(149), + SH73A0_PIN_I_PU_PD(150), + SH73A0_PIN_IO_PU_PD(151), + SH73A0_PIN_IO_PU_PD(152), + SH73A0_PIN_IO_PD(153), + SH73A0_PIN_IO_PD(154), + SH73A0_PIN_I_PU_PD(155), + SH73A0_PIN_IO_PU_PD(156), + SH73A0_PIN_I_PD(157), + SH73A0_PIN_IO_PD(158), + SH73A0_PIN_IO_PU_PD(159), + SH73A0_PIN_IO_PU_PD(160), + SH73A0_PIN_I_PU_PD(161), + SH73A0_PIN_I_PU_PD(162), + SH73A0_PIN_IO_PU_PD(163), + SH73A0_PIN_I_PU_PD(164), + SH73A0_PIN_IO_PD(192), + SH73A0_PIN_IO_PU_PD(193), + SH73A0_PIN_IO_PD(194), + SH73A0_PIN_IO_PU_PD(195), + SH73A0_PIN_IO_PD(196), + SH73A0_PIN_IO_PD(197), + SH73A0_PIN_IO_PD(198), + SH73A0_PIN_IO_PD(199), + SH73A0_PIN_IO_PU_PD(200), + SH73A0_PIN_IO_PU_PD(201), + SH73A0_PIN_IO_PU_PD(202), + SH73A0_PIN_IO_PU_PD(203), + SH73A0_PIN_IO_PU_PD(204), + SH73A0_PIN_IO_PU_PD(205), + SH73A0_PIN_IO_PU_PD(206), + SH73A0_PIN_IO_PD(207), + SH73A0_PIN_IO_PD(208), + SH73A0_PIN_IO_PD(209), + SH73A0_PIN_IO_PD(210), + SH73A0_PIN_IO_PD(211), + SH73A0_PIN_IO_PD(212), + SH73A0_PIN_IO_PD(213), + SH73A0_PIN_IO_PU_PD(214), + SH73A0_PIN_IO_PU_PD(215), + SH73A0_PIN_IO_PD(216), + SH73A0_PIN_IO_PD(217), + SH73A0_PIN_O(218), + SH73A0_PIN_IO_PD(219), + SH73A0_PIN_IO_PD(220), + SH73A0_PIN_IO_PU_PD(221), + SH73A0_PIN_IO_PU_PD(222), + SH73A0_PIN_I_PU_PD(223), + SH73A0_PIN_I_PU_PD(224), + SH73A0_PIN_IO_PU_PD(225), + SH73A0_PIN_O(226), + SH73A0_PIN_IO_PU_PD(227), + SH73A0_PIN_I_PU_PD(228), + SH73A0_PIN_I_PD(229), + SH73A0_PIN_IO(230), + SH73A0_PIN_IO_PU_PD(231), + SH73A0_PIN_IO_PU_PD(232), + SH73A0_PIN_I_PU_PD(233), + SH73A0_PIN_IO_PU_PD(234), + SH73A0_PIN_IO_PU_PD(235), + SH73A0_PIN_IO_PU_PD(236), + SH73A0_PIN_IO_PD(237), + SH73A0_PIN_IO_PU_PD(238), + SH73A0_PIN_IO_PU_PD(239), + SH73A0_PIN_IO_PU_PD(240), + SH73A0_PIN_O(241), + SH73A0_PIN_I_PD(242), + SH73A0_PIN_IO_PU_PD(243), + SH73A0_PIN_IO_PU_PD(244), + SH73A0_PIN_IO_PU_PD(245), + SH73A0_PIN_IO_PU_PD(246), + SH73A0_PIN_IO_PU_PD(247), + SH73A0_PIN_IO_PU_PD(248), + SH73A0_PIN_IO_PU_PD(249), + SH73A0_PIN_IO_PU_PD(250), + SH73A0_PIN_IO_PU_PD(251), + SH73A0_PIN_IO_PU_PD(252), + SH73A0_PIN_IO_PU_PD(253), + SH73A0_PIN_IO_PU_PD(254), + SH73A0_PIN_IO_PU_PD(255), + SH73A0_PIN_IO_PU_PD(256), + SH73A0_PIN_IO_PU_PD(257), + SH73A0_PIN_IO_PU_PD(258), + SH73A0_PIN_IO_PU_PD(259), + SH73A0_PIN_IO_PU_PD(260), + SH73A0_PIN_IO_PU_PD(261), + SH73A0_PIN_IO_PU_PD(262), + SH73A0_PIN_IO_PU_PD(263), + SH73A0_PIN_IO_PU_PD(264), + SH73A0_PIN_IO_PU_PD(265), + SH73A0_PIN_IO_PU_PD(266), + SH73A0_PIN_IO_PU_PD(267), + SH73A0_PIN_IO_PU_PD(268), + SH73A0_PIN_IO_PU_PD(269), + SH73A0_PIN_IO_PU_PD(270), + SH73A0_PIN_IO_PU_PD(271), + SH73A0_PIN_IO_PU_PD(272), + SH73A0_PIN_IO_PU_PD(273), + SH73A0_PIN_IO_PU_PD(274), + SH73A0_PIN_IO_PU_PD(275), + SH73A0_PIN_IO_PU_PD(276), + SH73A0_PIN_IO_PU_PD(277), + SH73A0_PIN_IO_PU_PD(278), + SH73A0_PIN_IO_PU_PD(279), + SH73A0_PIN_IO_PU_PD(280), + SH73A0_PIN_O(281), + SH73A0_PIN_O(282), + SH73A0_PIN_I_PU(288), + SH73A0_PIN_IO_PU_PD(289), + SH73A0_PIN_IO_PU_PD(290), + SH73A0_PIN_IO_PU_PD(291), + SH73A0_PIN_IO_PU_PD(292), + SH73A0_PIN_IO_PU_PD(293), + SH73A0_PIN_IO_PU_PD(294), + SH73A0_PIN_IO_PU_PD(295), + SH73A0_PIN_IO_PU_PD(296), + SH73A0_PIN_IO_PU_PD(297), + SH73A0_PIN_IO_PU_PD(298), + SH73A0_PIN_IO_PU_PD(299), + SH73A0_PIN_IO_PU_PD(300), + SH73A0_PIN_IO_PU_PD(301), + SH73A0_PIN_IO_PU_PD(302), + SH73A0_PIN_IO_PU_PD(303), + SH73A0_PIN_IO_PU_PD(304), + SH73A0_PIN_IO_PU_PD(305), + SH73A0_PIN_O(306), + SH73A0_PIN_O(307), + SH73A0_PIN_I_PU(308), + SH73A0_PIN_O(309), }; static const struct pinmux_range pinmux_ranges[] = { @@ -2779,8 +3075,61 @@ static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16L(9), 308), }; +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +static const unsigned int sh73a0_portcr_offsets[] = { + 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000, + 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, +}; + +static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = pfc->window->virt + + sh73a0_portcr_offsets[pin >> 5] + pin; + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = pfc->window->virt + + sh73a0_portcr_offsets[pin >> 5] + pin; + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { + .get_bias = sh73a0_pinmux_get_bias, + .set_bias = sh73a0_pinmux_set_bias, +}; + const struct sh_pfc_soc_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", + .ops = &sh73a0_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, From df68a28d1765d9409262136b1fb098f44aa32642 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 118/307] sh-pfc: sh73a0: Add LCD and LCD2 pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 254 ++++++++++++++++++++++++++++ 1 file changed, 254 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index f31adfc687fa..c8b2604eb8f6 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1846,6 +1846,255 @@ static const struct pinmux_range pinmux_ranges[] = { {.begin = 288, .end = 309,}, }; +/* - LCD -------------------------------------------------------------------- */ +static const unsigned int lcd_data8_pins[] = { + /* D[0:7] */ + 192, 193, 194, 195, 196, 197, 198, 199, +}; +static const unsigned int lcd_data8_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, +}; +static const unsigned int lcd_data9_pins[] = { + /* D[0:8] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, +}; +static const unsigned int lcd_data9_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, +}; +static const unsigned int lcd_data12_pins[] = { + /* D[0:11] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, +}; +static const unsigned int lcd_data12_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, +}; +static const unsigned int lcd_data16_pins[] = { + /* D[0:15] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, +}; +static const unsigned int lcd_data16_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, +}; +static const unsigned int lcd_data18_pins[] = { + /* D[0:17] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, +}; +static const unsigned int lcd_data18_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, +}; +static const unsigned int lcd_data24_pins[] = { + /* D[0:23] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215 +}; +static const unsigned int lcd_data24_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, + LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, +}; +static const unsigned int lcd_display_pins[] = { + /* DON */ + 222, +}; +static const unsigned int lcd_display_mux[] = { + LCDDON_MARK, +}; +static const unsigned int lcd_lclk_pins[] = { + /* LCLK */ + 221, +}; +static const unsigned int lcd_lclk_mux[] = { + LCDLCLK_MARK, +}; +static const unsigned int lcd_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 220, 218, 216, 219, +}; +static const unsigned int lcd_sync_mux[] = { + LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, +}; +static const unsigned int lcd_sys_pins[] = { + /* CS, WR, RD, RS */ + 218, 216, 217, 219, +}; +static const unsigned int lcd_sys_mux[] = { + LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK, +}; +/* - LCD2 ------------------------------------------------------------------- */ +static const unsigned int lcd2_data8_pins[] = { + /* D[0:7] */ + 128, 129, 142, 143, 144, 145, 138, 139, +}; +static const unsigned int lcd2_data8_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, +}; +static const unsigned int lcd2_data9_pins[] = { + /* D[0:8] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, +}; +static const unsigned int lcd2_data9_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, +}; +static const unsigned int lcd2_data12_pins[] = { + /* D[0:12] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, +}; +static const unsigned int lcd2_data12_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, +}; +static const unsigned int lcd2_data16_pins[] = { + /* D[0:15] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, 132, 133, 134, 135, +}; +static const unsigned int lcd2_data16_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, + LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, +}; +static const unsigned int lcd2_data18_pins[] = { + /* D[0:17] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, 132, 133, 134, 135, + 136, 137, +}; +static const unsigned int lcd2_data18_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, + LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, + LCD2D16_MARK, LCD2D17_MARK, +}; +static const unsigned int lcd2_data24_pins[] = { + /* D[0:23] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, 132, 133, 134, 135, + 136, 137, 146, 147, 234, 235, 238, 239 +}; +static const unsigned int lcd2_data24_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, + LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, + LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK, + LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK, +}; +static const unsigned int lcd2_sync_0_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 128, 129, 146, 145, +}; +static const unsigned int lcd2_sync_0_mux[] = { + PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK, + LCD2DCK_MARK, PORT145_LCD2DISP_MARK, +}; +static const unsigned int lcd2_sync_1_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 222, 221, 219, 217, +}; +static const unsigned int lcd2_sync_1_mux[] = { + PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK, + LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK, +}; +static const unsigned int lcd2_sys_0_pins[] = { + /* CS, WR, RD, RS */ + 129, 146, 147, 145, +}; +static const unsigned int lcd2_sys_0_mux[] = { + PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK, + LCD2RD__MARK, PORT145_LCD2RS_MARK, +}; +static const unsigned int lcd2_sys_1_pins[] = { + /* CS, WR, RD, RS */ + 221, 219, 147, 217, +}; +static const unsigned int lcd2_sys_1_mux[] = { + PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK, + LCD2RD__MARK, PORT217_LCD2RS_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(lcd_data8), + SH_PFC_PIN_GROUP(lcd_data9), + SH_PFC_PIN_GROUP(lcd_data12), + SH_PFC_PIN_GROUP(lcd_data16), + SH_PFC_PIN_GROUP(lcd_data18), + SH_PFC_PIN_GROUP(lcd_data24), + SH_PFC_PIN_GROUP(lcd_display), + SH_PFC_PIN_GROUP(lcd_lclk), + SH_PFC_PIN_GROUP(lcd_sync), + SH_PFC_PIN_GROUP(lcd_sys), + SH_PFC_PIN_GROUP(lcd2_data8), + SH_PFC_PIN_GROUP(lcd2_data9), + SH_PFC_PIN_GROUP(lcd2_data12), + SH_PFC_PIN_GROUP(lcd2_data16), + SH_PFC_PIN_GROUP(lcd2_data18), + SH_PFC_PIN_GROUP(lcd2_data24), + SH_PFC_PIN_GROUP(lcd2_sync_0), + SH_PFC_PIN_GROUP(lcd2_sync_1), + SH_PFC_PIN_GROUP(lcd2_sys_0), + SH_PFC_PIN_GROUP(lcd2_sys_1), +}; + +static const char * const lcd_groups[] = { + "lcd_data8", + "lcd_data9", + "lcd_data12", + "lcd_data16", + "lcd_data18", + "lcd_data24", + "lcd_display", + "lcd_lclk", + "lcd_sync", + "lcd_sys", +}; + +static const char * const lcd2_groups[] = { + "lcd2_data8", + "lcd2_data9", + "lcd2_data12", + "lcd2_data16", + "lcd2_data18", + "lcd2_data24", + "lcd2_sync_0", + "lcd2_sync_1", + "lcd2_sys_0", + "lcd2_sys_1", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(lcd), + SH_PFC_FUNCTION(lcd2), +}; + #define PINMUX_FN_BASE GPIO_FN_VBUS_0 static const struct pinmux_func pinmux_func_gpios[] = { @@ -3140,6 +3389,11 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { .nr_pins = ARRAY_SIZE(pinmux_pins), .ranges = pinmux_ranges, .nr_ranges = ARRAY_SIZE(pinmux_ranges), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), From 64d87acb278fe90dbe5c69d7b1242eaf670ccc46 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 119/307] sh-pfc: sh73a0: Add SCIFA and SCIFB pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 351 ++++++++++++++++++++++++++++ 1 file changed, 351 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index c8b2604eb8f6..4b0a34958fdb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2040,6 +2040,253 @@ static const unsigned int lcd2_sys_1_mux[] = { PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK, LCD2RD__MARK, PORT217_LCD2RS_MARK, }; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 43, 17, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 16, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 42, 44, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS__MARK, SCIFA0_CTS__MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 228, 225, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 226, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 227, 229, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS__MARK, SCIFA1_CTS__MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_0_pins[] = { + /* RXD, TXD */ + 155, 154, +}; +static const unsigned int scifa2_data_0_mux[] = { + SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, +}; +static const unsigned int scifa2_clk_0_pins[] = { + /* SCK */ + 158, +}; +static const unsigned int scifa2_clk_0_mux[] = { + SCIFA2_SCK1_MARK, +}; +static const unsigned int scifa2_ctrl_0_pins[] = { + /* RTS, CTS */ + 156, 157, +}; +static const unsigned int scifa2_ctrl_0_mux[] = { + SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK, +}; +static const unsigned int scifa2_data_1_pins[] = { + /* RXD, TXD */ + 233, 230, +}; +static const unsigned int scifa2_data_1_mux[] = { + SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK, +}; +static const unsigned int scifa2_clk_1_pins[] = { + /* SCK */ + 232, +}; +static const unsigned int scifa2_clk_1_mux[] = { + SCIFA2_SCK2_MARK, +}; +static const unsigned int scifa2_ctrl_1_pins[] = { + /* RTS, CTS */ + 234, 231, +}; +static const unsigned int scifa2_ctrl_1_mux[] = { + SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + 108, 110, +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_ctrl_pins[] = { + /* RTS, CTS */ + 109, 107, +}; +static const unsigned int scifa3_ctrl_mux[] = { + SCIFA3_RTS__MARK, SCIFA3_CTS__MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + 33, 32, +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +static const unsigned int scifa4_ctrl_pins[] = { + /* RTS, CTS */ + 34, 35, +}; +static const unsigned int scifa4_ctrl_mux[] = { + SCIFA4_RTS__MARK, SCIFA4_CTS__MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_0_pins[] = { + /* RXD, TXD */ + 246, 247, +}; +static const unsigned int scifa5_data_0_mux[] = { + PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_clk_0_pins[] = { + /* SCK */ + 248, +}; +static const unsigned int scifa5_clk_0_mux[] = { + PORT248_SCIFA5_SCK_MARK, +}; +static const unsigned int scifa5_ctrl_0_pins[] = { + /* RTS, CTS */ + 245, 244, +}; +static const unsigned int scifa5_ctrl_0_mux[] = { + PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK, +}; +static const unsigned int scifa5_data_1_pins[] = { + /* RXD, TXD */ + 195, 196, +}; +static const unsigned int scifa5_data_1_mux[] = { + PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_clk_1_pins[] = { + /* SCK */ + 197, +}; +static const unsigned int scifa5_clk_1_mux[] = { + PORT197_SCIFA5_SCK_MARK, +}; +static const unsigned int scifa5_ctrl_1_pins[] = { + /* RTS, CTS */ + 194, 193, +}; +static const unsigned int scifa5_ctrl_1_mux[] = { + PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK, +}; +static const unsigned int scifa5_data_2_pins[] = { + /* RXD, TXD */ + 162, 160, +}; +static const unsigned int scifa5_data_2_mux[] = { + PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_clk_2_pins[] = { + /* SCK */ + 159, +}; +static const unsigned int scifa5_clk_2_mux[] = { + PORT159_SCIFA5_SCK_MARK, +}; +static const unsigned int scifa5_ctrl_2_pins[] = { + /* RTS, CTS */ + 163, 161, +}; +static const unsigned int scifa5_ctrl_2_mux[] = { + PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK, +}; +/* - SCIFA6 ----------------------------------------------------------------- */ +static const unsigned int scifa6_pins[] = { + /* TXD */ + 240, +}; +static const unsigned int scifa6_mux[] = { + SCIFA6_TXD_MARK, +}; +/* - SCIFA7 ----------------------------------------------------------------- */ +static const unsigned int scifa7_data_pins[] = { + /* RXD, TXD */ + 12, 18, +}; +static const unsigned int scifa7_data_mux[] = { + SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, +}; +static const unsigned int scifa7_ctrl_pins[] = { + /* RTS, CTS */ + 19, 13, +}; +static const unsigned int scifa7_ctrl_mux[] = { + SCIFA7_RTS__MARK, SCIFA7_CTS__MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_0_pins[] = { + /* RXD, TXD */ + 162, 160, +}; +static const unsigned int scifb_data_0_mux[] = { + PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK, +}; +static const unsigned int scifb_clk_0_pins[] = { + /* SCK */ + 159, +}; +static const unsigned int scifb_clk_0_mux[] = { + PORT159_SCIFB_SCK_MARK, +}; +static const unsigned int scifb_ctrl_0_pins[] = { + /* RTS, CTS */ + 163, 161, +}; +static const unsigned int scifb_ctrl_0_mux[] = { + PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK, +}; +static const unsigned int scifb_data_1_pins[] = { + /* RXD, TXD */ + 246, 247, +}; +static const unsigned int scifb_data_1_mux[] = { + PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK, +}; +static const unsigned int scifb_clk_1_pins[] = { + /* SCK */ + 248, +}; +static const unsigned int scifb_clk_1_mux[] = { + PORT248_SCIFB_SCK_MARK, +}; +static const unsigned int scifb_ctrl_1_pins[] = { + /* RTS, CTS */ + 245, 244, +}; +static const unsigned int scifb_ctrl_1_mux[] = { + PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lcd_data8), @@ -2062,6 +2309,40 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lcd2_sync_1), SH_PFC_PIN_GROUP(lcd2_sys_0), SH_PFC_PIN_GROUP(lcd2_sys_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_0), + SH_PFC_PIN_GROUP(scifa2_clk_0), + SH_PFC_PIN_GROUP(scifa2_ctrl_0), + SH_PFC_PIN_GROUP(scifa2_data_1), + SH_PFC_PIN_GROUP(scifa2_clk_1), + SH_PFC_PIN_GROUP(scifa2_ctrl_1), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_ctrl), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa4_ctrl), + SH_PFC_PIN_GROUP(scifa5_data_0), + SH_PFC_PIN_GROUP(scifa5_clk_0), + SH_PFC_PIN_GROUP(scifa5_ctrl_0), + SH_PFC_PIN_GROUP(scifa5_data_1), + SH_PFC_PIN_GROUP(scifa5_clk_1), + SH_PFC_PIN_GROUP(scifa5_ctrl_1), + SH_PFC_PIN_GROUP(scifa5_data_2), + SH_PFC_PIN_GROUP(scifa5_clk_2), + SH_PFC_PIN_GROUP(scifa5_ctrl_2), + SH_PFC_PIN_GROUP(scifa6), + SH_PFC_PIN_GROUP(scifa7_data), + SH_PFC_PIN_GROUP(scifa7_ctrl), + SH_PFC_PIN_GROUP(scifb_data_0), + SH_PFC_PIN_GROUP(scifb_clk_0), + SH_PFC_PIN_GROUP(scifb_ctrl_0), + SH_PFC_PIN_GROUP(scifb_data_1), + SH_PFC_PIN_GROUP(scifb_clk_1), + SH_PFC_PIN_GROUP(scifb_ctrl_1), }; static const char * const lcd_groups[] = { @@ -2090,9 +2371,79 @@ static const char * const lcd2_groups[] = { "lcd2_sys_1", }; +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data_0", + "scifa2_clk_0", + "scifa2_ctrl_0", + "scifa2_data_1", + "scifa2_clk_1", + "scifa2_ctrl_1", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_ctrl", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data", + "scifa4_ctrl", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data_0", + "scifa5_clk_0", + "scifa5_ctrl_0", + "scifa5_data_1", + "scifa5_clk_1", + "scifa5_ctrl_1", + "scifa5_data_2", + "scifa5_clk_2", + "scifa5_ctrl_2", +}; + +static const char * const scifa6_groups[] = { + "scifa6", +}; + +static const char * const scifa7_groups[] = { + "scifa7_data", + "scifa7_ctrl", +}; + +static const char * const scifb_groups[] = { + "scifb_data_0", + "scifb_clk_0", + "scifb_ctrl_0", + "scifb_data_1", + "scifb_clk_1", + "scifb_ctrl_1", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(lcd2), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifa6), + SH_PFC_FUNCTION(scifa7), + SH_PFC_FUNCTION(scifb), }; #define PINMUX_FN_BASE GPIO_FN_VBUS_0 From ec3a57bb3b69a2af0f136872105335ec965cdd98 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 120/307] sh-pfc: sh73a0: Add I2C2 and I2C3 pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 64 +++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 4b0a34958fdb..fad11d7a7dde 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1846,6 +1846,50 @@ static const struct pinmux_range pinmux_ranges[] = { {.begin = 288, .end = 309,}, }; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_0_pins[] = { + /* SCL, SDA */ + 237, 236, +}; +static const unsigned int i2c2_0_mux[] = { + PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK, +}; +static const unsigned int i2c2_1_pins[] = { + /* SCL, SDA */ + 27, 28, +}; +static const unsigned int i2c2_1_mux[] = { + PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK, +}; +static const unsigned int i2c2_2_pins[] = { + /* SCL, SDA */ + 115, 116, +}; +static const unsigned int i2c2_2_mux[] = { + PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_0_pins[] = { + /* SCL, SDA */ + 248, 249, +}; +static const unsigned int i2c3_0_mux[] = { + PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK, +}; +static const unsigned int i2c3_1_pins[] = { + /* SCL, SDA */ + 27, 28, +}; +static const unsigned int i2c3_1_mux[] = { + PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK, +}; +static const unsigned int i2c3_2_pins[] = { + /* SCL, SDA */ + 115, 116, +}; +static const unsigned int i2c3_2_mux[] = { + PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK, +}; /* - LCD -------------------------------------------------------------------- */ static const unsigned int lcd_data8_pins[] = { /* D[0:7] */ @@ -2289,6 +2333,12 @@ static const unsigned int scifb_ctrl_1_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(i2c2_0), + SH_PFC_PIN_GROUP(i2c2_1), + SH_PFC_PIN_GROUP(i2c2_2), + SH_PFC_PIN_GROUP(i2c3_0), + SH_PFC_PIN_GROUP(i2c3_1), + SH_PFC_PIN_GROUP(i2c3_2), SH_PFC_PIN_GROUP(lcd_data8), SH_PFC_PIN_GROUP(lcd_data9), SH_PFC_PIN_GROUP(lcd_data12), @@ -2345,6 +2395,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb_ctrl_1), }; +static const char * const i2c2_groups[] = { + "i2c2_0", + "i2c2_1", + "i2c2_2", +}; + +static const char * const i2c3_groups[] = { + "i2c3_0", + "i2c3_1", + "i2c3_2", +}; + static const char * const lcd_groups[] = { "lcd_data8", "lcd_data9", @@ -2433,6 +2495,8 @@ static const char * const scifb_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(lcd2), SH_PFC_FUNCTION(scifa0), From 2ecd4154c906b7d60e7d06a515e6384cc58e93ab Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 121/307] sh-pfc: sh73a0: Add FSI pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 244 ++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index fad11d7a7dde..0d35f7b3e5b4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1846,6 +1846,185 @@ static const struct pinmux_range pinmux_ranges[] = { {.begin = 288, .end = 309,}, }; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 49, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 49, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 50, 51, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 50, 51, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_pins[] = { + /* ISLD */ + 55, +}; +static const unsigned int fsia_data_in_mux[] = { + FSIAISLD_MARK, +}; +static const unsigned int fsia_data_out_pins[] = { + /* OSLD */ + 52, +}; +static const unsigned int fsia_data_out_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_spdif_pins[] = { + /* SPDIF */ + 53, +}; +static const unsigned int fsia_spdif_mux[] = { + FSIASPDIF_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 54, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +static const unsigned int fsib_mclk_out_pins[] = { + /* OMC */ + 54, +}; +static const unsigned int fsib_mclk_out_mux[] = { + FSIBOMC_MARK, +}; +static const unsigned int fsib_sclk_in_pins[] = { + /* ILR, IBT */ + 37, 36, +}; +static const unsigned int fsib_sclk_in_mux[] = { + FSIBILR_MARK, FSIBIBT_MARK, +}; +static const unsigned int fsib_sclk_out_pins[] = { + /* OLR, OBT */ + 37, 36, +}; +static const unsigned int fsib_sclk_out_mux[] = { + FSIBOLR_MARK, FSIBOBT_MARK, +}; +static const unsigned int fsib_data_in_pins[] = { + /* ISLD */ + 39, +}; +static const unsigned int fsib_data_in_mux[] = { + FSIBISLD_MARK, +}; +static const unsigned int fsib_data_out_pins[] = { + /* OSLD */ + 38, +}; +static const unsigned int fsib_data_out_mux[] = { + FSIBOSLD_MARK, +}; +static const unsigned int fsib_spdif_pins[] = { + /* SPDIF */ + 53, +}; +static const unsigned int fsib_spdif_mux[] = { + FSIBSPDIF_MARK, +}; +/* - FSIC ------------------------------------------------------------------- */ +static const unsigned int fsic_mclk_in_pins[] = { + /* CK */ + 54, +}; +static const unsigned int fsic_mclk_in_mux[] = { + FSICCK_MARK, +}; +static const unsigned int fsic_mclk_out_pins[] = { + /* OMC */ + 54, +}; +static const unsigned int fsic_mclk_out_mux[] = { + FSICOMC_MARK, +}; +static const unsigned int fsic_sclk_in_pins[] = { + /* ILR, IBT */ + 46, 45, +}; +static const unsigned int fsic_sclk_in_mux[] = { + FSICILR_MARK, FSICIBT_MARK, +}; +static const unsigned int fsic_sclk_out_pins[] = { + /* OLR, OBT */ + 46, 45, +}; +static const unsigned int fsic_sclk_out_mux[] = { + FSICOLR_MARK, FSICOBT_MARK, +}; +static const unsigned int fsic_data_in_pins[] = { + /* ISLD */ + 48, +}; +static const unsigned int fsic_data_in_mux[] = { + FSICISLD_MARK, +}; +static const unsigned int fsic_data_out_pins[] = { + /* OSLD, OSLDT1, OSLDT2, OSLDT3 */ + 47, 44, 42, 16, +}; +static const unsigned int fsic_data_out_mux[] = { + FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK, +}; +static const unsigned int fsic_spdif_0_pins[] = { + /* SPDIF */ + 53, +}; +static const unsigned int fsic_spdif_0_mux[] = { + PORT53_FSICSPDIF_MARK, +}; +static const unsigned int fsic_spdif_1_pins[] = { + /* SPDIF */ + 47, +}; +static const unsigned int fsic_spdif_1_mux[] = { + PORT47_FSICSPDIF_MARK, +}; +/* - FSID ------------------------------------------------------------------- */ +static const unsigned int fsid_sclk_in_pins[] = { + /* ILR, IBT */ + 46, 45, +}; +static const unsigned int fsid_sclk_in_mux[] = { + FSIDILR_MARK, FSIDIBT_MARK, +}; +static const unsigned int fsid_sclk_out_pins[] = { + /* OLR, OBT */ + 46, 45, +}; +static const unsigned int fsid_sclk_out_mux[] = { + FSIDOLR_MARK, FSIDOBT_MARK, +}; +static const unsigned int fsid_data_in_pins[] = { + /* ISLD */ + 48, +}; +static const unsigned int fsid_data_in_mux[] = { + FSIDISLD_MARK, +}; /* - I2C2 ------------------------------------------------------------------- */ static const unsigned int i2c2_0_pins[] = { /* SCL, SDA */ @@ -2333,6 +2512,31 @@ static const unsigned int scifb_ctrl_1_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in), + SH_PFC_PIN_GROUP(fsia_data_out), + SH_PFC_PIN_GROUP(fsia_spdif), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(fsib_mclk_out), + SH_PFC_PIN_GROUP(fsib_sclk_in), + SH_PFC_PIN_GROUP(fsib_sclk_out), + SH_PFC_PIN_GROUP(fsib_data_in), + SH_PFC_PIN_GROUP(fsib_data_out), + SH_PFC_PIN_GROUP(fsib_spdif), + SH_PFC_PIN_GROUP(fsic_mclk_in), + SH_PFC_PIN_GROUP(fsic_mclk_out), + SH_PFC_PIN_GROUP(fsic_sclk_in), + SH_PFC_PIN_GROUP(fsic_sclk_out), + SH_PFC_PIN_GROUP(fsic_data_in), + SH_PFC_PIN_GROUP(fsic_data_out), + SH_PFC_PIN_GROUP(fsic_spdif_0), + SH_PFC_PIN_GROUP(fsic_spdif_1), + SH_PFC_PIN_GROUP(fsid_sclk_in), + SH_PFC_PIN_GROUP(fsid_sclk_out), + SH_PFC_PIN_GROUP(fsid_data_in), SH_PFC_PIN_GROUP(i2c2_0), SH_PFC_PIN_GROUP(i2c2_1), SH_PFC_PIN_GROUP(i2c2_2), @@ -2395,6 +2599,42 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb_ctrl_1), }; +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in", + "fsia_data_out", + "fsia_spdif", +}; + +static const char * const fsib_groups[] = { + "fsib_mclk_in", + "fsib_mclk_out", + "fsib_sclk_in", + "fsib_sclk_out", + "fsib_data_in", + "fsib_data_out", + "fsib_spdif", +}; + +static const char * const fsic_groups[] = { + "fsic_mclk_in", + "fsic_mclk_out", + "fsic_sclk_in", + "fsic_sclk_out", + "fsic_data_in", + "fsic_data_out", + "fsic_spdif", +}; + +static const char * const fsid_groups[] = { + "fsid_sclk_in", + "fsid_sclk_out", + "fsid_data_in", +}; + static const char * const i2c2_groups[] = { "i2c2_0", "i2c2_1", @@ -2495,6 +2735,10 @@ static const char * const scifb_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(fsic), + SH_PFC_FUNCTION(fsid), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(lcd), From 82f6b6da703e784b923763cc7161116829b2ca66 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 12 Feb 2013 16:50:03 +0100 Subject: [PATCH 122/307] sh-pfc: sh73a0: Add SDHI and MMCIF pin groups and functions Add pin group definitions for SDHI0, SDHI1, SDHI2 and MMCIF interfaces on sh73a0. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 194 ++++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 0d35f7b3e5b4..ed5cbaf66ac2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2263,6 +2263,66 @@ static const unsigned int lcd2_sys_1_mux[] = { PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK, LCD2RD__MARK, PORT217_LCD2RS_MARK, }; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ + 271, +}; +static const unsigned int mmc0_data1_0_mux[] = { + MMCD0_0_MARK, +}; +static const unsigned int mmc0_data4_0_pins[] = { + /* D[0:3] */ + 271, 272, 273, 274, +}; +static const unsigned int mmc0_data4_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, +}; +static const unsigned int mmc0_data8_0_pins[] = { + /* D[0:7] */ + 271, 272, 273, 274, 275, 276, 277, 278, +}; +static const unsigned int mmc0_data8_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, +}; +static const unsigned int mmc0_ctrl_0_pins[] = { + /* CMD, CLK */ + 279, 270, +}; +static const unsigned int mmc0_ctrl_0_mux[] = { + MMCCMD0_MARK, MMCCLK0_MARK, +}; + +static const unsigned int mmc0_data1_1_pins[] = { + /* D[0] */ + 305, +}; +static const unsigned int mmc0_data1_1_mux[] = { + MMCD1_0_MARK, +}; +static const unsigned int mmc0_data4_1_pins[] = { + /* D[0:3] */ + 305, 304, 303, 302, +}; +static const unsigned int mmc0_data4_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, +}; +static const unsigned int mmc0_data8_1_pins[] = { + /* D[0:7] */ + 305, 304, 303, 302, 301, 300, 299, 298, +}; +static const unsigned int mmc0_data8_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, +}; +static const unsigned int mmc0_ctrl_1_pins[] = { + /* CMD, CLK */ + 297, 289, +}; +static const unsigned int mmc0_ctrl_1_mux[] = { + MMCCMD1_MARK, MMCCLK1_MARK, +}; /* - SCIFA0 ----------------------------------------------------------------- */ static const unsigned int scifa0_data_pins[] = { /* RXD, TXD */ @@ -2510,6 +2570,86 @@ static const unsigned int scifb_ctrl_1_pins[] = { static const unsigned int scifb_ctrl_1_mux[] = { PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 252, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHID0_0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 252, 253, 254, 255, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + 256, 250, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHICMD0_MARK, SDHICLK0_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 251, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHICD0_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 257, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHIWP0_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 259, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHID1_0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 259, 260, 261, 262, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + 263, 258, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHICMD1_MARK, SDHICLK1_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 265, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHID2_0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 265, 266, 267, 268, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + 269, 264, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHICMD2_MARK, SDHICLK2_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(fsia_mclk_in), @@ -2563,6 +2703,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lcd2_sync_1), SH_PFC_PIN_GROUP(lcd2_sys_0), SH_PFC_PIN_GROUP(lcd2_sys_1), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), + SH_PFC_PIN_GROUP(mmc0_ctrl_0), + SH_PFC_PIN_GROUP(mmc0_data1_1), + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), SH_PFC_PIN_GROUP(scifa0_ctrl), @@ -2597,6 +2745,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb_data_1), SH_PFC_PIN_GROUP(scifb_clk_1), SH_PFC_PIN_GROUP(scifb_ctrl_1), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), }; static const char * const fsia_groups[] = { @@ -2673,6 +2832,17 @@ static const char * const lcd2_groups[] = { "lcd2_sys_1", }; +static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", + "mmc0_data8_0", + "mmc0_ctrl_0", + "mmc0_data1_1", + "mmc0_data4_1", + "mmc0_data8_1", + "mmc0_ctrl_1", +}; + static const char * const scifa0_groups[] = { "scifa0_data", "scifa0_clk", @@ -2734,6 +2904,26 @@ static const char * const scifb_groups[] = { "scifb_ctrl_1", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(fsia), SH_PFC_FUNCTION(fsib), @@ -2743,6 +2933,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(lcd2), + SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(scifa0), SH_PFC_FUNCTION(scifa1), SH_PFC_FUNCTION(scifa2), @@ -2752,6 +2943,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scifa6), SH_PFC_FUNCTION(scifa7), SH_PFC_FUNCTION(scifb), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), }; #define PINMUX_FN_BASE GPIO_FN_VBUS_0 From d6bab7b12e815e6c2a637a3b509143c866683c2a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 12 Mar 2013 01:55:08 +0100 Subject: [PATCH 123/307] sh-pfc: sh73a0: Add KEYSC pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 213 ++++++++++++++++++++++++++++ 1 file changed, 213 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index ed5cbaf66ac2..aad800431241 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1846,6 +1846,12 @@ static const struct pinmux_range pinmux_ranges[] = { {.begin = 288, .end = 309,}, }; +/* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. + */ +#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) + /* - FSIA ------------------------------------------------------------------- */ static const unsigned int fsia_mclk_in_pins[] = { /* CK */ @@ -2069,6 +2075,165 @@ static const unsigned int i2c3_2_pins[] = { static const unsigned int i2c3_2_mux[] = { PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK, }; +/* - KEYSC ------------------------------------------------------------------ */ +static const unsigned int keysc_in5_pins[] = { + /* KEYIN[0:4] */ + 66, 67, 68, 69, 70, +}; +static const unsigned int keysc_in5_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in6_pins[] = { + /* KEYIN[0:5] */ + 66, 67, 68, 69, 70, 71, +}; +static const unsigned int keysc_in6_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, KEYIN5_MARK, +}; +static const unsigned int keysc_in7_pins[] = { + /* KEYIN[0:6] */ + 66, 67, 68, 69, 70, 71, 72, +}; +static const unsigned int keysc_in7_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, +}; +static const unsigned int keysc_in8_pins[] = { + /* KEYIN[0:7] */ + 66, 67, 68, 69, 70, 71, 72, 73, +}; +static const unsigned int keysc_in8_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, +}; +static const unsigned int keysc_out04_pins[] = { + /* KEYOUT[0:4] */ + 65, 64, 63, 62, 61, +}; +static const unsigned int keysc_out04_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK, +}; +static const unsigned int keysc_out5_pins[] = { + /* KEYOUT5 */ + 60, +}; +static const unsigned int keysc_out5_mux[] = { + KEYOUT5_MARK, +}; +static const unsigned int keysc_out6_0_pins[] = { + /* KEYOUT6 */ + 59, +}; +static const unsigned int keysc_out6_0_mux[] = { + PORT59_KEYOUT6_MARK, +}; +static const unsigned int keysc_out6_1_pins[] = { + /* KEYOUT6 */ + 131, +}; +static const unsigned int keysc_out6_1_mux[] = { + PORT131_KEYOUT6_MARK, +}; +static const unsigned int keysc_out6_2_pins[] = { + /* KEYOUT6 */ + 143, +}; +static const unsigned int keysc_out6_2_mux[] = { + PORT143_KEYOUT6_MARK, +}; +static const unsigned int keysc_out7_0_pins[] = { + /* KEYOUT7 */ + 58, +}; +static const unsigned int keysc_out7_0_mux[] = { + PORT58_KEYOUT7_MARK, +}; +static const unsigned int keysc_out7_1_pins[] = { + /* KEYOUT7 */ + 132, +}; +static const unsigned int keysc_out7_1_mux[] = { + PORT132_KEYOUT7_MARK, +}; +static const unsigned int keysc_out7_2_pins[] = { + /* KEYOUT7 */ + 144, +}; +static const unsigned int keysc_out7_2_mux[] = { + PORT144_KEYOUT7_MARK, +}; +static const unsigned int keysc_out8_0_pins[] = { + /* KEYOUT8 */ + PIN_NUMBER(6, 26), +}; +static const unsigned int keysc_out8_0_mux[] = { + KEYOUT8_MARK, +}; +static const unsigned int keysc_out8_1_pins[] = { + /* KEYOUT8 */ + 136, +}; +static const unsigned int keysc_out8_1_mux[] = { + PORT136_KEYOUT8_MARK, +}; +static const unsigned int keysc_out8_2_pins[] = { + /* KEYOUT8 */ + 138, +}; +static const unsigned int keysc_out8_2_mux[] = { + PORT138_KEYOUT8_MARK, +}; +static const unsigned int keysc_out9_0_pins[] = { + /* KEYOUT9 */ + 137, +}; +static const unsigned int keysc_out9_0_mux[] = { + PORT137_KEYOUT9_MARK, +}; +static const unsigned int keysc_out9_1_pins[] = { + /* KEYOUT9 */ + 139, +}; +static const unsigned int keysc_out9_1_mux[] = { + PORT139_KEYOUT9_MARK, +}; +static const unsigned int keysc_out9_2_pins[] = { + /* KEYOUT9 */ + 149, +}; +static const unsigned int keysc_out9_2_mux[] = { + PORT149_KEYOUT9_MARK, +}; +static const unsigned int keysc_out10_0_pins[] = { + /* KEYOUT10 */ + 132, +}; +static const unsigned int keysc_out10_0_mux[] = { + PORT132_KEYOUT10_MARK, +}; +static const unsigned int keysc_out10_1_pins[] = { + /* KEYOUT10 */ + 142, +}; +static const unsigned int keysc_out10_1_mux[] = { + PORT142_KEYOUT10_MARK, +}; +static const unsigned int keysc_out11_0_pins[] = { + /* KEYOUT11 */ + 131, +}; +static const unsigned int keysc_out11_0_mux[] = { + PORT131_KEYOUT11_MARK, +}; +static const unsigned int keysc_out11_1_pins[] = { + /* KEYOUT11 */ + 143, +}; +static const unsigned int keysc_out11_1_mux[] = { + PORT143_KEYOUT11_MARK, +}; /* - LCD -------------------------------------------------------------------- */ static const unsigned int lcd_data8_pins[] = { /* D[0:7] */ @@ -2683,6 +2848,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_0), SH_PFC_PIN_GROUP(i2c3_1), SH_PFC_PIN_GROUP(i2c3_2), + SH_PFC_PIN_GROUP(keysc_in5), + SH_PFC_PIN_GROUP(keysc_in6), + SH_PFC_PIN_GROUP(keysc_in7), + SH_PFC_PIN_GROUP(keysc_in8), + SH_PFC_PIN_GROUP(keysc_out04), + SH_PFC_PIN_GROUP(keysc_out5), + SH_PFC_PIN_GROUP(keysc_out6_0), + SH_PFC_PIN_GROUP(keysc_out6_1), + SH_PFC_PIN_GROUP(keysc_out6_2), + SH_PFC_PIN_GROUP(keysc_out7_0), + SH_PFC_PIN_GROUP(keysc_out7_1), + SH_PFC_PIN_GROUP(keysc_out7_2), + SH_PFC_PIN_GROUP(keysc_out8_0), + SH_PFC_PIN_GROUP(keysc_out8_1), + SH_PFC_PIN_GROUP(keysc_out8_2), + SH_PFC_PIN_GROUP(keysc_out9_0), + SH_PFC_PIN_GROUP(keysc_out9_1), + SH_PFC_PIN_GROUP(keysc_out9_2), + SH_PFC_PIN_GROUP(keysc_out10_0), + SH_PFC_PIN_GROUP(keysc_out10_1), + SH_PFC_PIN_GROUP(keysc_out11_0), + SH_PFC_PIN_GROUP(keysc_out11_1), SH_PFC_PIN_GROUP(lcd_data8), SH_PFC_PIN_GROUP(lcd_data9), SH_PFC_PIN_GROUP(lcd_data12), @@ -2806,6 +2993,31 @@ static const char * const i2c3_groups[] = { "i2c3_2", }; +static const char * const keysc_groups[] = { + "keysc_in5", + "keysc_in6", + "keysc_in7", + "keysc_in8", + "keysc_out04", + "keysc_out5", + "keysc_out6_0", + "keysc_out6_1", + "keysc_out6_2", + "keysc_out7_0", + "keysc_out7_1", + "keysc_out7_2", + "keysc_out8_0", + "keysc_out8_1", + "keysc_out8_2", + "keysc_out9_0", + "keysc_out9_1", + "keysc_out9_2", + "keysc_out10_0", + "keysc_out10_1", + "keysc_out11_0", + "keysc_out11_1", +}; + static const char * const lcd_groups[] = { "lcd_data8", "lcd_data9", @@ -2931,6 +3143,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(fsid), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(keysc), SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(lcd2), SH_PFC_FUNCTION(mmc0), From e24c62a6ce6b789d1372397894ffdea43e3a9f36 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 12 Mar 2013 01:55:08 +0100 Subject: [PATCH 124/307] sh-pfc: sh73a0: Add BSC pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 124 ++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index aad800431241..76674af19d29 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1852,6 +1852,100 @@ static const struct pinmux_range pinmux_ranges[] = { */ #define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data_0_7_pins[] = { + /* D[0:7] */ + 74, 75, 76, 77, 78, 79, 80, 81, +}; +static const unsigned int bsc_data_0_7_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data_8_15_pins[] = { + /* D[8:15] */ + 82, 83, 84, 85, 86, 87, 88, 89, +}; +static const unsigned int bsc_data_8_15_mux[] = { + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 90, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4__MARK, +}; +static const unsigned int bsc_cs5_a_pins[] = { + /* CS */ + 91, +}; +static const unsigned int bsc_cs5_a_mux[] = { + CS5A__MARK, +}; +static const unsigned int bsc_cs5_b_pins[] = { + /* CS */ + 92, +}; +static const unsigned int bsc_cs5_b_mux[] = { + CS5B__MARK, +}; +static const unsigned int bsc_cs6_a_pins[] = { + /* CS */ + 94, +}; +static const unsigned int bsc_cs6_a_mux[] = { + CS6A__MARK, +}; +static const unsigned int bsc_cs6_b_pins[] = { + /* CS */ + 93, +}; +static const unsigned int bsc_cs6_b_mux[] = { + CS6B__MARK, +}; +static const unsigned int bsc_rd_pins[] = { + /* RD */ + 96, +}; +static const unsigned int bsc_rd_mux[] = { + RD__FSC_MARK, +}; +static const unsigned int bsc_rdwr_0_pins[] = { + /* RDWR */ + 91, +}; +static const unsigned int bsc_rdwr_0_mux[] = { + PORT91_RDWR_MARK, +}; +static const unsigned int bsc_rdwr_1_pins[] = { + /* RDWR */ + 97, +}; +static const unsigned int bsc_rdwr_1_mux[] = { + RDWR_FWE_MARK, +}; +static const unsigned int bsc_rdwr_2_pins[] = { + /* RDWR */ + 149, +}; +static const unsigned int bsc_rdwr_2_mux[] = { + PORT149_RDWR_MARK, +}; +static const unsigned int bsc_we0_pins[] = { + /* WE0 */ + 97, +}; +static const unsigned int bsc_we0_mux[] = { + WE0__FWE_MARK, +}; +static const unsigned int bsc_we1_pins[] = { + /* WE1 */ + 98, +}; +static const unsigned int bsc_we1_mux[] = { + WE1__MARK, +}; /* - FSIA ------------------------------------------------------------------- */ static const unsigned int fsia_mclk_in_pins[] = { /* CK */ @@ -2817,6 +2911,19 @@ static const unsigned int sdhi2_ctrl_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data_0_7), + SH_PFC_PIN_GROUP(bsc_data_8_15), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5_a), + SH_PFC_PIN_GROUP(bsc_cs5_b), + SH_PFC_PIN_GROUP(bsc_cs6_a), + SH_PFC_PIN_GROUP(bsc_cs6_b), + SH_PFC_PIN_GROUP(bsc_rd), + SH_PFC_PIN_GROUP(bsc_rdwr_0), + SH_PFC_PIN_GROUP(bsc_rdwr_1), + SH_PFC_PIN_GROUP(bsc_rdwr_2), + SH_PFC_PIN_GROUP(bsc_we0), + SH_PFC_PIN_GROUP(bsc_we1), SH_PFC_PIN_GROUP(fsia_mclk_in), SH_PFC_PIN_GROUP(fsia_mclk_out), SH_PFC_PIN_GROUP(fsia_sclk_in), @@ -2945,6 +3052,22 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_ctrl), }; +static const char * const bsc_groups[] = { + "bsc_data_0_7", + "bsc_data_8_15", + "bsc_cs4", + "bsc_cs5_a", + "bsc_cs5_b", + "bsc_cs6_a", + "bsc_cs6_b", + "bsc_rd", + "bsc_rdwr_0", + "bsc_rdwr_1", + "bsc_rdwr_2", + "bsc_we0", + "bsc_we1", +}; + static const char * const fsia_groups[] = { "fsia_mclk_in", "fsia_mclk_out", @@ -3137,6 +3260,7 @@ static const char * const sdhi2_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), SH_PFC_FUNCTION(fsia), SH_PFC_FUNCTION(fsib), SH_PFC_FUNCTION(fsic), From a6aa1c7b0ac6a57dac5855c64316057771f186e4 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 12 Mar 2013 01:55:08 +0100 Subject: [PATCH 125/307] sh-pfc: sh73a0: Add USB pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 76674af19d29..61c682aa38ef 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2909,6 +2909,14 @@ static const unsigned int sdhi2_ctrl_pins[] = { static const unsigned int sdhi2_ctrl_mux[] = { SDHICMD2_MARK, SDHICLK2_MARK, }; +/* - USB -------------------------------------------------------------------- */ +static const unsigned int usb_vbus_pins[] = { + /* VBUS */ + 0, +}; +static const unsigned int usb_vbus_mux[] = { + VBUS_0_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(bsc_data_0_7), @@ -3050,6 +3058,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_data1), SH_PFC_PIN_GROUP(sdhi2_data4), SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(usb_vbus), }; static const char * const bsc_groups[] = { @@ -3259,6 +3268,10 @@ static const char * const sdhi2_groups[] = { "sdhi2_ctrl", }; +static const char * const usb_groups[] = { + "usb_vbus", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(bsc), SH_PFC_FUNCTION(fsia), @@ -3283,6 +3296,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb), }; #define PINMUX_FN_BASE GPIO_FN_VBUS_0 From 512b156cefb2931a483ff3dd25852d122230894a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 12 Mar 2013 01:55:08 +0100 Subject: [PATCH 126/307] sh-pfc: sh73a0: Add IrDA pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 61c682aa38ef..8fc5eb0025c5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2169,6 +2169,21 @@ static const unsigned int i2c3_2_pins[] = { static const unsigned int i2c3_2_mux[] = { PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK, }; +/* - IrDA ------------------------------------------------------------------- */ +static const unsigned int irda_0_pins[] = { + /* OUT, IN, FIRSEL */ + 241, 242, 243, +}; +static const unsigned int irda_0_mux[] = { + PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK, +}; +static const unsigned int irda_1_pins[] = { + /* OUT, IN, FIRSEL */ + 49, 53, 54, +}; +static const unsigned int irda_1_mux[] = { + PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK, +}; /* - KEYSC ------------------------------------------------------------------ */ static const unsigned int keysc_in5_pins[] = { /* KEYIN[0:4] */ @@ -2963,6 +2978,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_0), SH_PFC_PIN_GROUP(i2c3_1), SH_PFC_PIN_GROUP(i2c3_2), + SH_PFC_PIN_GROUP(irda_0), + SH_PFC_PIN_GROUP(irda_1), SH_PFC_PIN_GROUP(keysc_in5), SH_PFC_PIN_GROUP(keysc_in6), SH_PFC_PIN_GROUP(keysc_in7), @@ -3125,6 +3142,11 @@ static const char * const i2c3_groups[] = { "i2c3_2", }; +static const char * const irda_groups[] = { + "irda_0", + "irda_1", +}; + static const char * const keysc_groups[] = { "keysc_in5", "keysc_in6", @@ -3280,6 +3302,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(fsid), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(irda), SH_PFC_FUNCTION(keysc), SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(lcd2), From 06c7dd866da70f6c324ae3990b2c0d77fb2d07f5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 127/307] sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 276 +++++++++++++++++++++++++++ 1 file changed, 276 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index de13348be5c0..e16ec10b7dc1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -1658,6 +1658,277 @@ static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; +/* - LCD0 ------------------------------------------------------------------- */ +static const unsigned int lcd0_data8_pins[] = { + /* D[0:7] */ + 58, 57, 56, 55, 54, 53, 52, 51, +}; +static const unsigned int lcd0_data8_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, +}; +static const unsigned int lcd0_data9_pins[] = { + /* D[0:8] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, +}; +static const unsigned int lcd0_data9_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, +}; +static const unsigned int lcd0_data12_pins[] = { + /* D[0:11] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, +}; +static const unsigned int lcd0_data12_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, +}; +static const unsigned int lcd0_data16_pins[] = { + /* D[0:15] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, +}; +static const unsigned int lcd0_data16_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, +}; +static const unsigned int lcd0_data18_pins[] = { + /* D[0:17] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, +}; +static const unsigned int lcd0_data18_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, +}; +static const unsigned int lcd0_data24_0_pins[] = { + /* D[0:23] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 40, 4, 3, 2, 0, 1, +}; +static const unsigned int lcd0_data24_0_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK, + LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK, + LCD0_D23_PORT1_MARK, +}; +static const unsigned int lcd0_data24_1_pins[] = { + /* D[0:23] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 163, 162, 161, 158, 160, 159, +}; +static const unsigned int lcd0_data24_1_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK, + LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK, + LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK, +}; +static const unsigned int lcd0_display_pins[] = { + /* DON, VCPWC, VEPWC */ + 61, 59, 60, +}; +static const unsigned int lcd0_display_mux[] = { + LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, +}; +static const unsigned int lcd0_lclk_0_pins[] = { + /* LCLK */ + 102, +}; +static const unsigned int lcd0_lclk_0_mux[] = { + LCD0_LCLK_PORT102_MARK, +}; +static const unsigned int lcd0_lclk_1_pins[] = { + /* LCLK */ + 165, +}; +static const unsigned int lcd0_lclk_1_mux[] = { + LCD0_LCLK_PORT165_MARK, +}; +static const unsigned int lcd0_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 63, 64, 62, 65, +}; +static const unsigned int lcd0_sync_mux[] = { + LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK, +}; +static const unsigned int lcd0_sys_pins[] = { + /* CS, WR, RD, RS */ + 64, 62, 164, 65, +}; +static const unsigned int lcd0_sys_mux[] = { + LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK, +}; +/* - LCD1 ------------------------------------------------------------------- */ +static const unsigned int lcd1_data8_pins[] = { + /* D[0:7] */ + 4, 3, 2, 1, 0, 91, 92, 23, +}; +static const unsigned int lcd1_data8_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, +}; +static const unsigned int lcd1_data9_pins[] = { + /* D[0:8] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, +}; +static const unsigned int lcd1_data9_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, +}; +static const unsigned int lcd1_data12_pins[] = { + /* D[0:12] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, +}; +static const unsigned int lcd1_data12_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, +}; +static const unsigned int lcd1_data16_pins[] = { + /* D[0:15] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, 200, 199, 196, 195, +}; +static const unsigned int lcd1_data16_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, +}; +static const unsigned int lcd1_data18_pins[] = { + /* D[0:17] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, 200, 199, 196, 195, + 194, 193, +}; +static const unsigned int lcd1_data18_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, + LCD1_D16_MARK, LCD1_D17_MARK, +}; +static const unsigned int lcd1_data24_pins[] = { + /* D[0:23] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, 200, 199, 196, 195, + 194, 193, 198, 197, 75, 74, 15, 14, +}; +static const unsigned int lcd1_data24_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, + LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, + LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, +}; +static const unsigned int lcd1_display_pins[] = { + /* DON, VCPWC, VEPWC */ + 100, 5, 6, +}; +static const unsigned int lcd1_display_mux[] = { + LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK, +}; +static const unsigned int lcd1_lclk_pins[] = { + /* LCLK */ + 40, +}; +static const unsigned int lcd1_lclk_mux[] = { + LCD1_LCLK_MARK, +}; +static const unsigned int lcd1_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 98, 97, 99, 12, +}; +static const unsigned int lcd1_sync_mux[] = { + LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK, +}; +static const unsigned int lcd1_sys_pins[] = { + /* CS, WR, RD, RS */ + 97, 99, 13, 12, +}; +static const unsigned int lcd1_sys_mux[] = { + LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(lcd0_data8), + SH_PFC_PIN_GROUP(lcd0_data9), + SH_PFC_PIN_GROUP(lcd0_data12), + SH_PFC_PIN_GROUP(lcd0_data16), + SH_PFC_PIN_GROUP(lcd0_data18), + SH_PFC_PIN_GROUP(lcd0_data24_0), + SH_PFC_PIN_GROUP(lcd0_data24_1), + SH_PFC_PIN_GROUP(lcd0_display), + SH_PFC_PIN_GROUP(lcd0_lclk_0), + SH_PFC_PIN_GROUP(lcd0_lclk_1), + SH_PFC_PIN_GROUP(lcd0_sync), + SH_PFC_PIN_GROUP(lcd0_sys), + SH_PFC_PIN_GROUP(lcd1_data8), + SH_PFC_PIN_GROUP(lcd1_data9), + SH_PFC_PIN_GROUP(lcd1_data12), + SH_PFC_PIN_GROUP(lcd1_data16), + SH_PFC_PIN_GROUP(lcd1_data18), + SH_PFC_PIN_GROUP(lcd1_data24), + SH_PFC_PIN_GROUP(lcd1_display), + SH_PFC_PIN_GROUP(lcd1_lclk), + SH_PFC_PIN_GROUP(lcd1_sync), + SH_PFC_PIN_GROUP(lcd1_sys), +}; + +static const char * const lcd0_groups[] = { + "lcd0_data8", + "lcd0_data9", + "lcd0_data12", + "lcd0_data16", + "lcd0_data18", + "lcd0_data24_0", + "lcd0_data24_1", + "lcd0_display", + "lcd0_lclk_0", + "lcd0_lclk_1", + "lcd0_sync", + "lcd0_sys", +}; + +static const char * const lcd1_groups[] = { + "lcd1_data8", + "lcd1_data9", + "lcd1_data12", + "lcd1_data16", + "lcd1_data18", + "lcd1_data24", + "lcd1_display", + "lcd1_lclk", + "lcd1_sync", + "lcd1_sys", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), +}; + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) static const struct pinmux_func pinmux_func_gpios[] = { @@ -2596,6 +2867,11 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), From 8b2810b9578612e093420a8c9d56d2e83e3c9496 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 23 Jan 2013 17:37:44 +0100 Subject: [PATCH 128/307] sh-pfc: r8a7740: Add SDHI and MMCIF pin groups and functions Add pin groups for the first two SDHI interfaces and two alternative pin groups for the MMCIF interface on the r8a7740 SoC. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 248 +++++++++++++++++++++++++++ 1 file changed, 248 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index e16ec10b7dc1..a2f909a7c235 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -1870,6 +1870,188 @@ static const unsigned int lcd1_sys_pins[] = { static const unsigned int lcd1_sys_mux[] = { LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK, }; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ + 68, +}; +static const unsigned int mmc0_data1_0_mux[] = { + MMC0_D0_PORT68_MARK, +}; +static const unsigned int mmc0_data4_0_pins[] = { + /* D[0:3] */ + 68, 69, 70, 71, +}; +static const unsigned int mmc0_data4_0_mux[] = { + MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, +}; +static const unsigned int mmc0_data8_0_pins[] = { + /* D[0:7] */ + 68, 69, 70, 71, 72, 73, 74, 75, +}; +static const unsigned int mmc0_data8_0_mux[] = { + MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, + MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, +}; +static const unsigned int mmc0_ctrl_0_pins[] = { + /* CMD, CLK */ + 67, 66, +}; +static const unsigned int mmc0_ctrl_0_mux[] = { + MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK, +}; + +static const unsigned int mmc0_data1_1_pins[] = { + /* D[0] */ + 149, +}; +static const unsigned int mmc0_data1_1_mux[] = { + MMC1_D0_PORT149_MARK, +}; +static const unsigned int mmc0_data4_1_pins[] = { + /* D[0:3] */ + 149, 148, 147, 146, +}; +static const unsigned int mmc0_data4_1_mux[] = { + MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, +}; +static const unsigned int mmc0_data8_1_pins[] = { + /* D[0:7] */ + 149, 148, 147, 146, 145, 144, 143, 142, +}; +static const unsigned int mmc0_data8_1_mux[] = { + MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, + MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, +}; +static const unsigned int mmc0_ctrl_1_pins[] = { + /* CMD, CLK */ + 104, 103, +}; +static const unsigned int mmc0_ctrl_1_mux[] = { + MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 77, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHI0_D0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 77, 78, 79, 80, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + 76, 82, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHI0_CMD_MARK, SDHI0_CLK_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 81, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHI0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 83, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHI0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 68, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHI1_D0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 68, 69, 70, 71, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + 67, 66, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHI1_CMD_MARK, SDHI1_CLK_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + 72, +}; +static const unsigned int sdhi1_cd_mux[] = { + SDHI1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + 73, +}; +static const unsigned int sdhi1_wp_mux[] = { + SDHI1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 205, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHI2_D0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 205, 206, 207, 208, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + 204, 203, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHI2_CMD_MARK, SDHI2_CLK_MARK, +}; +static const unsigned int sdhi2_cd_0_pins[] = { + /* CD */ + 202, +}; +static const unsigned int sdhi2_cd_0_mux[] = { + SDHI2_CD_PORT202_MARK, +}; +static const unsigned int sdhi2_wp_0_pins[] = { + /* WP */ + 177, +}; +static const unsigned int sdhi2_wp_0_mux[] = { + SDHI2_WP_PORT177_MARK, +}; +static const unsigned int sdhi2_cd_1_pins[] = { + /* CD */ + 24, +}; +static const unsigned int sdhi2_cd_1_mux[] = { + SDHI2_CD_PORT24_MARK, +}; +static const unsigned int sdhi2_wp_1_pins[] = { + /* WP */ + 25, +}; +static const unsigned int sdhi2_wp_1_mux[] = { + SDHI2_WP_PORT25_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lcd0_data8), @@ -1894,6 +2076,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lcd1_lclk), SH_PFC_PIN_GROUP(lcd1_sync), SH_PFC_PIN_GROUP(lcd1_sys), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), + SH_PFC_PIN_GROUP(mmc0_ctrl_0), + SH_PFC_PIN_GROUP(mmc0_data1_1), + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_0), + SH_PFC_PIN_GROUP(sdhi2_wp_0), + SH_PFC_PIN_GROUP(sdhi2_cd_1), + SH_PFC_PIN_GROUP(sdhi2_wp_1), }; static const char * const lcd0_groups[] = { @@ -1924,9 +2131,50 @@ static const char * const lcd1_groups[] = { "lcd1_sys", }; +static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", + "mmc0_data8_0", + "mmc0_ctrl_0", + "mmc0_data1_1", + "mmc0_data4_1", + "mmc0_data8_1", + "mmc0_ctrl_1", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd_0", + "sdhi2_wp_0", + "sdhi2_cd_1", + "sdhi2_wp_1", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(lcd0), SH_PFC_FUNCTION(lcd1), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), }; #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) From e8ebafdfea399580b1bee7e83b955c6175b8a6c4 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 129/307] sh-pfc: r8a7779: Add DU pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 283 ++++++++++++++++++++++----- 1 file changed, 236 insertions(+), 47 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index eb5685848b68..9046a8f71d49 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1436,6 +1436,190 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - DU0 -------------------------------------------------------------------- */ +static const unsigned int du0_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + 188, 187, 186, 185, 184, 183, + 194, 193, 192, 191, 190, 189, + 200, 199, 198, 197, 196, 195, +}; +static const unsigned int du0_rgb666_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, +}; +static const unsigned int du0_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + 188, 187, 186, 185, 184, 183, 24, 23, + 194, 193, 192, 191, 190, 189, 26, 25, + 200, 199, 198, 197, 196, 195, 28, 27, +}; +static const unsigned int du0_rgb888_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, +}; +static const unsigned int du0_clk_0_pins[] = { + /* CLKIN, CLKOUT */ + 29, 180, +}; +static const unsigned int du0_clk_0_mux[] = { + DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK, +}; +static const unsigned int du0_clk_1_pins[] = { + /* CLKIN, CLKOUT */ + 29, 30, +}; +static const unsigned int du0_clk_1_mux[] = { + DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK, +}; +static const unsigned int du0_sync_0_pins[] = { + /* VSYNC, HSYNC, DISP */ + 182, 181, 31, +}; +static const unsigned int du0_sync_0_mux[] = { + DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK +}; +static const unsigned int du0_sync_1_pins[] = { + /* VSYNC, HSYNC, DISP */ + 182, 181, 32, +}; +static const unsigned int du0_sync_1_mux[] = { + DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, + DU0_DISP_MARK +}; +static const unsigned int du0_oddf_pins[] = { + /* ODDF */ + 31, +}; +static const unsigned int du0_oddf_mux[] = { + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK +}; +static const unsigned int du0_cde_pins[] = { + /* CDE */ + 33, +}; +static const unsigned int du0_cde_mux[] = { + DU0_CDE_MARK +}; +/* - DU1 -------------------------------------------------------------------- */ +static const unsigned int du1_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + 41, 40, 39, 38, 37, 36, + 49, 48, 47, 46, 45, 44, + 57, 56, 55, 54, 53, 52, +}; +static const unsigned int du1_rgb666_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, +}; +static const unsigned int du1_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + 41, 40, 39, 38, 37, 36, 35, 34, + 49, 48, 47, 46, 45, 44, 43, 32, + 57, 56, 55, 54, 53, 52, 51, 50, +}; +static const unsigned int du1_rgb888_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, +}; +static const unsigned int du1_clk_pins[] = { + /* CLKIN, CLKOUT */ + 58, 59, +}; +static const unsigned int du1_clk_mux[] = { + DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK, +}; +static const unsigned int du1_sync_0_pins[] = { + /* VSYNC, HSYNC, DISP */ + 61, 60, 62, +}; +static const unsigned int du1_sync_0_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK +}; +static const unsigned int du1_sync_1_pins[] = { + /* VSYNC, HSYNC, DISP */ + 61, 60, 63, +}; +static const unsigned int du1_sync_1_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, + DU1_DISP_MARK +}; +static const unsigned int du1_oddf_pins[] = { + /* ODDF */ + 62, +}; +static const unsigned int du1_oddf_mux[] = { + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK +}; +static const unsigned int du1_cde_pins[] = { + /* CDE */ + 64, +}; +static const unsigned int du1_cde_mux[] = { + DU1_CDE_MARK +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(du0_rgb666), + SH_PFC_PIN_GROUP(du0_rgb888), + SH_PFC_PIN_GROUP(du0_clk_0), + SH_PFC_PIN_GROUP(du0_clk_1), + SH_PFC_PIN_GROUP(du0_sync_0), + SH_PFC_PIN_GROUP(du0_sync_1), + SH_PFC_PIN_GROUP(du0_oddf), + SH_PFC_PIN_GROUP(du0_cde), + SH_PFC_PIN_GROUP(du1_rgb666), + SH_PFC_PIN_GROUP(du1_rgb888), + SH_PFC_PIN_GROUP(du1_clk), + SH_PFC_PIN_GROUP(du1_sync_0), + SH_PFC_PIN_GROUP(du1_sync_1), + SH_PFC_PIN_GROUP(du1_oddf), + SH_PFC_PIN_GROUP(du1_cde), +}; + +static const char * const du0_groups[] = { + "du0_rgb666", + "du0_rgb888", + "du0_clk_0", + "du0_clk_1", + "du0_sync_0", + "du0_sync_1", + "du0_oddf", + "du0_cde", +}; + +static const char * const du1_groups[] = { + "du1_rgb666", + "du1_rgb888", + "du1_clk", + "du1_sync_0", + "du1_sync_1", + "du1_oddf", + "du1_cde", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), +}; + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) static const struct pinmux_func pinmux_func_gpios[] = { @@ -1494,79 +1678,79 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS), GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), - GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0), + GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0), GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), - GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), + GPIO_FN(TX5_C), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C), - GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3), - GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5), - GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7), - GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), + GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3), + GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5), + GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7), + GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), GPIO_FN(AUDATA2), /* IPSR3 */ - GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), - GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10), - GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4), - GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13), - GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7), - GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16), + GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), + GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10), + GPIO_FN(LCDOUT11), + GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13), + GPIO_FN(LCDOUT14), + GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16), GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), - GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), + GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C), - GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3), - GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20), - GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6), - GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23), - GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D), - GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK), - GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D), + GPIO_FN(LCDOUT18), + GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20), + GPIO_FN(LCDOUT21), + GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23), + GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D), + GPIO_FN(SCL3_B), GPIO_FN(QCLK), + GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D), GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B), - GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS), - GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), - GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), + GPIO_FN(QSTH_QHS), + GPIO_FN(QSTB_QHE), + GPIO_FN(QCPV_QDE), GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), /* IPSR4 */ - GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), - GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), + GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), + GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), - GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), + GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), - GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1), + GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1), GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E), - GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0), - GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2), - GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4), - GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0), + GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(VI2_G0), + GPIO_FN(VI2_G1), GPIO_FN(VI2_G2), + GPIO_FN(VI2_G3), GPIO_FN(VI2_G4), + GPIO_FN(VI2_G5), GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2), - GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1), + GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3), - GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2), - GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4), - GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6), - GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0), + GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), + GPIO_FN(VI2_G6), GPIO_FN(VI2_G7), + GPIO_FN(VI2_R0), GPIO_FN(VI2_R1), + GPIO_FN(VI2_R2), GPIO_FN(VI2_R3), GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0), GPIO_FN(TX5), GPIO_FN(SCK0_D), /* IPSR5 */ - GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), + GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), - GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5), - GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7), - GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D), - GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1), - GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD), - GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC), - GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC), - GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), + GPIO_FN(VI2_R4), GPIO_FN(VI2_R5), + GPIO_FN(VI2_R6), GPIO_FN(VI2_R7), + GPIO_FN(SCL2_D), GPIO_FN(SDA2_D), + GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1), + GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD), + GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC), + GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC), + GPIO_FN(VI3_VSYNC), GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD), GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN), - GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6), + GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6), GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), - GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), + GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D), GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), @@ -2598,6 +2782,11 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), From 6dbf296a452ff5c1613be989f4e3ce10568cf6df Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 19:04:43 +0100 Subject: [PATCH 130/307] sh-pfc: r8a7779: Add SDHI and MMCIF pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 284 +++++++++++++++++++++++++++ 1 file changed, 284 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 9046a8f71d49..ca16b04edd6d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1575,6 +1575,210 @@ static const unsigned int du1_cde_pins[] = { static const unsigned int du1_cde_mux[] = { DU1_CDE_MARK }; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + 19, +}; +static const unsigned int mmc0_data1_mux[] = { + MMC0_D0_MARK, +}; +static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ + 19, 20, 21, 2, +}; +static const unsigned int mmc0_data4_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +}; +static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ + 19, 20, 21, 2, 10, 11, 15, 16, +}; +static const unsigned int mmc0_data8_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, + MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, +}; +static const unsigned int mmc0_ctrl_pins[] = { + /* CMD, CLK */ + 18, 17, +}; +static const unsigned int mmc0_ctrl_mux[] = { + MMC0_CMD_MARK, MMC0_CLK_MARK, +}; + +static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + 72, +}; +static const unsigned int mmc1_data1_mux[] = { + MMC1_D0_MARK, +}; +static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ + 72, 73, 74, 75, +}; +static const unsigned int mmc1_data4_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +}; +static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ + 72, 73, 74, 75, 76, 77, 80, 81, +}; +static const unsigned int mmc1_data8_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, + MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, +}; +static const unsigned int mmc1_ctrl_pins[] = { + /* CMD, CLK */ + 68, 65, +}; +static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CMD_MARK, MMC1_CLK_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 117, +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 117, 118, 119, 120, +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + 114, 113, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CMD_MARK, SD0_CLK_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 115, +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 116, +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 19, +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 19, 20, 21, 2, +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + 18, 17, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CMD_MARK, SD1_CLK_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + 10, +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + 11, +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 97, +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 97, 98, 99, 100, +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + 102, 101, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CMD_MARK, SD2_CLK_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + 103, +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + 104, +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + 50, +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + 50, 51, 52, 53, +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CMD, CLK */ + 35, 34, +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CMD_MARK, SD3_CLK_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + 62, +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + 64, +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_rgb666), @@ -1592,6 +1796,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du1_sync_1), SH_PFC_PIN_GROUP(du1_oddf), SH_PFC_PIN_GROUP(du1_cde), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), }; static const char * const du0_groups[] = { @@ -1615,9 +1847,61 @@ static const char * const du1_groups[] = { "du1_cde", }; +static const char * const mmc0_groups[] = { + "mmc0_data1", + "mmc0_data4", + "mmc0_data8", + "mmc0_ctrl", +}; + +static const char * const mmc1_groups[] = { + "mmc1_data1", + "mmc1_data4", + "mmc1_data8", + "mmc1_ctrl", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), }; #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) From 081b69bbb2c2df2f00b420f9f612c1c3ee0be592 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 19:04:43 +0100 Subject: [PATCH 131/307] sh-pfc: r8a7779: Add SCIF pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 490 +++++++++++++++++++++++++++ 1 file changed, 490 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index ca16b04edd6d..a01adea444e1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1635,6 +1635,370 @@ static const unsigned int mmc1_ctrl_pins[] = { static const unsigned int mmc1_ctrl_mux[] = { MMC1_CMD_MARK, MMC1_CLK_MARK, }; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RXD, TXD */ + 153, 152, +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + 156, +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + 151, 150, +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_TANS_MARK, CTS0_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RXD, TXD */ + 20, 19, +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ + 33, +}; +static const unsigned int scif0_clk_b_mux[] = { + SCK0_B_MARK, +}; +static const unsigned int scif0_ctrl_b_pins[] = { + /* RTS, CTS */ + 18, 11, +}; +static const unsigned int scif0_ctrl_b_mux[] = { + RTS0_B_TANS_B_MARK, CTS0_B_MARK, +}; +static const unsigned int scif0_data_c_pins[] = { + /* RXD, TXD */ + 146, 147, +}; +static const unsigned int scif0_data_c_mux[] = { + RX0_C_MARK, TX0_C_MARK, +}; +static const unsigned int scif0_clk_c_pins[] = { + /* SCK */ + 145, +}; +static const unsigned int scif0_clk_c_mux[] = { + SCK0_C_MARK, +}; +static const unsigned int scif0_ctrl_c_pins[] = { + /* RTS, CTS */ + 149, 148, +}; +static const unsigned int scif0_ctrl_c_mux[] = { + RTS0_C_TANS_C_MARK, CTS0_C_MARK, +}; +static const unsigned int scif0_data_d_pins[] = { + /* RXD, TXD */ + 43, 42, +}; +static const unsigned int scif0_data_d_mux[] = { + RX0_D_MARK, TX0_D_MARK, +}; +static const unsigned int scif0_clk_d_pins[] = { + /* SCK */ + 50, +}; +static const unsigned int scif0_clk_d_mux[] = { + SCK0_D_MARK, +}; +static const unsigned int scif0_ctrl_d_pins[] = { + /* RTS, CTS */ + 51, 35, +}; +static const unsigned int scif0_ctrl_d_mux[] = { + RTS0_D_TANS_D_MARK, CTS0_D_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RXD, TXD */ + 149, 148, +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + 145, +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + 147, 146, +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_TANS_MARK, CTS1_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RXD, TXD */ + 117, 114, +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ + 113, +}; +static const unsigned int scif1_clk_b_mux[] = { + SCK1_B_MARK, +}; +static const unsigned int scif1_ctrl_b_pins[] = { + /* RTS, CTS */ + 115, 116, +}; +static const unsigned int scif1_ctrl_b_mux[] = { + RTS1_B_TANS_B_MARK, CTS1_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RXD, TXD */ + 67, 66, +}; +static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, +}; +static const unsigned int scif1_clk_c_pins[] = { + /* SCK */ + 86, +}; +static const unsigned int scif1_clk_c_mux[] = { + SCK1_C_MARK, +}; +static const unsigned int scif1_ctrl_c_pins[] = { + /* RTS, CTS */ + 69, 68, +}; +static const unsigned int scif1_ctrl_c_mux[] = { + RTS1_C_TANS_C_MARK, CTS1_C_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RXD, TXD */ + 106, 105, +}; +static const unsigned int scif2_data_mux[] = { + RX2_MARK, TX2_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + 107, +}; +static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RXD, TXD */ + 120, 119, +}; +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; +static const unsigned int scif2_clk_b_pins[] = { + /* SCK */ + 118, +}; +static const unsigned int scif2_clk_b_mux[] = { + SCK2_B_MARK, +}; +static const unsigned int scif2_data_c_pins[] = { + /* RXD, TXD */ + 33, 31, +}; +static const unsigned int scif2_data_c_mux[] = { + RX2_C_MARK, TX2_C_MARK, +}; +static const unsigned int scif2_clk_c_pins[] = { + /* SCK */ + 32, +}; +static const unsigned int scif2_clk_c_mux[] = { + SCK2_C_MARK, +}; +static const unsigned int scif2_data_d_pins[] = { + /* RXD, TXD */ + 64, 62, +}; +static const unsigned int scif2_data_d_mux[] = { + RX2_D_MARK, TX2_D_MARK, +}; +static const unsigned int scif2_clk_d_pins[] = { + /* SCK */ + 63, +}; +static const unsigned int scif2_clk_d_mux[] = { + SCK2_D_MARK, +}; +static const unsigned int scif2_data_e_pins[] = { + /* RXD, TXD */ + 20, 19, +}; +static const unsigned int scif2_data_e_mux[] = { + RX2_E_MARK, TX2_E_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RXD, TXD */ + 137, 136, +}; +static const unsigned int scif3_data_mux[] = { + RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + 135, +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; + +static const unsigned int scif3_data_b_pins[] = { + /* RXD, TXD */ + 64, 62, +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, +}; +static const unsigned int scif3_data_c_pins[] = { + /* RXD, TXD */ + 15, 12, +}; +static const unsigned int scif3_data_c_mux[] = { + RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, +}; +static const unsigned int scif3_data_d_pins[] = { + /* RXD, TXD */ + 30, 29, +}; +static const unsigned int scif3_data_d_mux[] = { + RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, +}; +static const unsigned int scif3_data_e_pins[] = { + /* RXD, TXD */ + 35, 34, +}; +static const unsigned int scif3_data_e_mux[] = { + RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, +}; +static const unsigned int scif3_clk_e_pins[] = { + /* SCK */ + 42, +}; +static const unsigned int scif3_clk_e_mux[] = { + SCK3_E_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RXD, TXD */ + 123, 122, +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK */ + 121, +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RXD, TXD */ + 111, 110, +}; +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; +static const unsigned int scif4_clk_b_pins[] = { + /* SCK */ + 112, +}; +static const unsigned int scif4_clk_b_mux[] = { + SCK4_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RXD, TXD */ + 22, 21, +}; +static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, +}; +static const unsigned int scif4_data_d_pins[] = { + /* RXD, TXD */ + 69, 68, +}; +static const unsigned int scif4_data_d_mux[] = { + RX4_D_MARK, TX4_D_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_pins[] = { + /* RXD, TXD */ + 51, 50, +}; +static const unsigned int scif5_data_mux[] = { + RX5_MARK, TX5_MARK, +}; +static const unsigned int scif5_clk_pins[] = { + /* SCK */ + 43, +}; +static const unsigned int scif5_clk_mux[] = { + SCK5_MARK, +}; +static const unsigned int scif5_data_b_pins[] = { + /* RXD, TXD */ + 18, 11, +}; +static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, +}; +static const unsigned int scif5_clk_b_pins[] = { + /* SCK */ + 19, +}; +static const unsigned int scif5_clk_b_mux[] = { + SCK5_B_MARK, +}; +static const unsigned int scif5_data_c_pins[] = { + /* RXD, TXD */ + 24, 23, +}; +static const unsigned int scif5_data_c_mux[] = { + RX5_C_MARK, TX5_C_MARK, +}; +static const unsigned int scif5_clk_c_pins[] = { + /* SCK */ + 28, +}; +static const unsigned int scif5_clk_c_mux[] = { + SCK5_C_MARK, +}; +static const unsigned int scif5_data_d_pins[] = { + /* RXD, TXD */ + 8, 6, +}; +static const unsigned int scif5_data_d_mux[] = { + RX5_D_MARK, TX5_D_MARK, +}; +static const unsigned int scif5_clk_d_pins[] = { + /* SCK */ + 7, +}; +static const unsigned int scif5_clk_d_mux[] = { + SCK5_D_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -1804,6 +2168,57 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc1_data4), SH_PFC_PIN_GROUP(mmc1_data8), SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_clk_b), + SH_PFC_PIN_GROUP(scif0_ctrl_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_clk_c), + SH_PFC_PIN_GROUP(scif0_ctrl_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_clk_d), + SH_PFC_PIN_GROUP(scif0_ctrl_d), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_ctrl_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif1_ctrl_c), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_clk_c), + SH_PFC_PIN_GROUP(scif2_data_d), + SH_PFC_PIN_GROUP(scif2_clk_d), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif3_data_e), + SH_PFC_PIN_GROUP(scif3_clk_e), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_data_d), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_clk), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), + SH_PFC_PIN_GROUP(scif5_data_c), + SH_PFC_PIN_GROUP(scif5_clk_c), + SH_PFC_PIN_GROUP(scif5_data_d), + SH_PFC_PIN_GROUP(scif5_clk_d), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -1861,6 +2276,75 @@ static const char * const mmc1_groups[] = { "mmc1_ctrl", }; +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", + "scif0_data_b", + "scif0_clk_b", + "scif0_ctrl_b", + "scif0_data_c", + "scif0_clk_c", + "scif0_ctrl_c", + "scif0_data_d", + "scif0_clk_d", + "scif0_ctrl_d", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", + "scif1_clk_b", + "scif1_ctrl_b", + "scif1_data_c", + "scif1_clk_c", + "scif1_ctrl_c", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_clk", + "scif2_data_b", + "scif2_clk_b", + "scif2_data_c", + "scif2_clk_c", + "scif2_data_d", + "scif2_clk_d", + "scif2_data_e", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_data_b", + "scif3_data_c", + "scif3_data_d", + "scif3_data_e", + "scif3_clk_e", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_data_b", + "scif4_clk_b", + "scif4_data_c", + "scif4_data_d", +}; + +static const char * const scif5_groups[] = { + "scif5_data", + "scif5_clk", + "scif5_data_b", + "scif5_clk_b", + "scif5_data_c", + "scif5_clk_c", + "scif5_data_d", + "scif5_clk_d", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -1902,6 +2386,12 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), }; #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) From f516238737e1412613aee493961f352977666bbd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 19:04:43 +0100 Subject: [PATCH 132/307] sh-pfc: r8a7779: Add HSPI pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 79 +++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index a01adea444e1..361b16240887 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1575,6 +1575,58 @@ static const unsigned int du1_cde_pins[] = { static const unsigned int du1_cde_mux[] = { DU1_CDE_MARK }; +/* - HSPI0 ------------------------------------------------------------------ */ +static const unsigned int hspi0_pins[] = { + /* CLK, CS, RX, TX */ + 150, 151, 153, 152, +}; +static const unsigned int hspi0_mux[] = { + HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, +}; +/* - HSPI1 ------------------------------------------------------------------ */ +static const unsigned int hspi1_pins[] = { + /* CLK, CS, RX, TX */ + 63, 58, 64, 62, +}; +static const unsigned int hspi1_mux[] = { + HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, +}; +static const unsigned int hspi1_b_pins[] = { + /* CLK, CS, RX, TX */ + 90, 91, 93, 92, +}; +static const unsigned int hspi1_b_mux[] = { + HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, +}; +static const unsigned int hspi1_c_pins[] = { + /* CLK, CS, RX, TX */ + 141, 142, 144, 143, +}; +static const unsigned int hspi1_c_mux[] = { + HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, +}; +static const unsigned int hspi1_d_pins[] = { + /* CLK, CS, RX, TX */ + 101, 102, 104, 103, +}; +static const unsigned int hspi1_d_mux[] = { + HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, +}; +/* - HSPI2 ------------------------------------------------------------------ */ +static const unsigned int hspi2_pins[] = { + /* CLK, CS, RX, TX */ + 9, 10, 11, 14, +}; +static const unsigned int hspi2_mux[] = { + HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, +}; +static const unsigned int hspi2_b_pins[] = { + /* CLK, CS, RX, TX */ + 7, 13, 8, 6, +}; +static const unsigned int hspi2_b_mux[] = { + HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, +}; /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ @@ -1605,7 +1657,6 @@ static const unsigned int mmc0_ctrl_pins[] = { static const unsigned int mmc0_ctrl_mux[] = { MMC0_CMD_MARK, MMC0_CLK_MARK, }; - static const unsigned int mmc1_data1_pins[] = { /* D[0] */ 72, @@ -2160,6 +2211,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du1_sync_1), SH_PFC_PIN_GROUP(du1_oddf), SH_PFC_PIN_GROUP(du1_cde), + SH_PFC_PIN_GROUP(hspi0), + SH_PFC_PIN_GROUP(hspi1), + SH_PFC_PIN_GROUP(hspi1_b), + SH_PFC_PIN_GROUP(hspi1_c), + SH_PFC_PIN_GROUP(hspi1_d), + SH_PFC_PIN_GROUP(hspi2), + SH_PFC_PIN_GROUP(hspi2_b), SH_PFC_PIN_GROUP(mmc0_data1), SH_PFC_PIN_GROUP(mmc0_data4), SH_PFC_PIN_GROUP(mmc0_data8), @@ -2262,6 +2320,22 @@ static const char * const du1_groups[] = { "du1_cde", }; +static const char * const hspi0_groups[] = { + "hspi0", +}; + +static const char * const hspi1_groups[] = { + "hspi1", + "hspi1_b", + "hspi1_c", + "hspi1_d", +}; + +static const char * const hspi2_groups[] = { + "hspi2", + "hspi2_b", +}; + static const char * const mmc0_groups[] = { "mmc0_data1", "mmc0_data4", @@ -2380,6 +2454,9 @@ static const char * const sdhi3_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(hspi0), + SH_PFC_FUNCTION(hspi1), + SH_PFC_FUNCTION(hspi2), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), SH_PFC_FUNCTION(sdhi0), From 0f6e2e0e4e3cf5899c9acf03884991bb67301132 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:36:36 +0100 Subject: [PATCH 133/307] sh-pfc: r8a7779: Add USB0 and USB1 PENC pinmux support The USB0 and USB1 PENC functions were missing. Add them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 361b16240887..946572bcdaac 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -429,7 +429,8 @@ enum { A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, - USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, + USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK, + SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, SCIF_CLK_MARK, TCLK0_C_MARK, EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, @@ -640,6 +641,9 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(A18_MARK, FN_A18), PINMUX_DATA(A19_MARK, FN_A19), + PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0), + PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1), + PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP0_2_0, PWM1), From 97d40c4224172451f666febdd865c24b1c3c3fe5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:38:51 +0100 Subject: [PATCH 134/307] sh-pfc: r8a7779: Add USB pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 946572bcdaac..6043d2c8dd8d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2198,6 +2198,30 @@ static const unsigned int sdhi3_wp_pins[] = { static const unsigned int sdhi3_wp_mux[] = { SD3_WP_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* OVC */ + 150, 154, +}; +static const unsigned int usb0_mux[] = { + USB_OVC0_MARK, USB_PENC0_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + /* OVC */ + 152, 155, +}; +static const unsigned int usb1_mux[] = { + USB_OVC1_MARK, USB_PENC1_MARK, +}; +/* - USB2 ------------------------------------------------------------------- */ +static const unsigned int usb2_pins[] = { + /* OVC, PENC */ + 125, 156, +}; +static const unsigned int usb2_mux[] = { + USB_OVC2_MARK, USB_PENC2_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_rgb666), @@ -2301,6 +2325,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), }; static const char * const du0_groups[] = { @@ -2455,6 +2482,18 @@ static const char * const sdhi3_groups[] = { "sdhi3_wp", }; +static const char * const usb0_groups[] = { + "usb0", +}; + +static const char * const usb1_groups[] = { + "usb1", +}; + +static const char * const usb2_groups[] = { + "usb2", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), @@ -2473,6 +2512,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), }; #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) From f27f81f2c04e1cd382a3c3bb072c708a895d83bb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:38:51 +0100 Subject: [PATCH 135/307] sh-pfc: r8a7779: Add LBSC pin groups and functions Only the CS pins and functions are currently handled. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 6043d2c8dd8d..3f671439ae6e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1631,6 +1631,63 @@ static const unsigned int hspi2_b_pins[] = { static const unsigned int hspi2_b_mux[] = { HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, }; +/* - LSBC ------------------------------------------------------------------- */ +static const unsigned int lbsc_cs0_pins[] = { + /* CS */ + 13, +}; +static const unsigned int lbsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int lbsc_cs1_pins[] = { + /* CS */ + 14, +}; +static const unsigned int lbsc_cs1_mux[] = { + CS1_A26_MARK, +}; +static const unsigned int lbsc_ex_cs0_pins[] = { + /* CS */ + 15, +}; +static const unsigned int lbsc_ex_cs0_mux[] = { + EX_CS0_MARK, +}; +static const unsigned int lbsc_ex_cs1_pins[] = { + /* CS */ + 16, +}; +static const unsigned int lbsc_ex_cs1_mux[] = { + EX_CS1_MARK, +}; +static const unsigned int lbsc_ex_cs2_pins[] = { + /* CS */ + 17, +}; +static const unsigned int lbsc_ex_cs2_mux[] = { + EX_CS2_MARK, +}; +static const unsigned int lbsc_ex_cs3_pins[] = { + /* CS */ + 18, +}; +static const unsigned int lbsc_ex_cs3_mux[] = { + EX_CS3_MARK, +}; +static const unsigned int lbsc_ex_cs4_pins[] = { + /* CS */ + 19, +}; +static const unsigned int lbsc_ex_cs4_mux[] = { + EX_CS4_MARK, +}; +static const unsigned int lbsc_ex_cs5_pins[] = { + /* CS */ + 20, +}; +static const unsigned int lbsc_ex_cs5_mux[] = { + EX_CS5_MARK, +}; /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ @@ -2246,6 +2303,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hspi1_d), SH_PFC_PIN_GROUP(hspi2), SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(lbsc_cs0), + SH_PFC_PIN_GROUP(lbsc_cs1), + SH_PFC_PIN_GROUP(lbsc_ex_cs0), + SH_PFC_PIN_GROUP(lbsc_ex_cs1), + SH_PFC_PIN_GROUP(lbsc_ex_cs2), + SH_PFC_PIN_GROUP(lbsc_ex_cs3), + SH_PFC_PIN_GROUP(lbsc_ex_cs4), + SH_PFC_PIN_GROUP(lbsc_ex_cs5), SH_PFC_PIN_GROUP(mmc0_data1), SH_PFC_PIN_GROUP(mmc0_data4), SH_PFC_PIN_GROUP(mmc0_data8), @@ -2367,6 +2432,17 @@ static const char * const hspi2_groups[] = { "hspi2_b", }; +static const char * const lbsc_groups[] = { + "lbsc_cs0", + "lbsc_cs1", + "lbsc_ex_cs0", + "lbsc_ex_cs1", + "lbsc_ex_cs2", + "lbsc_ex_cs3", + "lbsc_ex_cs4", + "lbsc_ex_cs5", +}; + static const char * const mmc0_groups[] = { "mmc0_data1", "mmc0_data4", @@ -2500,6 +2576,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hspi0), SH_PFC_FUNCTION(hspi1), SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), SH_PFC_FUNCTION(sdhi0), From fd9e7feb9ae96346724f35fd20eb2009743fb868 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:38:51 +0100 Subject: [PATCH 136/307] sh-pfc: r8a7779: Add INTC pin groups and functions Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 3f671439ae6e..5b498ffaef03 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1631,6 +1631,63 @@ static const unsigned int hspi2_b_pins[] = { static const unsigned int hspi2_b_mux[] = { HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, }; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ */ + 78, +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq0_b_pins[] = { + /* IRQ */ + 141, +}; +static const unsigned int intc_irq0_b_mux[] = { + IRQ0_B_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ */ + 79, +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq1_b_pins[] = { + /* IRQ */ + 142, +}; +static const unsigned int intc_irq1_b_mux[] = { + IRQ1_B_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ */ + 88, +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq2_b_pins[] = { + /* IRQ */ + 143, +}; +static const unsigned int intc_irq2_b_mux[] = { + IRQ2_B_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ */ + 89, +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_irq3_b_pins[] = { + /* IRQ */ + 144, +}; +static const unsigned int intc_irq3_b_mux[] = { + IRQ3_B_MARK, +}; /* - LSBC ------------------------------------------------------------------- */ static const unsigned int lbsc_cs0_pins[] = { /* CS */ @@ -2303,6 +2360,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hspi1_d), SH_PFC_PIN_GROUP(hspi2), SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq0_b), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq1_b), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq2_b), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(intc_irq3_b), SH_PFC_PIN_GROUP(lbsc_cs0), SH_PFC_PIN_GROUP(lbsc_cs1), SH_PFC_PIN_GROUP(lbsc_ex_cs0), @@ -2432,6 +2497,17 @@ static const char * const hspi2_groups[] = { "hspi2_b", }; +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq0_b", + "intc_irq1", + "intc_irq1_b", + "intc_irq2", + "intc_irq2_b", + "intc_irq3", + "intc_irq4_b", +}; + static const char * const lbsc_groups[] = { "lbsc_cs0", "lbsc_cs1", @@ -2576,6 +2652,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hspi0), SH_PFC_FUNCTION(hspi1), SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), From b5012cd33b826eb7659ff66c829535ff38ca54dd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 137/307] ARM: shmobile: ag5evm: Register pinctrl mappings for SCIF Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-ag5evm.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index a4ac46a89b27..5b8dcdc3c2af 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -550,6 +551,14 @@ static struct platform_device *ag5evm_devices[] __initdata = { &sdhi1_device, }; +static const struct pinctrl_map ag5evm_pinctrl_map[] = { + /* SCIFA2 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", + "scifa2_data_0", "scifa2"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", + "scifa2_ctrl_0", "scifa2"), +}; + static void __init ag5evm_init(void) { regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, @@ -558,14 +567,10 @@ static void __init ag5evm_init(void) ARRAY_SIZE(fixed2v8_power_consumers), 3300000); regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + pinctrl_register_mappings(ag5evm_pinctrl_map, + ARRAY_SIZE(ag5evm_pinctrl_map)); sh73a0_pinmux_init(); - /* enable SCIFA2 */ - gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); - gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); - gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); - gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); - /* enable KEYSC */ gpio_request(GPIO_FN_KEYIN0_PU, NULL); gpio_request(GPIO_FN_KEYIN1_PU, NULL); From 63d6fc90f35c388c6f0c147e58140fde099ee449 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 138/307] ARM: shmobile: ag5evm: Register pinctrl mappings for I2C Replace the GPIO-based I2C pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-ag5evm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index 5b8dcdc3c2af..e19dade83a1f 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -552,6 +552,11 @@ static struct platform_device *ag5evm_devices[] __initdata = { }; static const struct pinctrl_map ag5evm_pinctrl_map[] = { + /* I2C2 & I2C3 */ + PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0", + "i2c2_0", "i2c2"), + PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", + "i2c3_0", "i2c3"), /* SCIFA2 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", "scifa2_data_0", "scifa2"), @@ -591,12 +596,6 @@ static void __init ag5evm_init(void) gpio_request(GPIO_FN_KEYOUT8, NULL); gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL); - /* enable I2C channel 2 and 3 */ - gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); - gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); - gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL); - gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL); - /* enable MMCIF */ gpio_request(GPIO_FN_MMCCLK0, NULL); gpio_request(GPIO_FN_MMCCMD0_PU, NULL); From 9723b7934920091b2a2515f22d433e4efea1d2fb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 139/307] ARM: shmobile: ag5evm: Register pinctrl mappings for FSI Replace the GPIO-based FSI pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-ag5evm.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index e19dade83a1f..178bfd12de9f 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -552,6 +552,15 @@ static struct platform_device *ag5evm_devices[] __initdata = { }; static const struct pinctrl_map ag5evm_pinctrl_map[] = { + /* FSIA */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_mclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_sclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_data_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_data_out", "fsia"), /* I2C2 & I2C3 */ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0", "i2c2_0", "i2c2"), @@ -613,13 +622,6 @@ static void __init ag5evm_init(void) gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ - /* FSI A */ - gpio_request(GPIO_FN_FSIACK, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAISLD, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); - /* IrDA */ gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL); gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL); From a1fedc46c897c58e62d40d03557c25279f666227 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:52:31 +0100 Subject: [PATCH 140/307] ARM: shmobile: ag5evm: Register pinctrl mappings for SDHI and MMCIF Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-ag5evm.c | 57 ++++++++++++++------------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index 178bfd12de9f..987b9b6f5f5d 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -551,6 +552,10 @@ static struct platform_device *ag5evm_devices[] __initdata = { &sdhi1_device, }; +static unsigned long pin_pullup_conf[] = { + PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +}; + static const struct pinctrl_map ag5evm_pinctrl_map[] = { /* FSIA */ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", @@ -566,11 +571,36 @@ static const struct pinctrl_map ag5evm_pinctrl_map[] = { "i2c2_0", "i2c2"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", "i2c3_0", "i2c3"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_ctrl_0", "mmc0"), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "PORT279", pin_pullup_conf), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", pin_pullup_conf), /* SCIFA2 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", "scifa2_data_0", "scifa2"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", "scifa2_ctrl_0", "scifa2"), + /* SDHI0 (CN15 [SD I/F]) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_wp", "sdhi0"), + /* SDHI1 (CN4 [WLAN I/F]) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "sdhi1_data4", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "sdhi1_ctrl", "sdhi1"), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "sdhi1_data4", pin_pullup_conf), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "PORT263", pin_pullup_conf), }; static void __init ag5evm_init(void) @@ -606,16 +636,6 @@ static void __init ag5evm_init(void) gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL); /* enable MMCIF */ - gpio_request(GPIO_FN_MMCCLK0, NULL); - gpio_request(GPIO_FN_MMCCMD0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_1_PU, NULL); - gpio_request(GPIO_FN_MMCD0_2_PU, NULL); - gpio_request(GPIO_FN_MMCD0_3_PU, NULL); - gpio_request(GPIO_FN_MMCD0_4_PU, NULL); - gpio_request(GPIO_FN_MMCD0_5_PU, NULL); - gpio_request(GPIO_FN_MMCD0_6_PU, NULL); - gpio_request(GPIO_FN_MMCD0_7_PU, NULL); gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ /* enable SMSC911X */ @@ -637,23 +657,6 @@ static void __init ag5evm_init(void) gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ lcd_backlight_set_brightness(0); - /* enable SDHI0 on CN15 [SD I/F] */ - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); - - /* enable SDHI1 on CN4 [WLAN I/F] */ - gpio_request(GPIO_FN_SDHICLK1, NULL); - gpio_request(GPIO_FN_SDHICMD1_PU, NULL); - gpio_request(GPIO_FN_SDHID1_3_PU, NULL); - gpio_request(GPIO_FN_SDHID1_2_PU, NULL); - gpio_request(GPIO_FN_SDHID1_1_PU, NULL); - gpio_request(GPIO_FN_SDHID1_0_PU, NULL); - #ifdef CONFIG_CACHE_L2X0 /* Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff); From 7e6455e122c56935d8eb5474b611c90287c149c9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:52:31 +0100 Subject: [PATCH 141/307] ARM: shmobile: ag5evm: Register pinctrl mappings for KEYSC Replace the GPIO-based KEYSC pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-ag5evm.c | 37 ++++++++++++--------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index 987b9b6f5f5d..22b9655a68ef 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -571,6 +571,23 @@ static const struct pinctrl_map ag5evm_pinctrl_map[] = { "i2c2_0", "i2c2"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", "i2c3_0", "i2c3"), + /* KEYSC */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_in8", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out04", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out5", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out6_0", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out7_0", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out8_0", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out9_2", "keysc"), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_in8", pin_pullup_conf), /* MMCIF */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_data8_0", "mmc0"), @@ -615,26 +632,6 @@ static void __init ag5evm_init(void) ARRAY_SIZE(ag5evm_pinctrl_map)); sh73a0_pinmux_init(); - /* enable KEYSC */ - gpio_request(GPIO_FN_KEYIN0_PU, NULL); - gpio_request(GPIO_FN_KEYIN1_PU, NULL); - gpio_request(GPIO_FN_KEYIN2_PU, NULL); - gpio_request(GPIO_FN_KEYIN3_PU, NULL); - gpio_request(GPIO_FN_KEYIN4_PU, NULL); - gpio_request(GPIO_FN_KEYIN5_PU, NULL); - gpio_request(GPIO_FN_KEYIN6_PU, NULL); - gpio_request(GPIO_FN_KEYIN7_PU, NULL); - gpio_request(GPIO_FN_KEYOUT0, NULL); - gpio_request(GPIO_FN_KEYOUT1, NULL); - gpio_request(GPIO_FN_KEYOUT2, NULL); - gpio_request(GPIO_FN_KEYOUT3, NULL); - gpio_request(GPIO_FN_KEYOUT4, NULL); - gpio_request(GPIO_FN_KEYOUT5, NULL); - gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); - gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); - gpio_request(GPIO_FN_KEYOUT8, NULL); - gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL); - /* enable MMCIF */ gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ From 2eaa0747f8162e741ed0609b6520d25fc2951864 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:52:31 +0100 Subject: [PATCH 142/307] ARM: shmobile: ag5evm: Register pinctrl mappings for IrDA Replace the GPIO-based IrDA pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-ag5evm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index 22b9655a68ef..c7540710906f 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -571,6 +571,9 @@ static const struct pinctrl_map ag5evm_pinctrl_map[] = { "i2c2_0", "i2c2"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", "i2c3_0", "i2c3"), + /* IrDA */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0", + "irda_0", "irda"), /* KEYSC */ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", "keysc_in8", "keysc"), @@ -639,11 +642,6 @@ static void __init ag5evm_init(void) gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ - /* IrDA */ - gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL); - gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL); - gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL); - /* LCD panel */ gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ mdelay(1); From e6bd960e93491b29831711151ccc850610d08393 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:21:27 +0100 Subject: [PATCH 143/307] ARM: shmobile: ap4evb: Register pinctrl mappings for SDHI and MMCIF Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl mappings Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-ap4evb.c | 55 ++++++++++++--------------- 1 file changed, 25 insertions(+), 30 deletions(-) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 0a2b6e435b65..45f78cadec1d 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = { }; +static const struct pinctrl_map ap4evb_pinctrl_map[] = { + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_ctrl_0", "mmc0"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_cd", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_wp", "sdhi0"), + /* SDHI1 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", + "sdhi1_data4", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", + "sdhi1_ctrl", "sdhi1"), +}; + #define GPIO_PORT9CR IOMEM(0xE6051009) #define GPIO_PORT10CR IOMEM(0xE605100A) #define USCCR1 IOMEM(0xE6058144) @@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void) /* External clock source */ clk_set_rate(&sh7372_dv_clki_clk, 27000000); + pinctrl_register_mappings(ap4evb_pinctrl_map, + ARRAY_SIZE(ap4evb_pinctrl_map)); sh7372_pinmux_init(); /* enable SCIFA0 */ @@ -1126,36 +1151,6 @@ static void __init ap4evb_init(void) gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL); gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL); - /* SDHI0 */ - gpio_request(GPIO_FN_SDHICD0, NULL); - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); - - /* SDHI1 */ - gpio_request(GPIO_FN_SDHICMD1, NULL); - gpio_request(GPIO_FN_SDHICLK1, NULL); - gpio_request(GPIO_FN_SDHID1_3, NULL); - gpio_request(GPIO_FN_SDHID1_2, NULL); - gpio_request(GPIO_FN_SDHID1_1, NULL); - gpio_request(GPIO_FN_SDHID1_0, NULL); - - /* MMCIF */ - gpio_request(GPIO_FN_MMCD0_0, NULL); - gpio_request(GPIO_FN_MMCD0_1, NULL); - gpio_request(GPIO_FN_MMCD0_2, NULL); - gpio_request(GPIO_FN_MMCD0_3, NULL); - gpio_request(GPIO_FN_MMCD0_4, NULL); - gpio_request(GPIO_FN_MMCD0_5, NULL); - gpio_request(GPIO_FN_MMCD0_6, NULL); - gpio_request(GPIO_FN_MMCD0_7, NULL); - gpio_request(GPIO_FN_MMCCMD0, NULL); - gpio_request(GPIO_FN_MMCCLK0, NULL); - /* USB enable */ gpio_request(GPIO_FN_VBUS0_1, NULL); gpio_request(GPIO_FN_IDIN_1_18, NULL); From 79f7182e410ba2bf0d4d8eda94feb2873215eb54 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 144/307] ARM: shmobile: armadillo800eva: Register pinctrl mappings for LCDC0 Replace the GPIO-based LCDC0 pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- .../arm/mach-shmobile/board-armadillo800eva.c | 42 ++++++------------- 1 file changed, 13 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 92d799138835..aa812cf7aa4e 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -914,6 +915,16 @@ static struct platform_device *eva_devices[] __initdata = { &i2c_gpio_device, }; +static const struct pinctrl_map eva_pinctrl_map[] = { + /* LCD0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_data24_0", "lcd0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_lclk_1", "lcd0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_sync", "lcd0"), +}; + static void __init eva_clock_init(void) { struct clk *system = clk_get(NULL, "system_clk"); @@ -961,6 +972,8 @@ static void __init eva_init(void) regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); + r8a7740_pinmux_init(); r8a7740_meram_workaround(); @@ -970,35 +983,6 @@ static void __init eva_init(void) /* LCDC0 */ gpio_request(GPIO_FN_LCDC0_SELECT, NULL); - gpio_request(GPIO_FN_LCD0_D0, NULL); - gpio_request(GPIO_FN_LCD0_D1, NULL); - gpio_request(GPIO_FN_LCD0_D2, NULL); - gpio_request(GPIO_FN_LCD0_D3, NULL); - gpio_request(GPIO_FN_LCD0_D4, NULL); - gpio_request(GPIO_FN_LCD0_D5, NULL); - gpio_request(GPIO_FN_LCD0_D6, NULL); - gpio_request(GPIO_FN_LCD0_D7, NULL); - gpio_request(GPIO_FN_LCD0_D8, NULL); - gpio_request(GPIO_FN_LCD0_D9, NULL); - gpio_request(GPIO_FN_LCD0_D10, NULL); - gpio_request(GPIO_FN_LCD0_D11, NULL); - gpio_request(GPIO_FN_LCD0_D12, NULL); - gpio_request(GPIO_FN_LCD0_D13, NULL); - gpio_request(GPIO_FN_LCD0_D14, NULL); - gpio_request(GPIO_FN_LCD0_D15, NULL); - gpio_request(GPIO_FN_LCD0_D16, NULL); - gpio_request(GPIO_FN_LCD0_D17, NULL); - gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL); - gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL); - gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL); - gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL); - gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL); - gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL); - gpio_request(GPIO_FN_LCD0_DCK, NULL); - gpio_request(GPIO_FN_LCD0_VSYN, NULL); - gpio_request(GPIO_FN_LCD0_HSYN, NULL); - gpio_request(GPIO_FN_LCD0_DISP, NULL); - gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ From c9e3a32f31dbac965ee492d7e768a40bc2b44dcd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:34:23 +0100 Subject: [PATCH 145/307] ARM: shmobile: armadillo800eva: Register pinctrl mappings for SDHI and MMCIF Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- .../arm/mach-shmobile/board-armadillo800eva.c | 58 ++++++++----------- 1 file changed, 25 insertions(+), 33 deletions(-) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index aa812cf7aa4e..04eff93df793 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -657,6 +657,17 @@ static struct platform_device sdhi1_device = { .resource = sdhi1_resources, }; +static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = { + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", + "sdhi1_data4", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", + "sdhi1_ctrl", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", + "sdhi1_cd", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", + "sdhi1_wp", "sdhi1"), +}; + /* MMCIF */ static struct sh_mmcif_plat_data sh_mmcif_plat = { .sup_pclk = 0, @@ -923,6 +934,18 @@ static const struct pinctrl_map eva_pinctrl_map[] = { "lcd0_lclk_1", "lcd0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", "lcd0_sync", "lcd0"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", + "mmc0_data8_1", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", + "mmc0_ctrl_1", "mmc0"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", + "sdhi0_wp", "sdhi0"), }; static void __init eva_clock_init(void) @@ -1036,37 +1059,12 @@ static void __init eva_init(void) } /* SDHI0 */ - gpio_request(GPIO_FN_SDHI0_CMD, NULL); - gpio_request(GPIO_FN_SDHI0_CLK, NULL); - gpio_request(GPIO_FN_SDHI0_D0, NULL); - gpio_request(GPIO_FN_SDHI0_D1, NULL); - gpio_request(GPIO_FN_SDHI0_D2, NULL); - gpio_request(GPIO_FN_SDHI0_D3, NULL); - gpio_request(GPIO_FN_SDHI0_WP, NULL); - gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */ gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */ gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */ /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */ - /* - * MMCIF - * - * Here doesn't care SW1.4 status, - * since CON2 is not mounted. - */ - gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL); - gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL); - gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL); - gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL); - gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL); - gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL); - gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL); - gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL); - gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL); - gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL); - /* CEU0 */ gpio_request(GPIO_FN_VIO0_D7, NULL); gpio_request(GPIO_FN_VIO0_D6, NULL); @@ -1124,14 +1122,8 @@ static void __init eva_init(void) /* CON14 enable */ } else { /* CON8 (SDHI1) enable */ - gpio_request(GPIO_FN_SDHI1_CLK, NULL); - gpio_request(GPIO_FN_SDHI1_CMD, NULL); - gpio_request(GPIO_FN_SDHI1_D0, NULL); - gpio_request(GPIO_FN_SDHI1_D1, NULL); - gpio_request(GPIO_FN_SDHI1_D2, NULL); - gpio_request(GPIO_FN_SDHI1_D3, NULL); - gpio_request(GPIO_FN_SDHI1_CD, NULL); - gpio_request(GPIO_FN_SDHI1_WP, NULL); + pinctrl_register_mappings(eva_sdhi1_pinctrl_map, + ARRAY_SIZE(eva_sdhi1_pinctrl_map)); /* SDSLOT2_PON */ gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL); From 1e47ff221d0ad1310eec0e57a55ccbb1150b9a2d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 146/307] ARM: shmobile: bonito: Register pinctrl mappings for LCDC0 Replace the GPIO-based LCDC0 pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-bonito.c | 44 +++++++++------------------ 1 file changed, 14 insertions(+), 30 deletions(-) diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c index d363526450ac..70d992c540ae 100644 --- a/arch/arm/mach-shmobile/board-bonito.c +++ b/arch/arm/mach-shmobile/board-bonito.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = { }, }; +static const struct pinctrl_map lcdc0_pinctrl_map[] = { + /* LCD0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_data24_1", "lcd0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_lclk_1", "lcd0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", + "lcd0_sync", "lcd0"), +}; + /* * SMSC 9221 */ @@ -430,36 +441,9 @@ static void __init bonito_init(void) */ if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */ BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ - gpio_request(GPIO_FN_LCDC0_SELECT, NULL); - gpio_request(GPIO_FN_LCD0_D0, NULL); - gpio_request(GPIO_FN_LCD0_D1, NULL); - gpio_request(GPIO_FN_LCD0_D2, NULL); - gpio_request(GPIO_FN_LCD0_D3, NULL); - gpio_request(GPIO_FN_LCD0_D4, NULL); - gpio_request(GPIO_FN_LCD0_D5, NULL); - gpio_request(GPIO_FN_LCD0_D6, NULL); - gpio_request(GPIO_FN_LCD0_D7, NULL); - gpio_request(GPIO_FN_LCD0_D8, NULL); - gpio_request(GPIO_FN_LCD0_D9, NULL); - gpio_request(GPIO_FN_LCD0_D10, NULL); - gpio_request(GPIO_FN_LCD0_D11, NULL); - gpio_request(GPIO_FN_LCD0_D12, NULL); - gpio_request(GPIO_FN_LCD0_D13, NULL); - gpio_request(GPIO_FN_LCD0_D14, NULL); - gpio_request(GPIO_FN_LCD0_D15, NULL); - gpio_request(GPIO_FN_LCD0_D16, NULL); - gpio_request(GPIO_FN_LCD0_D17, NULL); - gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL); - gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL); - gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL); - gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL); - gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL); - gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL); - gpio_request(GPIO_FN_LCD0_DCK, NULL); - gpio_request(GPIO_FN_LCD0_VSYN, NULL); - gpio_request(GPIO_FN_LCD0_HSYN, NULL); - gpio_request(GPIO_FN_LCD0_DISP, NULL); - gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); + pinctrl_register_mappings(lcdc0_pinctrl_map, + ARRAY_SIZE(lcdc0_pinctrl_map)); + gpio_request(GPIO_FN_LCDC0_SELECT, NULL); gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ From ff11e874093814e664c9cd0e4752924bb4d2ac84 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 147/307] ARM: shmobile: kota2: Register pinctrl mappings for SCIF Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kota2.c | 42 +++++++++++++++------------- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c index b6f051573b4a..09c4f000754e 100644 --- a/arch/arm/mach-shmobile/board-kota2.c +++ b/arch/arm/mach-shmobile/board-kota2.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -433,6 +434,26 @@ static struct platform_device *kota2_devices[] __initdata = { &sdhi1_device, }; +static const struct pinctrl_map kota2_pinctrl_map[] = { + /* SCIFA2 (UART2) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", + "scifa2_data_0", "scifa2"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", + "scifa2_ctrl_0", "scifa2"), + /* SCIFA4 (UART1) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", + "scifa4_data", "scifa4"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", + "scifa4_ctrl", "scifa4"), + /* SCIFB (BT) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", + "scifb_data_0", "scifb"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", + "scifb_clk_0", "scifb"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", + "scifb_ctrl_0", "scifb"), +}; + static void __init kota2_init(void) { regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, @@ -441,20 +462,10 @@ static void __init kota2_init(void) ARRAY_SIZE(fixed3v3_power_consumers), 3300000); regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + pinctrl_register_mappings(kota2_pinctrl_map, + ARRAY_SIZE(kota2_pinctrl_map)); sh73a0_pinmux_init(); - /* SCIFA2 (UART2) */ - gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); - gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); - gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); - gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); - - /* SCIFA4 (UART1) */ - gpio_request(GPIO_FN_SCIFA4_TXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); - gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); - /* SMSC911X */ gpio_request(GPIO_FN_D0_NAF0, NULL); gpio_request(GPIO_FN_D1_NAF1, NULL); @@ -518,13 +529,6 @@ static void __init kota2_init(void) gpio_request(GPIO_FN_SDHID0_1_PU, NULL); gpio_request(GPIO_FN_SDHID0_0_PU, NULL); - /* SCIFB (BT) */ - gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL); - gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL); - gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL); - gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL); - gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL); - /* SDHI1 (BCM4330) */ gpio_request(GPIO_FN_SDHICLK1, NULL); gpio_request(GPIO_FN_SDHICMD1_PU, NULL); From d1436d1991e443eea73f97217c6f9186eb506076 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:52:31 +0100 Subject: [PATCH 148/307] ARM: shmobile: kota2: Register pinctrl mappings for SDHI and MMCIF Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl mappings. Board code used the non-pulled-up version of the function GPIOs, but those are defined in the PFC driver as enabling the pull-ups anyway. Enable pull-ups on the MMCIF data and command pins through the pinconf API. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kota2.c | 63 ++++++++++++++++------------ 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c index 09c4f000754e..7fa71f5eeac1 100644 --- a/arch/arm/mach-shmobile/board-kota2.c +++ b/arch/arm/mach-shmobile/board-kota2.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -434,7 +435,20 @@ static struct platform_device *kota2_devices[] __initdata = { &sdhi1_device, }; +static unsigned long pin_pullup_conf[] = { + PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +}; + static const struct pinctrl_map kota2_pinctrl_map[] = { + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_ctrl_0", "mmc0"), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "PORT279", pin_pullup_conf), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", pin_pullup_conf), /* SCIFA2 (UART2) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", "scifa2_data_0", "scifa2"), @@ -452,6 +466,28 @@ static const struct pinctrl_map kota2_pinctrl_map[] = { "scifb_clk_0", "scifb"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", "scifb_ctrl_0", "scifb"), + /* SDHI0 (microSD) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_cd", "sdhi0"), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_data4", pin_pullup_conf), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "PORT256", pin_pullup_conf), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "PORT251", pin_pullup_conf), + /* SDHI1 (BCM4330) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "sdhi1_data4", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "sdhi1_ctrl", "sdhi1"), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "sdhi1_data4", pin_pullup_conf), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", + "PORT263", pin_pullup_conf), }; static void __init kota2_init(void) @@ -508,35 +544,8 @@ static void __init kota2_init(void) gpio_request(GPIO_FN_KEYOUT8, NULL); /* MMCIF */ - gpio_request(GPIO_FN_MMCCLK0, NULL); - gpio_request(GPIO_FN_MMCD0_0, NULL); - gpio_request(GPIO_FN_MMCD0_1, NULL); - gpio_request(GPIO_FN_MMCD0_2, NULL); - gpio_request(GPIO_FN_MMCD0_3, NULL); - gpio_request(GPIO_FN_MMCD0_4, NULL); - gpio_request(GPIO_FN_MMCD0_5, NULL); - gpio_request(GPIO_FN_MMCD0_6, NULL); - gpio_request(GPIO_FN_MMCD0_7, NULL); - gpio_request(GPIO_FN_MMCCMD0, NULL); gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ - /* SDHI0 (microSD) */ - gpio_request(GPIO_FN_SDHICD0_PU, NULL); - gpio_request(GPIO_FN_SDHICMD0_PU, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3_PU, NULL); - gpio_request(GPIO_FN_SDHID0_2_PU, NULL); - gpio_request(GPIO_FN_SDHID0_1_PU, NULL); - gpio_request(GPIO_FN_SDHID0_0_PU, NULL); - - /* SDHI1 (BCM4330) */ - gpio_request(GPIO_FN_SDHICLK1, NULL); - gpio_request(GPIO_FN_SDHICMD1_PU, NULL); - gpio_request(GPIO_FN_SDHID1_3_PU, NULL); - gpio_request(GPIO_FN_SDHID1_2_PU, NULL); - gpio_request(GPIO_FN_SDHID1_1_PU, NULL); - gpio_request(GPIO_FN_SDHID1_0_PU, NULL); - #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); From 67ee2fd7de181765bb59ce8ee3fb2002b7bff800 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:52:31 +0100 Subject: [PATCH 149/307] ARM: shmobile: kota2: Register pinctrl mappings for KEYSC Replace the GPIO-based KEYSC pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kota2.c | 34 ++++++++++++---------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c index 7fa71f5eeac1..3f3655702319 100644 --- a/arch/arm/mach-shmobile/board-kota2.c +++ b/arch/arm/mach-shmobile/board-kota2.c @@ -440,6 +440,21 @@ static unsigned long pin_pullup_conf[] = { }; static const struct pinctrl_map kota2_pinctrl_map[] = { + /* KEYSC */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_in8", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out04", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out5", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out6_0", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out7_0", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_out8_0", "keysc"), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", + "keysc_in8", pin_pullup_conf), /* MMCIF */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_data8_0", "mmc0"), @@ -524,25 +539,6 @@ static void __init kota2_init(void) gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ - /* KEYSC */ - gpio_request(GPIO_FN_KEYIN0_PU, NULL); - gpio_request(GPIO_FN_KEYIN1_PU, NULL); - gpio_request(GPIO_FN_KEYIN2_PU, NULL); - gpio_request(GPIO_FN_KEYIN3_PU, NULL); - gpio_request(GPIO_FN_KEYIN4_PU, NULL); - gpio_request(GPIO_FN_KEYIN5_PU, NULL); - gpio_request(GPIO_FN_KEYIN6_PU, NULL); - gpio_request(GPIO_FN_KEYIN7_PU, NULL); - gpio_request(GPIO_FN_KEYOUT0, NULL); - gpio_request(GPIO_FN_KEYOUT1, NULL); - gpio_request(GPIO_FN_KEYOUT2, NULL); - gpio_request(GPIO_FN_KEYOUT3, NULL); - gpio_request(GPIO_FN_KEYOUT4, NULL); - gpio_request(GPIO_FN_KEYOUT5, NULL); - gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); - gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); - gpio_request(GPIO_FN_KEYOUT8, NULL); - /* MMCIF */ gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ From b5ee0e101eaaf8e01cae1d7341037f687ceff868 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:52:31 +0100 Subject: [PATCH 150/307] ARM: shmobile: kota2: Register pinctrl mappings for BSC Replace the GPIO-based BSC pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kota2.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c index 3f3655702319..ef5ca0ef0cb5 100644 --- a/arch/arm/mach-shmobile/board-kota2.c +++ b/arch/arm/mach-shmobile/board-kota2.c @@ -503,6 +503,15 @@ static const struct pinctrl_map kota2_pinctrl_map[] = { "sdhi1_data4", pin_pullup_conf), PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", "PORT263", pin_pullup_conf), + /* SMSC911X */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", + "bsc_data_0_7", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", + "bsc_data_8_15", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", + "bsc_cs5_a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", + "bsc_we0", "bsc"), }; static void __init kota2_init(void) @@ -518,24 +527,6 @@ static void __init kota2_init(void) sh73a0_pinmux_init(); /* SMSC911X */ - gpio_request(GPIO_FN_D0_NAF0, NULL); - gpio_request(GPIO_FN_D1_NAF1, NULL); - gpio_request(GPIO_FN_D2_NAF2, NULL); - gpio_request(GPIO_FN_D3_NAF3, NULL); - gpio_request(GPIO_FN_D4_NAF4, NULL); - gpio_request(GPIO_FN_D5_NAF5, NULL); - gpio_request(GPIO_FN_D6_NAF6, NULL); - gpio_request(GPIO_FN_D7_NAF7, NULL); - gpio_request(GPIO_FN_D8_NAF8, NULL); - gpio_request(GPIO_FN_D9_NAF9, NULL); - gpio_request(GPIO_FN_D10_NAF10, NULL); - gpio_request(GPIO_FN_D11_NAF11, NULL); - gpio_request(GPIO_FN_D12_NAF12, NULL); - gpio_request(GPIO_FN_D13_NAF13, NULL); - gpio_request(GPIO_FN_D14_NAF14, NULL); - gpio_request(GPIO_FN_D15_NAF15, NULL); - gpio_request(GPIO_FN_CS5A_, NULL); - gpio_request(GPIO_FN_WE0__FWE, NULL); gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ From f3202e1b17f507a3199ea642e85080711f594555 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 151/307] ARM: shmobile: kzm9g: Register pinctrl mappings for LCD Replace the GPIO-based LCD pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- arch/arm/mach-shmobile/board-kzm9g.c | 38 ++++++++-------------------- 1 file changed, 11 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 65a5e0b80f06..7cef0058bfde 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -599,6 +600,14 @@ static struct platform_device *kzm_devices[] __initdata = { &fsi_ak4648_device, }; +static const struct pinctrl_map kzm_pinctrl_map[] = { + /* LCD */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", + "lcd_data24", "lcd"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", + "lcd_sync", "lcd"), +}; + /* * FIXME * @@ -660,6 +669,8 @@ static void __init kzm_init(void) ARRAY_SIZE(fixed2v8_power_consumers), 2800000); regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); + sh73a0_pinmux_init(); /* enable SCIFA4 */ @@ -675,33 +686,6 @@ static void __init kzm_init(void) gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */ /* LCDC */ - gpio_request(GPIO_FN_LCDD23, NULL); - gpio_request(GPIO_FN_LCDD22, NULL); - gpio_request(GPIO_FN_LCDD21, NULL); - gpio_request(GPIO_FN_LCDD20, NULL); - gpio_request(GPIO_FN_LCDD19, NULL); - gpio_request(GPIO_FN_LCDD18, NULL); - gpio_request(GPIO_FN_LCDD17, NULL); - gpio_request(GPIO_FN_LCDD16, NULL); - gpio_request(GPIO_FN_LCDD15, NULL); - gpio_request(GPIO_FN_LCDD14, NULL); - gpio_request(GPIO_FN_LCDD13, NULL); - gpio_request(GPIO_FN_LCDD12, NULL); - gpio_request(GPIO_FN_LCDD11, NULL); - gpio_request(GPIO_FN_LCDD10, NULL); - gpio_request(GPIO_FN_LCDD9, NULL); - gpio_request(GPIO_FN_LCDD8, NULL); - gpio_request(GPIO_FN_LCDD7, NULL); - gpio_request(GPIO_FN_LCDD6, NULL); - gpio_request(GPIO_FN_LCDD5, NULL); - gpio_request(GPIO_FN_LCDD4, NULL); - gpio_request(GPIO_FN_LCDD3, NULL); - gpio_request(GPIO_FN_LCDD2, NULL); - gpio_request(GPIO_FN_LCDD1, NULL); - gpio_request(GPIO_FN_LCDD0, NULL); - gpio_request(GPIO_FN_LCDDISP, NULL); - gpio_request(GPIO_FN_LCDDCK, NULL); - gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */ gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */ From 5606ed9c0c686f370a4f03ff3c1bfda4c020956d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 152/307] ARM: shmobile: kzm9g: Register pinctrl mappings for SCIF Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kzm9g.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 7cef0058bfde..3d2cdc45c4d0 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -606,6 +606,11 @@ static const struct pinctrl_map kzm_pinctrl_map[] = { "lcd_data24", "lcd"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", "lcd_sync", "lcd"), + /* SCIFA4 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", + "scifa4_data", "scifa4"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", + "scifa4_ctrl", "scifa4"), }; /* @@ -673,12 +678,6 @@ static void __init kzm_init(void) sh73a0_pinmux_init(); - /* enable SCIFA4 */ - gpio_request(GPIO_FN_SCIFA4_TXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); - gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); - /* CS4 for SMSC/USB */ gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */ From 118b673e87c55082e8f537a12db7f2629d6f5109 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 153/307] ARM: shmobile: kzm9g: Register pinctrl mappings for I2C Replace the GPIO-based I2C pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kzm9g.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 3d2cdc45c4d0..df3c5ca4a294 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -601,6 +601,9 @@ static struct platform_device *kzm_devices[] __initdata = { }; static const struct pinctrl_map kzm_pinctrl_map[] = { + /* I2C3 */ + PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", + "i2c3_1", "i2c3"), /* LCD */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", "lcd_data24", "lcd"), @@ -724,10 +727,6 @@ static void __init kzm_init(void) gpio_request(GPIO_FN_SDHICLK2, NULL); gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ - /* I2C 3 */ - gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); - gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); - /* enable FSI2 port A (ak4648) */ gpio_request(GPIO_FN_FSIACK, NULL); gpio_request(GPIO_FN_FSIAILR, NULL); From ee9f8da7f722367478b4ebfb51d3c88417246123 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 12:54:28 +0100 Subject: [PATCH 154/307] ARM: shmobile: kzm9g: Register pinctrl mappings for FSI Replace the GPIO-based FSI pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kzm9g.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index df3c5ca4a294..a628d1b3b84e 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -601,6 +601,15 @@ static struct platform_device *kzm_devices[] __initdata = { }; static const struct pinctrl_map kzm_pinctrl_map[] = { + /* FSIA (AK4648) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_mclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_sclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_data_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + "fsia_data_out", "fsia"), /* I2C3 */ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", "i2c3_1", "i2c3"), @@ -727,13 +736,6 @@ static void __init kzm_init(void) gpio_request(GPIO_FN_SDHICLK2, NULL); gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ - /* enable FSI2 port A (ak4648) */ - gpio_request(GPIO_FN_FSIACK, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAISLD, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); - /* enable USB */ gpio_request(GPIO_FN_VBUS_0, NULL); From 83aeac9874b6fe45e42891c0d4cc0f3e86b8aa66 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:23:50 +0100 Subject: [PATCH 155/307] ARM: shmobile: kzm9g: Register pinctrl mappings for SDHI and MMCIF Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kzm9g.c | 54 ++++++++++++++-------------- 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index a628d1b3b84e..335bdbbcd9f6 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -600,6 +601,10 @@ static struct platform_device *kzm_devices[] __initdata = { &fsi_ak4648_device, }; +static unsigned long pin_pullup_conf[] = { + PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +}; + static const struct pinctrl_map kzm_pinctrl_map[] = { /* FSIA (AK4648) */ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", @@ -618,11 +623,34 @@ static const struct pinctrl_map kzm_pinctrl_map[] = { "lcd_data24", "lcd"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", "lcd_sync", "lcd"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_ctrl_0", "mmc0"), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "PORT279", pin_pullup_conf), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", pin_pullup_conf), /* SCIFA4 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_data", "scifa4"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_ctrl", "scifa4"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_cd", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_wp", "sdhi0"), + /* SDHI2 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", + "sdhi2_data4", "sdhi2"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", + "sdhi2_ctrl", "sdhi2"), }; /* @@ -703,37 +731,11 @@ static void __init kzm_init(void) /* Touchscreen */ gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ - /* enable MMCIF */ - gpio_request(GPIO_FN_MMCCLK0, NULL); - gpio_request(GPIO_FN_MMCCMD0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_1_PU, NULL); - gpio_request(GPIO_FN_MMCD0_2_PU, NULL); - gpio_request(GPIO_FN_MMCD0_3_PU, NULL); - gpio_request(GPIO_FN_MMCD0_4_PU, NULL); - gpio_request(GPIO_FN_MMCD0_5_PU, NULL); - gpio_request(GPIO_FN_MMCD0_6_PU, NULL); - gpio_request(GPIO_FN_MMCD0_7_PU, NULL); - /* enable SD */ - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICD0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ /* enable Micro SD */ - gpio_request(GPIO_FN_SDHID2_0, NULL); - gpio_request(GPIO_FN_SDHID2_1, NULL); - gpio_request(GPIO_FN_SDHID2_2, NULL); - gpio_request(GPIO_FN_SDHID2_3, NULL); - gpio_request(GPIO_FN_SDHICMD2, NULL); - gpio_request(GPIO_FN_SDHICLK2, NULL); gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ /* enable USB */ From fed94cf818e318f3c1a8eddbaed33b7342050a1b Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:21:36 +0100 Subject: [PATCH 156/307] ARM: shmobile: kzm9g: Register pinctrl mappings for BSC Replace the GPIO-based BSC pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kzm9g.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 335bdbbcd9f6..742704111f72 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -651,6 +651,9 @@ static const struct pinctrl_map kzm_pinctrl_map[] = { "sdhi2_data4", "sdhi2"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", "sdhi2_ctrl", "sdhi2"), + /* SMSC */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", + "bsc_cs4", "bsc"), }; /* @@ -718,9 +721,6 @@ static void __init kzm_init(void) sh73a0_pinmux_init(); - /* CS4 for SMSC/USB */ - gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */ - /* SMSC */ gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */ From f4243860c6045763ea5b9d2407090bc7deca0ce7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 03:23:50 +0100 Subject: [PATCH 157/307] ARM: shmobile: kzm9g: Register pinctrl mappings for USB Replace the GPIO-based USB pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-kzm9g.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 742704111f72..c1c0401ff6a4 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -654,6 +654,9 @@ static const struct pinctrl_map kzm_pinctrl_map[] = { /* SMSC */ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", "bsc_cs4", "bsc"), + /* USB */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0", + "usb_vbus", "usb"), }; /* @@ -738,9 +741,6 @@ static void __init kzm_init(void) /* enable Micro SD */ gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ - /* enable USB */ - gpio_request(GPIO_FN_VBUS_0, NULL); - #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); From 26e19bd48137fde1a4be575faa9bb3157b0db8a3 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:22:11 +0100 Subject: [PATCH 158/307] ARM: shmobile: mackerel: Register pinctrl mappings for SDHI and MMCIF Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl mappings Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-mackerel.c | 68 +++++++++++-------------- 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 172d47216c91..336ccb4a0f2a 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -1328,6 +1329,33 @@ static struct i2c_board_info i2c1_devices[] = { }, }; +static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_ctrl_0", "mmc0"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "sdhi0_wp", "sdhi0"), + /* SDHI1 */ +#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", + "sdhi1_data4", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", + "sdhi1_ctrl", "sdhi1"), +#endif + /* SDHI2 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", + "sdhi2_data4", "sdhi2"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", + "sdhi2_ctrl", "sdhi2"), +}; + #define GPIO_PORT9CR IOMEM(0xE6051009) #define GPIO_PORT10CR IOMEM(0xE605100A) #define GPIO_PORT167CR IOMEM(0xE60520A7) @@ -1364,6 +1392,8 @@ static void __init mackerel_init(void) /* External clock source */ clk_set_rate(&sh7372_dv_clki_clk, 27000000); + pinctrl_register_mappings(mackerel_pinctrl_map, + ARRAY_SIZE(mackerel_pinctrl_map)); sh7372_pinmux_init(); /* enable SCIFA0 */ @@ -1453,53 +1483,15 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_IRQ21, NULL); irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); - /* enable SDHI0 */ - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); - /* SDHI0 PORT172 card-detect IRQ26 */ gpio_request(GPIO_FN_IRQ26_172, NULL); -#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) - /* enable SDHI1 */ - gpio_request(GPIO_FN_SDHICMD1, NULL); - gpio_request(GPIO_FN_SDHICLK1, NULL); - gpio_request(GPIO_FN_SDHID1_3, NULL); - gpio_request(GPIO_FN_SDHID1_2, NULL); - gpio_request(GPIO_FN_SDHID1_1, NULL); - gpio_request(GPIO_FN_SDHID1_0, NULL); -#endif /* card detect pin for MMC slot (CN7) */ gpio_request_one(41, GPIOF_IN, NULL); - /* enable SDHI2 */ - gpio_request(GPIO_FN_SDHICMD2, NULL); - gpio_request(GPIO_FN_SDHICLK2, NULL); - gpio_request(GPIO_FN_SDHID2_3, NULL); - gpio_request(GPIO_FN_SDHID2_2, NULL); - gpio_request(GPIO_FN_SDHID2_1, NULL); - gpio_request(GPIO_FN_SDHID2_0, NULL); - /* card detect pin for microSD slot (CN23) */ gpio_request_one(162, GPIOF_IN, NULL); - /* MMCIF */ - gpio_request(GPIO_FN_MMCD0_0, NULL); - gpio_request(GPIO_FN_MMCD0_1, NULL); - gpio_request(GPIO_FN_MMCD0_2, NULL); - gpio_request(GPIO_FN_MMCD0_3, NULL); - gpio_request(GPIO_FN_MMCD0_4, NULL); - gpio_request(GPIO_FN_MMCD0_5, NULL); - gpio_request(GPIO_FN_MMCD0_6, NULL); - gpio_request(GPIO_FN_MMCD0_7, NULL); - gpio_request(GPIO_FN_MMCCMD0, NULL); - gpio_request(GPIO_FN_MMCCLK0, NULL); - /* FLCTL */ gpio_request(GPIO_FN_D0_NAF0, NULL); gpio_request(GPIO_FN_D1_NAF1, NULL); From 4a655ecd30caae31aba3363f83e0f8d236da9570 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:22:11 +0100 Subject: [PATCH 159/307] ARM: shmobile: marzen: Register pinctrl mappings for SDHI and MMCIF Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl mappings Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-marzen.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index fec49ebc359a..f00677fcc78a 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -327,6 +328,18 @@ void __init marzen_init_late(void) ARRAY_SIZE(marzen_late_devices)); } +static const struct pinctrl_map marzen_pinctrl_map[] = { + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_cd", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_wp", "sdhi0"), +}; + static void __init marzen_init(void) { regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, @@ -334,6 +347,8 @@ static void __init marzen_init(void) regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + pinctrl_register_mappings(marzen_pinctrl_map, + ARRAY_SIZE(marzen_pinctrl_map)); r8a7779_pinmux_init(); /* SCIF2 (CN18: DEBUG0) */ @@ -348,16 +363,6 @@ static void __init marzen_init(void) gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ - /* SD0 (CN20) */ - gpio_request(GPIO_FN_SD0_CLK, NULL); - gpio_request(GPIO_FN_SD0_CMD, NULL); - gpio_request(GPIO_FN_SD0_DAT0, NULL); - gpio_request(GPIO_FN_SD0_DAT1, NULL); - gpio_request(GPIO_FN_SD0_DAT2, NULL); - gpio_request(GPIO_FN_SD0_DAT3, NULL); - gpio_request(GPIO_FN_SD0_CD, NULL); - gpio_request(GPIO_FN_SD0_WP, NULL); - /* HSPI 0 */ gpio_request(GPIO_FN_HSPI_CLK0, NULL); gpio_request(GPIO_FN_HSPI_CS0, NULL); From e9cd49faef0029efcffc22bba03baa638371f2f5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:22:11 +0100 Subject: [PATCH 160/307] ARM: shmobile: marzen: Register pinctrl mappings for SCIF Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-marzen.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index f00677fcc78a..4097366603b0 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -329,6 +329,12 @@ void __init marzen_init_late(void) } static const struct pinctrl_map marzen_pinctrl_map[] = { + /* SCIF2 (CN18: DEBUG0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", + "scif2_data_c", "scif2"), + /* SCIF4 (CN19: DEBUG1) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779", + "scif4_data", "scif4"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", "sdhi0_data4", "sdhi0"), @@ -351,14 +357,6 @@ static void __init marzen_init(void) ARRAY_SIZE(marzen_pinctrl_map)); r8a7779_pinmux_init(); - /* SCIF2 (CN18: DEBUG0) */ - gpio_request(GPIO_FN_TX2_C, NULL); - gpio_request(GPIO_FN_RX2_C, NULL); - - /* SCIF4 (CN19: DEBUG1) */ - gpio_request(GPIO_FN_TX4, NULL); - gpio_request(GPIO_FN_RX4, NULL); - /* LAN89218 */ gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ From a3217471863c6d3a1ca20bb728ee526c940d87f7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:22:11 +0100 Subject: [PATCH 161/307] ARM: shmobile: marzen: Register pinctrl mappings for HSPI Replace the GPIO-based HSPI pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-marzen.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 4097366603b0..8871af322b4e 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -329,6 +329,9 @@ void __init marzen_init_late(void) } static const struct pinctrl_map marzen_pinctrl_map[] = { + /* HSPI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", + "hspi0", "hspi0"), /* SCIF2 (CN18: DEBUG0) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", "scif2_data_c", "scif2"), @@ -361,12 +364,6 @@ static void __init marzen_init(void) gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ - /* HSPI 0 */ - gpio_request(GPIO_FN_HSPI_CLK0, NULL); - gpio_request(GPIO_FN_HSPI_CS0, NULL); - gpio_request(GPIO_FN_HSPI_TX0, NULL); - gpio_request(GPIO_FN_HSPI_RX0, NULL); - /* USB (CN21) */ gpio_request(GPIO_FN_USB_OVC0, NULL); gpio_request(GPIO_FN_USB_OVC1, NULL); From a00f6e57aaeb9831e0d248022051e3b6662c484a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:46:02 +0100 Subject: [PATCH 162/307] ARM: shmobile: marzen: Register pinctrl mappings for USB Replace the GPIO-based USB pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-marzen.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 8871af322b4e..04bcf8801c24 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -347,6 +347,15 @@ static const struct pinctrl_map marzen_pinctrl_map[] = { "sdhi0_cd", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", "sdhi0_wp", "sdhi0"), + /* USB0 */ + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", + "usb0", "usb0"), + /* USB1 */ + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", + "usb1", "usb1"), + /* USB2 */ + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779", + "usb2", "usb2"), }; static void __init marzen_init(void) @@ -364,14 +373,6 @@ static void __init marzen_init(void) gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ - /* USB (CN21) */ - gpio_request(GPIO_FN_USB_OVC0, NULL); - gpio_request(GPIO_FN_USB_OVC1, NULL); - gpio_request(GPIO_FN_USB_OVC2, NULL); - - /* USB (CN22) */ - gpio_request(GPIO_FN_USB_PENC2, NULL); - r8a7779_add_standard_devices(); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); } From f423df8e4911dad0b3adf36b0865a902192711b8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:46:02 +0100 Subject: [PATCH 163/307] ARM: shmobile: marzen: Register pinctrl mappings for LBSC Replace the GPIO-based LBSC pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-marzen.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 04bcf8801c24..b16f85f43df4 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -347,6 +347,9 @@ static const struct pinctrl_map marzen_pinctrl_map[] = { "sdhi0_cd", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", "sdhi0_wp", "sdhi0"), + /* SMSC */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", + "lbsc_ex_cs0", "lbsc"), /* USB0 */ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", "usb0", "usb0"), @@ -370,7 +373,6 @@ static void __init marzen_init(void) r8a7779_pinmux_init(); /* LAN89218 */ - gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ r8a7779_add_standard_devices(); From ee097e661722c65486cb94c07ae7393e8c11fb4b Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:46:02 +0100 Subject: [PATCH 164/307] ARM: shmobile: marzen: Register pinctrl mappings for INTC Replace the GPIO-based INTC pinmux configuration by pinctrl mappings. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/board-marzen.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index b16f85f43df4..5852331743e7 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -348,6 +347,8 @@ static const struct pinctrl_map marzen_pinctrl_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", "sdhi0_wp", "sdhi0"), /* SMSC */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", + "intc_irq1_b", "intc"), PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", "lbsc_ex_cs0", "lbsc"), /* USB0 */ @@ -372,9 +373,6 @@ static void __init marzen_init(void) ARRAY_SIZE(marzen_pinctrl_map)); r8a7779_pinmux_init(); - /* LAN89218 */ - gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ - r8a7779_add_standard_devices(); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); } From 570f76a867b98b61a018bea490adec065d871029 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:23:17 +0100 Subject: [PATCH 165/307] sh-pfc: sh7372: Remove SDHI and MMCIF function GPIOS All sh7372 platforms now use the pinctrl API to control the SDHI and MMCIF pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index cef4d6a598dd..df0ae21a5ac8 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -1277,18 +1277,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), - /* MMCIF(1) */ - GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2), - GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5), - GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0), - GPIO_FN(MMCCLK0), - - /* MMCIF(2) */ - GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2), - GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5), - GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1), - GPIO_FN(MMCCMD1), - /* SPU2 */ GPIO_FN(VINT_I), @@ -1385,19 +1373,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* HDMI */ GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), - /* SDHI0 */ - GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0), - GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1), - GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3), - - /* SDHI1 */ - GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0), - GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3), - - /* SDHI2 */ - GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0), - GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3), - /* SDENC */ GPIO_FN(SDENC_CPG), GPIO_FN(SDENC_DV_CLKI), From 31d3a01a870d9d69a1d407af651ccd65a099dc79 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 166/307] sh-pfc: sh73a0: Remove LCD and LCD2 function GPIOS All sh73a0 platforms now use the pinctrl API to control the LCD and LCD2 pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 76 ----------------------------- 1 file changed, 76 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 8fc5eb0025c5..1054a4265e0a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3545,87 +3545,59 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(BBIF1_FLOW), GPIO_FN(HSI_TX_FLAG), GPIO_FN(VIO_VD), \ - GPIO_FN(PORT128_LCD2VSYN), \ GPIO_FN(VIO2_VD), \ - GPIO_FN(LCD2D0), GPIO_FN(VIO_HD), \ - GPIO_FN(PORT129_LCD2HSYN), \ - GPIO_FN(PORT129_LCD2CS_), \ GPIO_FN(VIO2_HD), \ - GPIO_FN(LCD2D1), GPIO_FN(VIO_D0), \ GPIO_FN(PORT130_MSIOF2_RXD), \ - GPIO_FN(LCD2D10), GPIO_FN(VIO_D1), \ GPIO_FN(PORT131_KEYOUT6), \ GPIO_FN(PORT131_MSIOF2_SS1), \ GPIO_FN(PORT131_KEYOUT11), \ - GPIO_FN(LCD2D11), GPIO_FN(VIO_D2), \ GPIO_FN(PORT132_KEYOUT7), \ GPIO_FN(PORT132_MSIOF2_SS2), \ GPIO_FN(PORT132_KEYOUT10), \ - GPIO_FN(LCD2D12), GPIO_FN(VIO_D3), \ GPIO_FN(MSIOF2_TSYNC), \ - GPIO_FN(LCD2D13), GPIO_FN(VIO_D4), \ GPIO_FN(MSIOF2_TXD), \ - GPIO_FN(LCD2D14), GPIO_FN(VIO_D5), \ GPIO_FN(MSIOF2_TSCK), \ - GPIO_FN(LCD2D15), GPIO_FN(VIO_D6), \ GPIO_FN(PORT136_KEYOUT8), \ - GPIO_FN(LCD2D16), GPIO_FN(VIO_D7), \ GPIO_FN(PORT137_KEYOUT9), \ - GPIO_FN(LCD2D17), GPIO_FN(VIO_D8), \ GPIO_FN(PORT138_KEYOUT8), \ GPIO_FN(VIO2_D0), \ - GPIO_FN(LCD2D6), GPIO_FN(VIO_D9), \ GPIO_FN(PORT139_KEYOUT9), \ GPIO_FN(VIO2_D1), \ - GPIO_FN(LCD2D7), GPIO_FN(VIO_D10), \ GPIO_FN(TPU0TO2), \ GPIO_FN(VIO2_D2), \ - GPIO_FN(LCD2D8), GPIO_FN(VIO_D11), \ GPIO_FN(TPU0TO3), \ GPIO_FN(VIO2_D3), \ - GPIO_FN(LCD2D9), GPIO_FN(VIO_D12), \ GPIO_FN(PORT142_KEYOUT10), \ GPIO_FN(VIO2_D4), \ - GPIO_FN(LCD2D2), GPIO_FN(VIO_D13), \ GPIO_FN(PORT143_KEYOUT11), \ GPIO_FN(PORT143_KEYOUT6), \ GPIO_FN(VIO2_D5), \ - GPIO_FN(LCD2D3), GPIO_FN(VIO_D14), \ GPIO_FN(PORT144_KEYOUT7), \ GPIO_FN(VIO2_D6), \ - GPIO_FN(LCD2D4), GPIO_FN(VIO_D15), \ GPIO_FN(TPU1TO3), \ - GPIO_FN(PORT145_LCD2DISP), \ - GPIO_FN(PORT145_LCD2RS), \ GPIO_FN(VIO2_D7), \ - GPIO_FN(LCD2D5), GPIO_FN(VIO_CLK), \ - GPIO_FN(LCD2DCK), \ - GPIO_FN(PORT146_LCD2WR_), \ GPIO_FN(VIO2_CLK), \ - GPIO_FN(LCD2D18), GPIO_FN(VIO_FIELD), \ - GPIO_FN(LCD2RD_), \ GPIO_FN(VIO2_FIELD), \ - GPIO_FN(LCD2D19), GPIO_FN(VIO_CKO), GPIO_FN(A27), \ GPIO_FN(PORT149_RDWR), \ @@ -3662,107 +3634,63 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(PORT163_SCIFB_RTS_), \ GPIO_FN(PORT163_SCIFA5_RTS_), \ GPIO_FN(TPU3TO0), - GPIO_FN(LCDD0), - GPIO_FN(LCDD1), \ GPIO_FN(PORT193_SCIFA5_CTS_), \ GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(LCDD2), \ GPIO_FN(PORT194_SCIFA5_RTS_), \ GPIO_FN(BBIF2_TSCK1), - GPIO_FN(LCDD3), \ GPIO_FN(PORT195_SCIFA5_RXD), \ GPIO_FN(BBIF2_TXD1), - GPIO_FN(LCDD4), \ GPIO_FN(PORT196_SCIFA5_TXD), - GPIO_FN(LCDD5), \ GPIO_FN(PORT197_SCIFA5_SCK), \ GPIO_FN(MFG2_OUT2), \ GPIO_FN(TPU2TO1), - GPIO_FN(LCDD6), - GPIO_FN(LCDD7), \ GPIO_FN(TPU4TO1), \ GPIO_FN(MFG4_OUT2), - GPIO_FN(LCDD8), \ GPIO_FN(D16), - GPIO_FN(LCDD9), \ GPIO_FN(D17), - GPIO_FN(LCDD10), \ GPIO_FN(D18), - GPIO_FN(LCDD11), \ GPIO_FN(D19), - GPIO_FN(LCDD12), \ GPIO_FN(D20), - GPIO_FN(LCDD13), \ GPIO_FN(D21), - GPIO_FN(LCDD14), \ GPIO_FN(D22), - GPIO_FN(LCDD15), \ GPIO_FN(PORT207_MSIOF0L_SS1), \ GPIO_FN(D23), - GPIO_FN(LCDD16), \ GPIO_FN(PORT208_MSIOF0L_SS2), \ GPIO_FN(D24), - GPIO_FN(LCDD17), \ GPIO_FN(D25), - GPIO_FN(LCDD18), \ GPIO_FN(DREQ2), \ GPIO_FN(PORT210_MSIOF0L_SS1), \ GPIO_FN(D26), - GPIO_FN(LCDD19), \ GPIO_FN(PORT211_MSIOF0L_SS2), \ GPIO_FN(D27), - GPIO_FN(LCDD20), \ GPIO_FN(TS_SPSYNC1), \ GPIO_FN(MSIOF0L_MCK0), \ GPIO_FN(D28), - GPIO_FN(LCDD21), \ GPIO_FN(TS_SDAT1), \ GPIO_FN(MSIOF0L_MCK1), \ GPIO_FN(D29), - GPIO_FN(LCDD22), \ GPIO_FN(TS_SDEN1), \ GPIO_FN(MSIOF0L_RSCK), \ GPIO_FN(D30), - GPIO_FN(LCDD23), \ GPIO_FN(TS_SCK1), \ GPIO_FN(MSIOF0L_RSYNC), \ GPIO_FN(D31), - GPIO_FN(LCDDCK), \ - GPIO_FN(LCDWR_), - GPIO_FN(LCDRD_), \ GPIO_FN(DACK2), \ - GPIO_FN(PORT217_LCD2RS), \ GPIO_FN(MSIOF0L_TSYNC), \ GPIO_FN(VIO2_FIELD3), \ - GPIO_FN(PORT217_LCD2DISP), - GPIO_FN(LCDHSYN), \ - GPIO_FN(LCDCS_), \ - GPIO_FN(LCDCS2_), \ GPIO_FN(DACK3), \ GPIO_FN(PORT218_VIO_CKOR), - GPIO_FN(LCDDISP), \ - GPIO_FN(LCDRS), \ - GPIO_FN(PORT219_LCD2WR_), \ GPIO_FN(DREQ3), \ GPIO_FN(MSIOF0L_TSCK), \ GPIO_FN(VIO2_CLK3), \ - GPIO_FN(LCD2DCK_2), - GPIO_FN(LCDVSYN), \ - GPIO_FN(LCDVSYN2), - GPIO_FN(LCDLCLK), \ GPIO_FN(DREQ1), \ - GPIO_FN(PORT221_LCD2CS_), \ GPIO_FN(PWEN), \ GPIO_FN(MSIOF0L_RXD), \ GPIO_FN(VIO2_HD3), \ - GPIO_FN(PORT221_LCD2HSYN), - GPIO_FN(LCDDON), \ - GPIO_FN(LCDDON2), \ GPIO_FN(DACK1), \ GPIO_FN(OVCN), \ GPIO_FN(MSIOF0L_TXD), \ GPIO_FN(VIO2_VD3), \ - GPIO_FN(PORT222_LCD2VSYN), GPIO_FN(SCIFA1_TXD), \ GPIO_FN(OVCN2), @@ -3785,21 +3713,17 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MSIOF1_RSCK), \ GPIO_FN(SCIFA2_RTS2_), \ GPIO_FN(VIO2_CLK2), \ - GPIO_FN(LCD2D20), GPIO_FN(MSIOF1_RSYNC), \ GPIO_FN(MFG1_IN2), \ GPIO_FN(VIO2_VD2), \ - GPIO_FN(LCD2D21), GPIO_FN(MSIOF1_MCK0), \ GPIO_FN(PORT236_I2C_SDA2), GPIO_FN(MSIOF1_MCK1), \ GPIO_FN(PORT237_I2C_SCL2), GPIO_FN(MSIOF1_SS1), \ GPIO_FN(VIO2_FIELD2), \ - GPIO_FN(LCD2D22), GPIO_FN(MSIOF1_SS2), \ GPIO_FN(VIO2_HD2), \ - GPIO_FN(LCD2D23), GPIO_FN(SCIFA6_TXD), GPIO_FN(PORT241_IRDA_OUT), \ GPIO_FN(PORT241_IROUT), \ From 27d9b21f79fdd59a3592b8c973be1472d8f54d46 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 167/307] sh-pfc: sh73a0: Remove SCIFA and SCIFB function GPIOS All sh73a0 platforms now use the pinctrl API to control the SCIFA and SCIFB pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 58 ----------------------------- 1 file changed, 58 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 1054a4265e0a..6d36ebbdcdd3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3335,19 +3335,13 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(GPI5), GPIO_FN(GPI6), GPIO_FN(GPI7), - GPIO_FN(SCIFA7_RXD), - GPIO_FN(SCIFA7_CTS_), GPIO_FN(GPO7), \ GPIO_FN(MFG0_OUT2), GPIO_FN(GPO6), \ GPIO_FN(MFG1_OUT2), GPIO_FN(GPO5), \ - GPIO_FN(SCIFA0_SCK), \ GPIO_FN(FSICOSLDT3), \ GPIO_FN(PORT16_VIO_CKOR), - GPIO_FN(SCIFA0_TXD), - GPIO_FN(SCIFA7_TXD), - GPIO_FN(SCIFA7_RTS_), \ GPIO_FN(PORT19_VIO_CKO2), GPIO_FN(GPO0), GPIO_FN(GPO1), @@ -3374,11 +3368,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(PORT30_VIO_CKOR), GPIO_FN(SIM_D), \ GPIO_FN(PORT31_IROUT), - GPIO_FN(SCIFA4_TXD), - GPIO_FN(SCIFA4_RXD), \ GPIO_FN(XWUP), - GPIO_FN(SCIFA4_RTS_), - GPIO_FN(SCIFA4_CTS_), GPIO_FN(FSIBOBT), \ GPIO_FN(FSIBIBT), GPIO_FN(FSIBOLR), \ @@ -3387,10 +3377,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(FSIBISLD), GPIO_FN(VACK), GPIO_FN(XTAL1L), - GPIO_FN(SCIFA0_RTS_), \ GPIO_FN(FSICOSLDT2), - GPIO_FN(SCIFA0_RXD), - GPIO_FN(SCIFA0_CTS_), \ GPIO_FN(FSICOSLDT1), GPIO_FN(FSICOBT), \ GPIO_FN(FSICIBT), \ @@ -3516,14 +3503,10 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(BBIF2_RXD), GPIO_FN(BBIF2_SYNC), GPIO_FN(BBIF2_SCK), - GPIO_FN(SCIFA3_CTS_), \ GPIO_FN(MFG3_IN2), - GPIO_FN(SCIFA3_RXD), \ GPIO_FN(MFG3_IN1), GPIO_FN(BBIF1_SS2), \ - GPIO_FN(SCIFA3_RTS_), \ GPIO_FN(MFG3_OUT1), - GPIO_FN(SCIFA3_TXD), GPIO_FN(HSI_RX_DATA), \ GPIO_FN(BBIF1_RXD), GPIO_FN(HSI_TX_WAKE), \ @@ -3611,37 +3594,17 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(TPU1TO2), \ GPIO_FN(TS_SDEN3), \ GPIO_FN(PORT153_MSIOF2_SS1), - GPIO_FN(SCIFA2_TXD1), \ GPIO_FN(MSIOF2_MCK0), - GPIO_FN(SCIFA2_RXD1), \ GPIO_FN(MSIOF2_MCK1), - GPIO_FN(SCIFA2_RTS1_), \ GPIO_FN(PORT156_MSIOF2_SS2), - GPIO_FN(SCIFA2_CTS1_), \ GPIO_FN(PORT157_MSIOF2_RXD), GPIO_FN(DINT_), \ - GPIO_FN(SCIFA2_SCK1), \ GPIO_FN(TS_SCK3), - GPIO_FN(PORT159_SCIFB_SCK), \ - GPIO_FN(PORT159_SCIFA5_SCK), \ GPIO_FN(NMI), - GPIO_FN(PORT160_SCIFB_TXD), \ - GPIO_FN(PORT160_SCIFA5_TXD), - GPIO_FN(PORT161_SCIFB_CTS_), \ - GPIO_FN(PORT161_SCIFA5_CTS_), - GPIO_FN(PORT162_SCIFB_RXD), \ - GPIO_FN(PORT162_SCIFA5_RXD), - GPIO_FN(PORT163_SCIFB_RTS_), \ - GPIO_FN(PORT163_SCIFA5_RTS_), \ GPIO_FN(TPU3TO0), - GPIO_FN(PORT193_SCIFA5_CTS_), \ GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(PORT194_SCIFA5_RTS_), \ GPIO_FN(BBIF2_TSCK1), - GPIO_FN(PORT195_SCIFA5_RXD), \ GPIO_FN(BBIF2_TXD1), - GPIO_FN(PORT196_SCIFA5_TXD), - GPIO_FN(PORT197_SCIFA5_SCK), \ GPIO_FN(MFG2_OUT2), \ GPIO_FN(TPU2TO1), GPIO_FN(TPU4TO1), \ @@ -3692,26 +3655,16 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MSIOF0L_TXD), \ GPIO_FN(VIO2_VD3), \ - GPIO_FN(SCIFA1_TXD), \ GPIO_FN(OVCN2), GPIO_FN(EXTLP), \ - GPIO_FN(SCIFA1_SCK), \ GPIO_FN(PORT226_VIO_CKO2), - GPIO_FN(SCIFA1_RTS_), \ GPIO_FN(IDIN), - GPIO_FN(SCIFA1_RXD), - GPIO_FN(SCIFA1_CTS_), \ GPIO_FN(MFG1_IN1), GPIO_FN(MSIOF1_TXD), \ - GPIO_FN(SCIFA2_TXD2), GPIO_FN(MSIOF1_TSYNC), \ - GPIO_FN(SCIFA2_CTS2_), GPIO_FN(MSIOF1_TSCK), \ - GPIO_FN(SCIFA2_SCK2), GPIO_FN(MSIOF1_RXD), \ - GPIO_FN(SCIFA2_RXD2), GPIO_FN(MSIOF1_RSCK), \ - GPIO_FN(SCIFA2_RTS2_), \ GPIO_FN(VIO2_CLK2), \ GPIO_FN(MSIOF1_RSYNC), \ GPIO_FN(MFG1_IN2), \ @@ -3724,7 +3677,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VIO2_FIELD2), \ GPIO_FN(MSIOF1_SS2), \ GPIO_FN(VIO2_HD2), \ - GPIO_FN(SCIFA6_TXD), GPIO_FN(PORT241_IRDA_OUT), \ GPIO_FN(PORT241_IROUT), \ GPIO_FN(MFG4_OUT1), \ @@ -3733,25 +3685,15 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MFG4_IN2), GPIO_FN(PORT243_IRDA_FIRSEL), \ GPIO_FN(PORT243_VIO_CKO2), - GPIO_FN(PORT244_SCIFA5_CTS_), \ GPIO_FN(MFG2_IN1), \ - GPIO_FN(PORT244_SCIFB_CTS_), \ GPIO_FN(MSIOF2R_RXD), - GPIO_FN(PORT245_SCIFA5_RTS_), \ GPIO_FN(MFG2_IN2), \ - GPIO_FN(PORT245_SCIFB_RTS_), \ GPIO_FN(MSIOF2R_TXD), - GPIO_FN(PORT246_SCIFA5_RXD), \ GPIO_FN(MFG1_OUT1), \ - GPIO_FN(PORT246_SCIFB_RXD), \ GPIO_FN(TPU1TO0), - GPIO_FN(PORT247_SCIFA5_TXD), \ GPIO_FN(MFG3_OUT2), \ - GPIO_FN(PORT247_SCIFB_TXD), \ GPIO_FN(TPU3TO1), - GPIO_FN(PORT248_SCIFA5_SCK), \ GPIO_FN(MFG2_OUT1), \ - GPIO_FN(PORT248_SCIFB_SCK), \ GPIO_FN(TPU2TO0), \ GPIO_FN(PORT248_I2C_SCL3), \ GPIO_FN(MSIOF2R_TSCK), From 85ef3315475fc999730fc24c58343091dd4d1727 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 168/307] sh-pfc: sh73a0: Remove I2C function GPIOS All sh73a0 platforms now use the pinctrl API to control the I2C pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 6d36ebbdcdd3..13bd1380316d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3354,13 +3354,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VINT), GPIO_FN(TCKON), GPIO_FN(XDVFS1), \ - GPIO_FN(PORT27_I2C_SCL2), \ - GPIO_FN(PORT27_I2C_SCL3), \ GPIO_FN(MFG0_OUT1), \ GPIO_FN(PORT27_IROUT), GPIO_FN(XDVFS2), \ - GPIO_FN(PORT28_I2C_SDA2), \ - GPIO_FN(PORT28_I2C_SDA3), \ GPIO_FN(PORT28_TPU1TO1), GPIO_FN(SIM_RST), \ GPIO_FN(PORT29_TPU1TO1), @@ -3517,12 +3513,8 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(BBIF1_TXD), GPIO_FN(HSI_RX_READY), \ GPIO_FN(BBIF1_RSCK), \ - GPIO_FN(PORT115_I2C_SCL2), \ - GPIO_FN(PORT115_I2C_SCL3), GPIO_FN(HSI_RX_WAKE), \ GPIO_FN(BBIF1_RSYNC), \ - GPIO_FN(PORT116_I2C_SDA2), \ - GPIO_FN(PORT116_I2C_SDA3), GPIO_FN(HSI_RX_FLAG), \ GPIO_FN(BBIF1_SS1), \ GPIO_FN(BBIF1_FLOW), @@ -3670,9 +3662,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MFG1_IN2), \ GPIO_FN(VIO2_VD2), \ GPIO_FN(MSIOF1_MCK0), \ - GPIO_FN(PORT236_I2C_SDA2), GPIO_FN(MSIOF1_MCK1), \ - GPIO_FN(PORT237_I2C_SCL2), GPIO_FN(MSIOF1_SS1), \ GPIO_FN(VIO2_FIELD2), \ GPIO_FN(MSIOF1_SS2), \ @@ -3695,11 +3685,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(TPU3TO1), GPIO_FN(MFG2_OUT1), \ GPIO_FN(TPU2TO0), \ - GPIO_FN(PORT248_I2C_SCL3), \ GPIO_FN(MSIOF2R_TSCK), GPIO_FN(PORT249_IROUT), \ GPIO_FN(MFG4_IN1), \ - GPIO_FN(PORT249_I2C_SDA3), \ GPIO_FN(MSIOF2R_TSYNC), GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), From 0b1e75ccc18c34a0f4c37e501aa4cf17a3ae37f7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 169/307] sh-pfc: sh73a0: Remove FSI function GPIOS All sh73a0 platforms now use the pinctrl API to control the FSI pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 36 ----------------------------- 1 file changed, 36 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 13bd1380316d..1a638f2c7ec2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3340,7 +3340,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(GPO6), \ GPIO_FN(MFG1_OUT2), GPIO_FN(GPO5), \ - GPIO_FN(FSICOSLDT3), \ GPIO_FN(PORT16_VIO_CKOR), GPIO_FN(PORT19_VIO_CKO2), GPIO_FN(GPO0), @@ -3365,55 +3364,20 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SIM_D), \ GPIO_FN(PORT31_IROUT), GPIO_FN(XWUP), - GPIO_FN(FSIBOBT), \ - GPIO_FN(FSIBIBT), - GPIO_FN(FSIBOLR), \ - GPIO_FN(FSIBILR), - GPIO_FN(FSIBOSLD), - GPIO_FN(FSIBISLD), GPIO_FN(VACK), GPIO_FN(XTAL1L), - GPIO_FN(FSICOSLDT2), - GPIO_FN(FSICOSLDT1), - GPIO_FN(FSICOBT), \ - GPIO_FN(FSICIBT), \ - GPIO_FN(FSIDOBT), \ - GPIO_FN(FSIDIBT), - GPIO_FN(FSICOLR), \ - GPIO_FN(FSICILR), \ - GPIO_FN(FSIDOLR), \ - GPIO_FN(FSIDILR), - GPIO_FN(FSICOSLD), \ - GPIO_FN(PORT47_FSICSPDIF), - GPIO_FN(FSICISLD), \ - GPIO_FN(FSIDISLD), - GPIO_FN(FSIACK), \ GPIO_FN(PORT49_IRDA_OUT), \ GPIO_FN(PORT49_IROUT), \ - GPIO_FN(FSIAOMC), - GPIO_FN(FSIAOLR), \ GPIO_FN(BBIF2_TSYNC2), \ GPIO_FN(TPU2TO2), \ - GPIO_FN(FSIAILR), - GPIO_FN(FSIAOBT), \ GPIO_FN(BBIF2_TSCK2), \ GPIO_FN(TPU2TO3), \ - GPIO_FN(FSIAIBT), - GPIO_FN(FSIAOSLD), \ GPIO_FN(BBIF2_TXD2), - GPIO_FN(FSIASPDIF), \ GPIO_FN(PORT53_IRDA_IN), \ GPIO_FN(TPU3TO3), \ - GPIO_FN(FSIBSPDIF), \ - GPIO_FN(PORT53_FSICSPDIF), - GPIO_FN(FSIBCK), \ GPIO_FN(PORT54_IRDA_FIRSEL), \ GPIO_FN(TPU3TO2), \ - GPIO_FN(FSIBOMC), \ - GPIO_FN(FSICCK), \ - GPIO_FN(FSICOMC), - GPIO_FN(FSIAISLD), \ GPIO_FN(TPU0TO0), GPIO_FN(A0), \ GPIO_FN(BS_), From 19ac5557e74fb4f9d7364235ff805f96c2c4f562 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:32:00 +0100 Subject: [PATCH 170/307] sh-pfc: sh73a0: Remove pull-up function GPIOS All sh73a0 platforms now use the pinconf API to control pull-ups, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 465 ++-------------------------- 1 file changed, 23 insertions(+), 442 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 1a638f2c7ec2..1249a3ffdb31 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -66,14 +66,6 @@ enum { PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ - PINMUX_INPUT_PULLUP_END, - - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ - PINMUX_INPUT_PULLDOWN_END, - PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ PINMUX_OUTPUT_END, @@ -468,328 +460,15 @@ enum { EDBGREQ_PD_MARK, EDBGREQ_PU_MARK, - /* Functions with pull-ups */ - KEYIN0_PU_MARK, - KEYIN1_PU_MARK, - KEYIN2_PU_MARK, - KEYIN3_PU_MARK, - KEYIN4_PU_MARK, - KEYIN5_PU_MARK, - KEYIN6_PU_MARK, - KEYIN7_PU_MARK, - SDHICD0_PU_MARK, - SDHID0_0_PU_MARK, - SDHID0_1_PU_MARK, - SDHID0_2_PU_MARK, - SDHID0_3_PU_MARK, - SDHICMD0_PU_MARK, - SDHIWP0_PU_MARK, - SDHID1_0_PU_MARK, - SDHID1_1_PU_MARK, - SDHID1_2_PU_MARK, - SDHID1_3_PU_MARK, - SDHICMD1_PU_MARK, - SDHID2_0_PU_MARK, - SDHID2_1_PU_MARK, - SDHID2_2_PU_MARK, - SDHID2_3_PU_MARK, - SDHICMD2_PU_MARK, - MMCCMD0_PU_MARK, - MMCCMD1_PU_MARK, - MMCD0_0_PU_MARK, - MMCD0_1_PU_MARK, - MMCD0_2_PU_MARK, - MMCD0_3_PU_MARK, - MMCD0_4_PU_MARK, - MMCD0_5_PU_MARK, - MMCD0_6_PU_MARK, - MMCD0_7_PU_MARK, - FSIBISLD_PU_MARK, - FSIACK_PU_MARK, - FSIAILR_PU_MARK, - FSIAIBT_PU_MARK, - FSIAISLD_PU_MARK, - PINMUX_MARK_END, }; +#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + static const pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ - - /* Table 25-1 (I/O and Pull U/D) */ - PORT_DATA_I_PD(0), - PORT_DATA_I_PU(1), - PORT_DATA_I_PU(2), - PORT_DATA_I_PU(3), - PORT_DATA_I_PU(4), - PORT_DATA_I_PU(5), - PORT_DATA_I_PU(6), - PORT_DATA_I_PU(7), - PORT_DATA_I_PU(8), - PORT_DATA_I_PD(9), - PORT_DATA_I_PD(10), - PORT_DATA_I_PU_PD(11), - PORT_DATA_IO_PU_PD(12), - PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PU_PD(14), - PORT_DATA_IO_PU_PD(15), - PORT_DATA_IO_PD(16), - PORT_DATA_IO_PD(17), - PORT_DATA_IO_PU(18), - PORT_DATA_IO_PU(19), - PORT_DATA_O(20), - PORT_DATA_O(21), - PORT_DATA_O(22), - PORT_DATA_O(23), - PORT_DATA_O(24), - PORT_DATA_I_PD(25), - PORT_DATA_I_PD(26), - PORT_DATA_IO_PU(27), - PORT_DATA_IO_PU(28), - PORT_DATA_IO_PD(29), - PORT_DATA_IO_PD(30), - PORT_DATA_IO_PU(31), - PORT_DATA_IO_PD(32), - PORT_DATA_I_PU_PD(33), - PORT_DATA_IO_PD(34), - PORT_DATA_I_PU_PD(35), - PORT_DATA_IO_PD(36), - PORT_DATA_IO(37), - PORT_DATA_O(38), - PORT_DATA_I_PU(39), - PORT_DATA_I_PU_PD(40), - PORT_DATA_O(41), - PORT_DATA_IO_PD(42), - PORT_DATA_IO_PU_PD(43), - PORT_DATA_IO_PU_PD(44), - PORT_DATA_IO_PD(45), - PORT_DATA_IO_PD(46), - PORT_DATA_IO_PD(47), - PORT_DATA_I_PD(48), - PORT_DATA_IO_PU_PD(49), - PORT_DATA_IO_PD(50), - - PORT_DATA_IO_PD(51), - PORT_DATA_O(52), - PORT_DATA_IO_PU_PD(53), - PORT_DATA_IO_PU_PD(54), - PORT_DATA_IO_PD(55), - PORT_DATA_I_PU_PD(56), - PORT_DATA_IO(57), - PORT_DATA_IO(58), - PORT_DATA_IO(59), - PORT_DATA_IO(60), - PORT_DATA_IO(61), - PORT_DATA_IO_PD(62), - PORT_DATA_IO_PD(63), - PORT_DATA_IO_PU_PD(64), - PORT_DATA_IO_PD(65), - PORT_DATA_IO_PU_PD(66), - PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), - PORT_DATA_IO_PU_PD(69), - PORT_DATA_IO_PU_PD(70), - PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), - PORT_DATA_I_PU_PD(73), - PORT_DATA_IO_PU(74), - PORT_DATA_IO_PU(75), - PORT_DATA_IO_PU(76), - PORT_DATA_IO_PU(77), - PORT_DATA_IO_PU(78), - PORT_DATA_IO_PU(79), - PORT_DATA_IO_PU(80), - PORT_DATA_IO_PU(81), - PORT_DATA_IO_PU(82), - PORT_DATA_IO_PU(83), - PORT_DATA_IO_PU(84), - PORT_DATA_IO_PU(85), - PORT_DATA_IO_PU(86), - PORT_DATA_IO_PU(87), - PORT_DATA_IO_PU(88), - PORT_DATA_IO_PU(89), - PORT_DATA_O(90), - PORT_DATA_IO_PU(91), - PORT_DATA_O(92), - PORT_DATA_IO_PU(93), - PORT_DATA_O(94), - PORT_DATA_I_PU_PD(95), - PORT_DATA_IO(96), - PORT_DATA_IO(97), - PORT_DATA_IO(98), - PORT_DATA_I_PU(99), - PORT_DATA_O(100), - PORT_DATA_O(101), - PORT_DATA_I_PU(102), - PORT_DATA_IO_PD(103), - PORT_DATA_I_PU_PD(104), - PORT_DATA_I_PD(105), - PORT_DATA_I_PD(106), - PORT_DATA_I_PU_PD(107), - PORT_DATA_I_PU_PD(108), - PORT_DATA_IO_PD(109), - PORT_DATA_IO_PD(110), - PORT_DATA_IO_PU_PD(111), - PORT_DATA_IO_PU_PD(112), - PORT_DATA_IO_PU_PD(113), - PORT_DATA_IO_PD(114), - PORT_DATA_IO_PU(115), - PORT_DATA_IO_PU(116), - PORT_DATA_IO_PU_PD(117), - PORT_DATA_IO_PU_PD(118), - PORT_DATA_IO_PD(128), - - PORT_DATA_IO_PD(129), - PORT_DATA_IO_PU_PD(130), - PORT_DATA_IO_PD(131), - PORT_DATA_IO_PD(132), - PORT_DATA_IO_PD(133), - PORT_DATA_IO_PU_PD(134), - PORT_DATA_IO_PU_PD(135), - PORT_DATA_IO_PU_PD(136), - PORT_DATA_IO_PU_PD(137), - PORT_DATA_IO_PD(138), - PORT_DATA_IO_PD(139), - PORT_DATA_IO_PD(140), - PORT_DATA_IO_PD(141), - PORT_DATA_IO_PD(142), - PORT_DATA_IO_PD(143), - PORT_DATA_IO_PU_PD(144), - PORT_DATA_IO_PD(145), - PORT_DATA_IO_PU_PD(146), - PORT_DATA_IO_PU_PD(147), - PORT_DATA_IO_PU_PD(148), - PORT_DATA_IO_PU_PD(149), - PORT_DATA_I_PU_PD(150), - PORT_DATA_IO_PU_PD(151), - PORT_DATA_IO_PU_PD(152), - PORT_DATA_IO_PD(153), - PORT_DATA_IO_PD(154), - PORT_DATA_I_PU_PD(155), - PORT_DATA_IO_PU_PD(156), - PORT_DATA_I_PD(157), - PORT_DATA_IO_PD(158), - PORT_DATA_IO_PU_PD(159), - PORT_DATA_IO_PU_PD(160), - PORT_DATA_I_PU_PD(161), - PORT_DATA_I_PU_PD(162), - PORT_DATA_IO_PU_PD(163), - PORT_DATA_I_PU_PD(164), - PORT_DATA_IO_PD(192), - PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PD(194), - PORT_DATA_IO_PU_PD(195), - PORT_DATA_IO_PD(196), - PORT_DATA_IO_PD(197), - PORT_DATA_IO_PD(198), - PORT_DATA_IO_PD(199), - PORT_DATA_IO_PU_PD(200), - PORT_DATA_IO_PU_PD(201), - PORT_DATA_IO_PU_PD(202), - PORT_DATA_IO_PU_PD(203), - PORT_DATA_IO_PU_PD(204), - PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), - PORT_DATA_IO_PD(207), - PORT_DATA_IO_PD(208), - PORT_DATA_IO_PD(209), - PORT_DATA_IO_PD(210), - PORT_DATA_IO_PD(211), - PORT_DATA_IO_PD(212), - PORT_DATA_IO_PD(213), - PORT_DATA_IO_PU_PD(214), - PORT_DATA_IO_PU_PD(215), - PORT_DATA_IO_PD(216), - PORT_DATA_IO_PD(217), - PORT_DATA_O(218), - PORT_DATA_IO_PD(219), - PORT_DATA_IO_PD(220), - PORT_DATA_IO_PU_PD(221), - PORT_DATA_IO_PU_PD(222), - PORT_DATA_I_PU_PD(223), - PORT_DATA_I_PU_PD(224), - - PORT_DATA_IO_PU_PD(225), - PORT_DATA_O(226), - PORT_DATA_IO_PU_PD(227), - PORT_DATA_I_PU_PD(228), - PORT_DATA_I_PD(229), - PORT_DATA_IO(230), - PORT_DATA_IO_PU_PD(231), - PORT_DATA_IO_PU_PD(232), - PORT_DATA_I_PU_PD(233), - PORT_DATA_IO_PU_PD(234), - PORT_DATA_IO_PU_PD(235), - PORT_DATA_IO_PU_PD(236), - PORT_DATA_IO_PD(237), - PORT_DATA_IO_PU_PD(238), - PORT_DATA_IO_PU_PD(239), - PORT_DATA_IO_PU_PD(240), - PORT_DATA_O(241), - PORT_DATA_I_PD(242), - PORT_DATA_IO_PU_PD(243), - PORT_DATA_IO_PU_PD(244), - PORT_DATA_IO_PU_PD(245), - PORT_DATA_IO_PU_PD(246), - PORT_DATA_IO_PU_PD(247), - PORT_DATA_IO_PU_PD(248), - PORT_DATA_IO_PU_PD(249), - PORT_DATA_IO_PU_PD(250), - PORT_DATA_IO_PU_PD(251), - PORT_DATA_IO_PU_PD(252), - PORT_DATA_IO_PU_PD(253), - PORT_DATA_IO_PU_PD(254), - PORT_DATA_IO_PU_PD(255), - PORT_DATA_IO_PU_PD(256), - PORT_DATA_IO_PU_PD(257), - PORT_DATA_IO_PU_PD(258), - PORT_DATA_IO_PU_PD(259), - PORT_DATA_IO_PU_PD(260), - PORT_DATA_IO_PU_PD(261), - PORT_DATA_IO_PU_PD(262), - PORT_DATA_IO_PU_PD(263), - PORT_DATA_IO_PU_PD(264), - PORT_DATA_IO_PU_PD(265), - PORT_DATA_IO_PU_PD(266), - PORT_DATA_IO_PU_PD(267), - PORT_DATA_IO_PU_PD(268), - PORT_DATA_IO_PU_PD(269), - PORT_DATA_IO_PU_PD(270), - PORT_DATA_IO_PU_PD(271), - PORT_DATA_IO_PU_PD(272), - PORT_DATA_IO_PU_PD(273), - PORT_DATA_IO_PU_PD(274), - PORT_DATA_IO_PU_PD(275), - PORT_DATA_IO_PU_PD(276), - PORT_DATA_IO_PU_PD(277), - PORT_DATA_IO_PU_PD(278), - PORT_DATA_IO_PU_PD(279), - PORT_DATA_IO_PU_PD(280), - PORT_DATA_O(281), - PORT_DATA_O(282), - PORT_DATA_I_PU(288), - PORT_DATA_IO_PU_PD(289), - PORT_DATA_IO_PU_PD(290), - PORT_DATA_IO_PU_PD(291), - PORT_DATA_IO_PU_PD(292), - PORT_DATA_IO_PU_PD(293), - PORT_DATA_IO_PU_PD(294), - PORT_DATA_IO_PU_PD(295), - PORT_DATA_IO_PU_PD(296), - PORT_DATA_IO_PU_PD(297), - PORT_DATA_IO_PU_PD(298), - - PORT_DATA_IO_PU_PD(299), - PORT_DATA_IO_PU_PD(300), - PORT_DATA_IO_PU_PD(301), - PORT_DATA_IO_PU_PD(302), - PORT_DATA_IO_PU_PD(303), - PORT_DATA_IO_PU_PD(304), - PORT_DATA_IO_PU_PD(305), - PORT_DATA_O(306), - PORT_DATA_O(307), - PORT_DATA_I_PU(308), - PORT_DATA_O(309), + PINMUX_DATA_GP_ALL(), /* Table 25-1 (Function 0-7) */ PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), @@ -1358,28 +1037,19 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), - PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), - PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), - PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), - PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, - MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), @@ -1485,62 +1155,6 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), - - /* Functions with pull-ups */ - PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), - PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), - PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), - PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), - PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), - PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), - PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), - PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), - - PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), - PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), - PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), - PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), - PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), - PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), - PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT257_IN_PU), - PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), - PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), - PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), - PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), - PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), - PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), - PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), - PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), - PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), - PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), - - PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, - MSEL4CR_MSEL15_1), - - PINMUX_DATA(MMCD0_0_PU_MARK, - PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_PU_MARK, - PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_PU_MARK, - PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_PU_MARK, - PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_PU_MARK, - PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_5_PU_MARK, - PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_6_PU_MARK, - PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_7_PU_MARK, - PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), - - PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), - PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), - PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), - PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), - PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), }; #define SH73A0_PIN(pin, cfgs) \ @@ -3775,49 +3389,18 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(RESETA_N_PU_OFF), GPIO_FN(EDBGREQ_PD), GPIO_FN(EDBGREQ_PU), - - /* Functions with pull-ups */ - GPIO_FN(KEYIN0_PU), - GPIO_FN(KEYIN1_PU), - GPIO_FN(KEYIN2_PU), - GPIO_FN(KEYIN3_PU), - GPIO_FN(KEYIN4_PU), - GPIO_FN(KEYIN5_PU), - GPIO_FN(KEYIN6_PU), - GPIO_FN(KEYIN7_PU), - GPIO_FN(SDHICD0_PU), - GPIO_FN(SDHID0_0_PU), - GPIO_FN(SDHID0_1_PU), - GPIO_FN(SDHID0_2_PU), - GPIO_FN(SDHID0_3_PU), - GPIO_FN(SDHICMD0_PU), - GPIO_FN(SDHIWP0_PU), - GPIO_FN(SDHID1_0_PU), - GPIO_FN(SDHID1_1_PU), - GPIO_FN(SDHID1_2_PU), - GPIO_FN(SDHID1_3_PU), - GPIO_FN(SDHICMD1_PU), - GPIO_FN(SDHID2_0_PU), - GPIO_FN(SDHID2_1_PU), - GPIO_FN(SDHID2_2_PU), - GPIO_FN(SDHID2_3_PU), - GPIO_FN(SDHICMD2_PU), - GPIO_FN(MMCCMD0_PU), - GPIO_FN(MMCCMD1_PU), - GPIO_FN(MMCD0_0_PU), - GPIO_FN(MMCD0_1_PU), - GPIO_FN(MMCD0_2_PU), - GPIO_FN(MMCD0_3_PU), - GPIO_FN(MMCD0_4_PU), - GPIO_FN(MMCD0_5_PU), - GPIO_FN(MMCD0_6_PU), - GPIO_FN(MMCD0_7_PU), - GPIO_FN(FSIACK_PU), - GPIO_FN(FSIAILR_PU), - GPIO_FN(FSIAIBT_PU), - GPIO_FN(FSIAISLD_PU), }; +#undef PORTCR +#define PORTCR(nr, reg) \ + { \ + PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ @@ -4425,8 +4008,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { .ops = &sh73a0_pinmux_ops, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, From d28d6d1d0d0e119f55c55da2bfcb38d62ff1c2db Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:53:05 +0100 Subject: [PATCH 171/307] sh-pfc: sh73a0: Remove KEYSC function GPIOS All sh73a0 platforms now use the pinctrl API to control the KEYSC pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 30 ----------------------------- 1 file changed, 30 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 1249a3ffdb31..33e2b3f8f144 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2996,48 +2996,32 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(A0), \ GPIO_FN(BS_), GPIO_FN(A12), \ - GPIO_FN(PORT58_KEYOUT7), \ GPIO_FN(TPU4TO2), GPIO_FN(A13), \ - GPIO_FN(PORT59_KEYOUT6), \ GPIO_FN(TPU0TO1), GPIO_FN(A14), \ - GPIO_FN(KEYOUT5), GPIO_FN(A15), \ - GPIO_FN(KEYOUT4), GPIO_FN(A16), \ - GPIO_FN(KEYOUT3), \ GPIO_FN(MSIOF0_SS1), GPIO_FN(A17), \ - GPIO_FN(KEYOUT2), \ GPIO_FN(MSIOF0_TSYNC), GPIO_FN(A18), \ - GPIO_FN(KEYOUT1), \ GPIO_FN(MSIOF0_TSCK), GPIO_FN(A19), \ - GPIO_FN(KEYOUT0), \ GPIO_FN(MSIOF0_TXD), GPIO_FN(A20), \ - GPIO_FN(KEYIN0), \ GPIO_FN(MSIOF0_RSCK), GPIO_FN(A21), \ - GPIO_FN(KEYIN1), \ GPIO_FN(MSIOF0_RSYNC), GPIO_FN(A22), \ - GPIO_FN(KEYIN2), \ GPIO_FN(MSIOF0_MCK0), GPIO_FN(A23), \ - GPIO_FN(KEYIN3), \ GPIO_FN(MSIOF0_MCK1), GPIO_FN(A24), \ - GPIO_FN(KEYIN4), \ GPIO_FN(MSIOF0_RXD), GPIO_FN(A25), \ - GPIO_FN(KEYIN5), \ GPIO_FN(MSIOF0_SS2), GPIO_FN(A26), \ - GPIO_FN(KEYIN6), - GPIO_FN(KEYIN7), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), GPIO_FN(D2_NAF2), @@ -3105,13 +3089,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VIO_D0), \ GPIO_FN(PORT130_MSIOF2_RXD), \ GPIO_FN(VIO_D1), \ - GPIO_FN(PORT131_KEYOUT6), \ GPIO_FN(PORT131_MSIOF2_SS1), \ - GPIO_FN(PORT131_KEYOUT11), \ GPIO_FN(VIO_D2), \ - GPIO_FN(PORT132_KEYOUT7), \ GPIO_FN(PORT132_MSIOF2_SS2), \ - GPIO_FN(PORT132_KEYOUT10), \ GPIO_FN(VIO_D3), \ GPIO_FN(MSIOF2_TSYNC), \ GPIO_FN(VIO_D4), \ @@ -3119,14 +3099,10 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VIO_D5), \ GPIO_FN(MSIOF2_TSCK), \ GPIO_FN(VIO_D6), \ - GPIO_FN(PORT136_KEYOUT8), \ GPIO_FN(VIO_D7), \ - GPIO_FN(PORT137_KEYOUT9), \ GPIO_FN(VIO_D8), \ - GPIO_FN(PORT138_KEYOUT8), \ GPIO_FN(VIO2_D0), \ GPIO_FN(VIO_D9), \ - GPIO_FN(PORT139_KEYOUT9), \ GPIO_FN(VIO2_D1), \ GPIO_FN(VIO_D10), \ GPIO_FN(TPU0TO2), \ @@ -3135,14 +3111,10 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(TPU0TO3), \ GPIO_FN(VIO2_D3), \ GPIO_FN(VIO_D12), \ - GPIO_FN(PORT142_KEYOUT10), \ GPIO_FN(VIO2_D4), \ GPIO_FN(VIO_D13), \ - GPIO_FN(PORT143_KEYOUT11), \ - GPIO_FN(PORT143_KEYOUT6), \ GPIO_FN(VIO2_D5), \ GPIO_FN(VIO_D14), \ - GPIO_FN(PORT144_KEYOUT7), \ GPIO_FN(VIO2_D6), \ GPIO_FN(VIO_D15), \ GPIO_FN(TPU1TO3), \ @@ -3155,7 +3127,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(A27), \ GPIO_FN(PORT149_RDWR), \ GPIO_FN(MFG0_IN1), \ - GPIO_FN(PORT149_KEYOUT9), GPIO_FN(MFG0_IN2), GPIO_FN(TS_SPSYNC3), \ GPIO_FN(MSIOF2_RSCK), @@ -3383,7 +3354,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(IRQ9_MEM_INT), GPIO_FN(IRQ9_MCP_INT), GPIO_FN(A11), - GPIO_FN(KEYOUT8), GPIO_FN(TPU4TO3), GPIO_FN(RESETA_N_PU_ON), GPIO_FN(RESETA_N_PU_OFF), From 0ad6fe53678abf33b6d3d882688d0b82591cbc54 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:53:05 +0100 Subject: [PATCH 172/307] sh-pfc: sh73a0: Remove BSC function GPIOS All sh73a0 platforms now use the pinctrl API to control the BSC pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 33e2b3f8f144..7b010b6ce44e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3022,37 +3022,11 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(A25), \ GPIO_FN(MSIOF0_SS2), GPIO_FN(A26), \ - GPIO_FN(D0_NAF0), - GPIO_FN(D1_NAF1), - GPIO_FN(D2_NAF2), - GPIO_FN(D3_NAF3), - GPIO_FN(D4_NAF4), - GPIO_FN(D5_NAF5), - GPIO_FN(D6_NAF6), - GPIO_FN(D7_NAF7), - GPIO_FN(D8_NAF8), - GPIO_FN(D9_NAF9), - GPIO_FN(D10_NAF10), - GPIO_FN(D11_NAF11), - GPIO_FN(D12_NAF12), - GPIO_FN(D13_NAF13), - GPIO_FN(D14_NAF14), - GPIO_FN(D15_NAF15), - GPIO_FN(CS4_), - GPIO_FN(CS5A_), \ - GPIO_FN(PORT91_RDWR), - GPIO_FN(CS5B_), \ GPIO_FN(FCE1_), - GPIO_FN(CS6B_), \ GPIO_FN(DACK0), GPIO_FN(FCE0_), \ - GPIO_FN(CS6A_), GPIO_FN(WAIT_), \ GPIO_FN(DREQ0), - GPIO_FN(RD__FSC), - GPIO_FN(WE0__FWE), \ - GPIO_FN(RDWR_FWE), - GPIO_FN(WE1_), GPIO_FN(FRB), GPIO_FN(CKO), GPIO_FN(NBRSTOUT_), @@ -3125,7 +3099,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VIO2_FIELD), \ GPIO_FN(VIO_CKO), GPIO_FN(A27), \ - GPIO_FN(PORT149_RDWR), \ GPIO_FN(MFG0_IN1), \ GPIO_FN(MFG0_IN2), GPIO_FN(TS_SPSYNC3), \ From f03e4be625c652e12bc14e9f975ebcde9119a762 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:53:05 +0100 Subject: [PATCH 173/307] sh-pfc: sh73a0: Remove USB function GPIOS All sh73a0 platforms now use the pinctrl API to control the USB pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 7b010b6ce44e..273345ceaeec 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2936,11 +2936,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb), }; -#define PINMUX_FN_BASE GPIO_FN_VBUS_0 +#define PINMUX_FN_BASE GPIO_FN_GPI0 static const struct pinmux_func pinmux_func_gpios[] = { /* Table 25-1 (Functions 0-7) */ - GPIO_FN(VBUS_0), GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPI2), From f89fa856639398550528bebd307d4d5e1e625348 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:53:05 +0100 Subject: [PATCH 174/307] sh-pfc: sh73a0: Remove IrDA function GPIOS All sh73a0 platforms now use the pinctrl API to control the IrDA pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 273345ceaeec..cde4387edce1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2979,7 +2979,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(XWUP), GPIO_FN(VACK), GPIO_FN(XTAL1L), - GPIO_FN(PORT49_IRDA_OUT), \ GPIO_FN(PORT49_IROUT), \ GPIO_FN(BBIF2_TSYNC2), \ GPIO_FN(TPU2TO2), \ @@ -2987,9 +2986,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(BBIF2_TSCK2), \ GPIO_FN(TPU2TO3), \ GPIO_FN(BBIF2_TXD2), - GPIO_FN(PORT53_IRDA_IN), \ GPIO_FN(TPU3TO3), \ - GPIO_FN(PORT54_IRDA_FIRSEL), \ GPIO_FN(TPU3TO2), \ GPIO_FN(TPU0TO0), GPIO_FN(A0), \ @@ -3188,13 +3185,10 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VIO2_FIELD2), \ GPIO_FN(MSIOF1_SS2), \ GPIO_FN(VIO2_HD2), \ - GPIO_FN(PORT241_IRDA_OUT), \ GPIO_FN(PORT241_IROUT), \ GPIO_FN(MFG4_OUT1), \ GPIO_FN(TPU4TO0), - GPIO_FN(PORT242_IRDA_IN), \ GPIO_FN(MFG4_IN2), - GPIO_FN(PORT243_IRDA_FIRSEL), \ GPIO_FN(PORT243_VIO_CKO2), GPIO_FN(MFG2_IN1), \ GPIO_FN(MSIOF2R_RXD), From b56479f233d7205466037ebc8fb2d1851459c86c Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 13:07:05 +0100 Subject: [PATCH 175/307] sh-pfc: r8a7740: Remove LCD0 and LCD1 function GPIOS All r8a7740 platforms now use the pinctrl API to control the LCD0 and LCD1 pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 37 ---------------------------- 1 file changed, 37 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index a2f909a7c235..de1212d0912a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2313,43 +2313,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SCIFB_RTS_PORT172), GPIO_FN(SCIFB_CTS_PORT173), - /* LCD0 */ - GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2), - GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5), - GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8), - GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11), - GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14), - GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17), - GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC), - GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN), - GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP), - GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD), - GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS), - - GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162), - GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158), - GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159), - GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */ - - GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4), - GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2), - GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1), - GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */ - - /* LCD1 */ - GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2), - GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5), - GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8), - GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11), - GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14), - GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17), - GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20), - GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23), - GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS), - GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON), - GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN), - GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP), - /* RSPI */ GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), From 3dff629bd8b98759b2a652d0a2b9eda6fb085b18 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:36:28 +0100 Subject: [PATCH 176/307] sh-pfc: r8a7740: Remove SDHI and MMCIF function GPIOS All r8a7740 platforms now use the pinctrl API to control the SDHI and MMCIF pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 35 ---------------------------- 1 file changed, 35 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index de1212d0912a..3621d3e81fc3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2373,26 +2373,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ GPIO_FN(SIM_D_PORT199), - /* SDHI0 */ - GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2), - GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP), - GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK), - - /* SDHI1 */ - GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2), - GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP), - GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK), - - /* SDHI2 */ - GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2), - GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD), - - GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */ - GPIO_FN(SDHI2_WP_PORT25), - - GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */ - GPIO_FN(SDHI2_CD_PORT202), - /* MSIOF2 */ GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), @@ -2437,21 +2417,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), GPIO_FN(MEMC_A0), - /* MMC */ - GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69), - GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71), - GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73), - GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75), - GPIO_FN(MMC0_CLK_PORT66), - GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */ - - GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148), - GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146), - GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144), - GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142), - GPIO_FN(MMC1_CLK_PORT103), - GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */ - /* MSIOF0 */ GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), From 2a02818cbbbc0971312bdbe2971cbcb8092e445c Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 9 Jan 2013 22:32:25 +0100 Subject: [PATCH 177/307] sh-pfc: r8a7779: Remove DU1_DOTCLKOUT1 GPIO The function is not documented in the r8a7779 datasheet. Remove it. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 5b498ffaef03..f1fa355f5d0b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -353,7 +353,7 @@ enum { FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, - FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, + FN_TS_SCK1, FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, @@ -615,7 +615,7 @@ enum { HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, - VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK, + VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK, DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, @@ -1385,7 +1385,6 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), - PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1), PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), PINMUX_IPSR_DATA(IP11_26_24, TX2), @@ -2926,7 +2925,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP), GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), - GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1), + GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO), GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2), @@ -3634,7 +3633,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, /* IP11_26_24 [3] */ - FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1, + FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, /* IP11_23_21 [3] */ FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, From dd11cd3d1b92b5d4d8a1918a4cf58f6c335af6a4 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:36:28 +0100 Subject: [PATCH 178/307] sh-pfc: r8a7779: Remove SDHI and MMCIF function GPIOS All r8a7779 platforms now use the pinctrl API to control the SDHI and MMCIF pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 112 +++++++++++++-------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index f1fa355f5d0b..0a6500387bd8 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2678,16 +2678,16 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* IPSR0 */ GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), - GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2), - GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), - GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3), - GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), + GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), + GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), + GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), + GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D), GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D), GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), - GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD), - GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), - GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5), + GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), + GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), + GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B), GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT), GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0), @@ -2696,17 +2696,17 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C), /* IPSR1 */ - GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6), - GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7), - GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE), - GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD), + GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), + GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(FD7), + GPIO_FN(EX_CS2), GPIO_FN(FALE), + GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B), GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B), - GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0), - GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), + GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), + GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B), - GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1), - GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), + GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), + GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9), GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG), GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), @@ -2766,26 +2766,26 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), - GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), + GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1), - GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E), + GPIO_FN(PWM0), GPIO_FN(RX3_E_IRDA_RX_E), GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(VI2_G0), GPIO_FN(VI2_G1), GPIO_FN(VI2_G2), GPIO_FN(VI2_G3), GPIO_FN(VI2_G4), GPIO_FN(VI2_G5), - GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2), + GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), - GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3), + GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(VI2_G6), GPIO_FN(VI2_G7), GPIO_FN(VI2_R0), GPIO_FN(VI2_R1), GPIO_FN(VI2_R2), GPIO_FN(VI2_R3), - GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0), + GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(TX5), GPIO_FN(SCK0_D), /* IPSR5 */ GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), - GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), + GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), GPIO_FN(VI2_R4), GPIO_FN(VI2_R5), GPIO_FN(VI2_R6), GPIO_FN(VI2_R7), GPIO_FN(SCL2_D), GPIO_FN(SDA2_D), @@ -2794,14 +2794,14 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC), GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC), GPIO_FN(VI3_VSYNC), - GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD), + GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN), GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6), GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), - GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), + GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D), GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), @@ -2835,14 +2835,14 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7), GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), - GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK), - GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11), - GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1), - GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1), - GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1), - GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1), - GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2), - GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2), + GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), + GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(ATACS11), + GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1), + GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(ATAG1), + GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(ATARD1), + GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1), + GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(DREQ2), + GPIO_FN(RTS1_B_TANS_B), GPIO_FN(DACK2), GPIO_FN(CTS1_B), /* IPSR8 */ @@ -2859,46 +2859,46 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA), - GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB), + GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB), GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B), GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C), - GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B), + GPIO_FN(TX4_D), GPIO_FN(HSCK1_B), GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B), GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C), /* IPSR9 */ GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM), - GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3), - GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2), - GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6), - GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), - GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), + GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3), + GPIO_FN(VI0_DATA4_VI0_B4), + GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6), + GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), + GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2), GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1), GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1), - GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), - GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7), + GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), + GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4), - GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6), - GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B), + GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6), + GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0), - GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7), - GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9), + GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7), + GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9), /* IPSR10 */ GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C), GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), - GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2), + GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(IRQ2), GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), - GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), - GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B), + GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), + GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), - GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15), + GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15), GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC), GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK), GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7), @@ -2911,19 +2911,19 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SPV_TRST), GPIO_FN(SCL3), /* IPSR11 */ - GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST), + GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST), GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1), - GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), - GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2), + GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), + GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B), - GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN), + GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN), GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4), - GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), + GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), - GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), + GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), - GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), - GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP), + GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), + GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO), From c97c7464f9b131ab16ce3dd39f5ddf8eeb68d7c0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:36:28 +0100 Subject: [PATCH 179/307] sh-pfc: r8a7779: Remove SCIF function GPIOS All r8a7779 platforms now use the pinctrl API to control the SCIF pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 141 +++++++++++++-------------- 1 file changed, 69 insertions(+), 72 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 0a6500387bd8..ecc300db2370 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2677,61 +2677,61 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(A19), /* IPSR0 */ - GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), + GPIO_FN(USB_PENC2), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), - GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), - GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), - GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D), - GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D), + GPIO_FN(HCTS1), GPIO_FN(A0), + GPIO_FN(FD3), GPIO_FN(A20), + GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), + GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), GPIO_FN(SSI_WS78_B), GPIO_FN(A25), - GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B), - GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT), - GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0), + GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), + GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT), + GPIO_FN(PWM0_B), GPIO_FN(CS0), GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2), GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), - GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C), + GPIO_FN(VI1_R7), GPIO_FN(HRTS1), /* IPSR1 */ - GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), + GPIO_FN(EX_CS0), GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(FD7), GPIO_FN(EX_CS2), GPIO_FN(FALE), GPIO_FN(ATACS00), GPIO_FN(EX_CS3), - GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B), - GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B), + GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), + GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), - GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B), + GPIO_FN(HTX1), GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), - GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9), - GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG), - GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), - GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA), - GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2), + GPIO_FN(HRX1), GPIO_FN(SSI_WS9), + GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG), + GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), + GPIO_FN(HTX0), GPIO_FN(SDATA), + GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2), GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26), GPIO_FN(CC5_STATE34), /* IPSR2 */ - GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C), + GPIO_FN(HRX0), GPIO_FN(SCKZ), GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11), GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35), - GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5), - GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), + GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5), + GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16), GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0), - GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C), + GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B), - GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS), - GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), + GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), + GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0), GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), - GPIO_FN(TX5_C), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), - GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C), + GPIO_FN(LCDOUT1), GPIO_FN(DACK0), + GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3), GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5), GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7), @@ -2747,45 +2747,43 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16), GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), - GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C), + GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(LCDOUT18), GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20), GPIO_FN(LCDOUT21), GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23), - GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D), + GPIO_FN(QSTVA_QVS), GPIO_FN(SCL3_B), GPIO_FN(QCLK), - GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D), + GPIO_FN(QSTVB_QVE), GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B), GPIO_FN(QSTH_QHS), GPIO_FN(QSTB_QHE), GPIO_FN(QCPV_QDE), - GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), + GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), /* IPSR4 */ - GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), - GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), - GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), + GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), + GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), + GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), - GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), + GPIO_FN(AUDCK), GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1), - GPIO_FN(PWM0), GPIO_FN(RX3_E_IRDA_RX_E), - GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(VI2_G0), + GPIO_FN(PWM0), + GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0), GPIO_FN(VI2_G1), GPIO_FN(VI2_G2), GPIO_FN(VI2_G3), GPIO_FN(VI2_G4), GPIO_FN(VI2_G5), GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), - GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), + GPIO_FN(AUDATA6), GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), - GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), + GPIO_FN(AUDATA7), GPIO_FN(VI2_G6), GPIO_FN(VI2_G7), GPIO_FN(VI2_R0), GPIO_FN(VI2_R1), GPIO_FN(VI2_R2), GPIO_FN(VI2_R3), GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), - GPIO_FN(TX5), GPIO_FN(SCK0_D), /* IPSR5 */ GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), - GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), GPIO_FN(VI2_R4), GPIO_FN(VI2_R5), GPIO_FN(VI2_R6), GPIO_FN(VI2_R7), GPIO_FN(SCL2_D), GPIO_FN(SDA2_D), @@ -2794,15 +2792,15 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC), GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC), GPIO_FN(VI3_VSYNC), - GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), + GPIO_FN(VI2_CLK), GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), - GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN), + GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN), GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6), GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), - GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), - GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), + GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), + GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), - GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D), + GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0), @@ -2820,10 +2818,10 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B), GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9), GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK), - GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D), + GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D), GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11), - GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA), - GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6), + GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA), + GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B), /* IPSR7 */ @@ -2836,36 +2834,35 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), - GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(ATACS11), - GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1), - GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(ATAG1), - GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(ATARD1), - GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1), - GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(DREQ2), - GPIO_FN(RTS1_B_TANS_B), GPIO_FN(DACK2), - GPIO_FN(CTS1_B), + GPIO_FN(ATACS01), GPIO_FN(ATACS11), + GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1), + GPIO_FN(CC5_TRST), GPIO_FN(ATAG1), + GPIO_FN(CC5_TMS), GPIO_FN(ATARD1), + GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1), + GPIO_FN(CC5_TDI), GPIO_FN(DREQ2), + GPIO_FN(DACK2), /* IPSR8 */ - GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), + GPIO_FN(HSPI_CLK0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0), - GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), + GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0), - GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), + GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0), - GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), + GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA), GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB), - GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), - GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B), - GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C), - GPIO_FN(TX4_D), GPIO_FN(HSCK1_B), + GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), + GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B), + GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), + GPIO_FN(HSCK1_B), GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B), - GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C), + GPIO_FN(PWMFSW0_C), /* IPSR9 */ GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), @@ -2888,7 +2885,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9), /* IPSR10 */ - GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C), + GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), @@ -2926,22 +2923,22 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), - GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO), + GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO), GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), - GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2), + GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(HRTS0_B), /* IPSR12 */ GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1), - GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), + GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1), GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4), GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B), GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5), - GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B), + GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B), GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB), - GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), - GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B), + GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), + GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From 52c5d0327e101ff57d7a6be8a983a610588d7332 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:36:28 +0100 Subject: [PATCH 180/307] sh-pfc: r8a7779: Remove HSPI function GPIOS All r8a7779 platforms now use the pinctrl API to control the HSPI pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 54 ++++++++++++++-------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index ecc300db2370..ca59a187b021 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2682,16 +2682,16 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), GPIO_FN(HCTS1), GPIO_FN(A0), GPIO_FN(FD3), GPIO_FN(A20), - GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), - GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), - GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), - GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), - GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), + GPIO_FN(A21), + GPIO_FN(A22), + GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), + GPIO_FN(VI1_R1), GPIO_FN(A24), + GPIO_FN(FD4), GPIO_FN(VI1_R2), GPIO_FN(SSI_WS78_B), GPIO_FN(A25), - GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), + GPIO_FN(FD5), GPIO_FN(VI1_R3), GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT), GPIO_FN(PWM0_B), GPIO_FN(CS0), - GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2), + GPIO_FN(CS1_A26), GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), GPIO_FN(VI1_R7), GPIO_FN(HRTS1), @@ -2787,19 +2787,19 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VI2_R4), GPIO_FN(VI2_R5), GPIO_FN(VI2_R6), GPIO_FN(VI2_R7), GPIO_FN(SCL2_D), GPIO_FN(SDA2_D), - GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1), + GPIO_FN(VI2_CLKENB), GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD), GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC), GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC), GPIO_FN(VI3_VSYNC), GPIO_FN(VI2_CLK), - GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), + GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN), GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6), - GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), + GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), GPIO_FN(VI2_DATA7_VI2_B7), - GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), + GPIO_FN(VI1_FIELD), GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), @@ -2828,12 +2828,12 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), - GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C), + GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B), - GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7), + GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7), GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), - GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), - GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), + GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), + GPIO_FN(IRQ3_B), GPIO_FN(ATACS01), GPIO_FN(ATACS11), GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1), GPIO_FN(CC5_TRST), GPIO_FN(ATAG1), @@ -2843,15 +2843,15 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(DACK2), /* IPSR8 */ - GPIO_FN(HSPI_CLK0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), + GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), - GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0), + GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), - GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0), + GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), - GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0), + GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), @@ -2893,13 +2893,13 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), - GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), + GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), - GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15), + GPIO_FN(ARM_TRACEDATA_15), GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC), - GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK), + GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK), GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7), - GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B), + GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN), GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC), GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C), @@ -2916,12 +2916,12 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN), GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), - GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), + GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), - GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), + GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), - GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), - GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), + GPIO_FN(VI1_DATA7_VI1_B7), + GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO), GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), From e1114715f4dc2c6f75a9d6e25ebc519faa4437fb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:58:48 +0100 Subject: [PATCH 181/307] sh-pfc: r8a7779: Remove USB function GPIOS All r8a7779 platforms now use the pinctrl API to control the USB pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index ca59a187b021..6f8cc53c07d5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2677,7 +2677,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(A19), /* IPSR0 */ - GPIO_FN(USB_PENC2), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), + GPIO_FN(PWM1), GPIO_FN(PWMFSW0), GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), GPIO_FN(HCTS1), GPIO_FN(A0), @@ -2802,7 +2802,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VI1_FIELD), GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), - GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), + GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0), /* IPSR6 */ @@ -2843,10 +2843,10 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(DACK2), /* IPSR8 */ - GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), + GPIO_FN(AD_CLK), GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), - GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), + GPIO_FN(AD_DI), GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), From cb1f8abc79e16edf776627ae7f1c0e76762cc7fd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:58:48 +0100 Subject: [PATCH 182/307] sh-pfc: r8a7779: Remove LBSC function GPIOS All r8a7779 platforms now use the pinctrl API to control the LBSC pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 6f8cc53c07d5..5d6549953b4b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2690,22 +2690,20 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(FD5), GPIO_FN(VI1_R3), GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT), - GPIO_FN(PWM0_B), GPIO_FN(CS0), - GPIO_FN(CS1_A26), + GPIO_FN(PWM0_B), GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), GPIO_FN(VI1_R7), GPIO_FN(HRTS1), /* IPSR1 */ - GPIO_FN(EX_CS0), - GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(FD7), - GPIO_FN(EX_CS2), GPIO_FN(FALE), - GPIO_FN(ATACS00), GPIO_FN(EX_CS3), + GPIO_FN(FD6), GPIO_FN(FD7), + GPIO_FN(FALE), + GPIO_FN(ATACS00), GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), - GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), + GPIO_FN(SSI_SDATA9), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), GPIO_FN(HTX1), - GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), + GPIO_FN(SSI_SCK9), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), GPIO_FN(HRX1), GPIO_FN(SSI_WS9), GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG), From fdd7fc55f54ef0c811bdc2f9d81b25f6cf3085c7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:58:48 +0100 Subject: [PATCH 183/307] sh-pfc: r8a7779: Remove INTC function GPIOS All r8a7779 platforms now use the pinctrl API to control the INTC pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 5d6549953b4b..1d7b0dfbbb21 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2826,12 +2826,11 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), - GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), - GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B), + GPIO_FN(SSI_SCK9_B), + GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7), - GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), + GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), - GPIO_FN(IRQ3_B), GPIO_FN(ATACS01), GPIO_FN(ATACS11), GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1), GPIO_FN(CC5_TRST), GPIO_FN(ATAG1), @@ -2870,8 +2869,8 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), - GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2), - GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1), + GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2), + GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), @@ -2887,9 +2886,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), - GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(IRQ2), + GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), - GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), + GPIO_FN(ARM_TRACEDATA_13), GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), From f56314c4a17dbac6a5595ebe8fc49ae4f435dfbe Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:24:53 +0100 Subject: [PATCH 184/307] ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh7372.h | 29 -------------------- 1 file changed, 29 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index b582facc1cf6..7ded4ebaf5cc 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -294,21 +294,6 @@ enum { GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, - /* - * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89, - * 90, 91, 92, 99) - */ - GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2, - GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5, - GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7, - GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0, - - /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */ - GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2, - GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5, - GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7, - GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1, - /* SPU2 (PORT 65) */ GPIO_FN_VINT_I, @@ -416,20 +401,6 @@ enum { /* HDMI (PORT 169, 170) */ GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, - /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */ - GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0, - GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0, - GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1, - GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3, - - /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */ - GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0, - GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3, - - /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */ - GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0, - GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3, - /* SDENC see MSEL4CR 19 */ GPIO_FN_SDENC_CPG, GPIO_FN_SDENC_DV_CLKI, From 58e8353b8cc45aba3de87551e28b8870fc7014b7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 16:30:34 +0100 Subject: [PATCH 185/307] ARM: shmobile: sh73a0: Remove LCDC and LCDC2 function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 112 ++++++++----------- 1 file changed, 49 insertions(+), 63 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 4dca135f3aa8..a7b7a3c173bf 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -218,38 +218,33 @@ enum { GPIO_FN_PORT116_I2C_SDA3, GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, GPIO_FN_HSI_TX_FLAG, - GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ - GPIO_FN_LCD2D0, + GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD, - GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ - GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, - GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, + GPIO_FN_VIO_HD, + GPIO_FN_VIO2_HD, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ - GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, + GPIO_FN_PORT131_KEYOUT11, GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ - GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, - GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, - GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, - GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, - GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, - GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, + GPIO_FN_PORT132_KEYOUT10, + GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, + GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, + GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ - GPIO_FN_LCD2D6, GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ - GPIO_FN_LCD2D7, - GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, - GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, + GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, + GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ - GPIO_FN_LCD2D2, GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ - GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, + GPIO_FN_VIO2_D5, GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ - GPIO_FN_LCD2D4, - GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ - GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, - GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ - GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, - GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, + GPIO_FN_VIO2_D7, + GPIO_FN_VIO_CLK, + GPIO_FN_VIO2_CLK, + GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD, GPIO_FN_VIO_CKO, GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ GPIO_FN_PORT149_KEYOUT9, @@ -268,45 +263,38 @@ enum { GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ GPIO_FN_TPU3TO0, - GPIO_FN_LCDD0, - GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, - GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, - GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, - GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, - GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ + GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1, - GPIO_FN_LCDD6, - GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, - GPIO_FN_LCDD8, GPIO_FN_D16, - GPIO_FN_LCDD9, GPIO_FN_D17, - GPIO_FN_LCDD10, GPIO_FN_D18, - GPIO_FN_LCDD11, GPIO_FN_D19, - GPIO_FN_LCDD12, GPIO_FN_D20, - GPIO_FN_LCDD13, GPIO_FN_D21, - GPIO_FN_LCDD14, GPIO_FN_D22, - GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, - GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, - GPIO_FN_LCDD17, GPIO_FN_D25, - GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, - GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, - GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, - GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, - GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, - GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, - GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, - GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ - GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, - GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ + GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, + GPIO_FN_D16, + GPIO_FN_D17, + GPIO_FN_D18, + GPIO_FN_D19, + GPIO_FN_D20, + GPIO_FN_D21, + GPIO_FN_D22, + GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, + GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, + GPIO_FN_D25, + GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, + GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_DACK2, + GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, + GPIO_FN_DACK3, GPIO_FN_PORT218_VIO_CKOR, - GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ - GPIO_FN_LCD2DCK_2, - GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, - GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ + GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ - GPIO_FN_PORT221_LCD2HSYN, - GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ - GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, + GPIO_FN_DACK1, GPIO_FN_OVCN, + GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, @@ -318,13 +306,11 @@ enum { GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ - GPIO_FN_LCD2D20, GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ - GPIO_FN_LCD2D21, GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, - GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, - GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, + GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, + GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_SCIFA6_TXD, GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ GPIO_FN_TPU4TO0, From eeba9dd601708822148bce487723bd2de642eb8a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 16:30:34 +0100 Subject: [PATCH 186/307] ARM: shmobile: sh73a0: Remove SCIFA and SCIFB function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 90 ++++++++------------ 1 file changed, 37 insertions(+), 53 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index a7b7a3c173bf..b843cd7f83ec 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -103,15 +103,11 @@ enum { GPIO_FN_GPI5, GPIO_FN_GPI6, GPIO_FN_GPI7, - GPIO_FN_SCIFA7_RXD, - GPIO_FN_SCIFA7_CTS_, GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, - GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ + GPIO_FN_GPO5, GPIO_FN_FSICOSLDT3, GPIO_FN_PORT16_VIO_CKOR, - GPIO_FN_SCIFA0_TXD, - GPIO_FN_SCIFA7_TXD, - GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_PORT19_VIO_CKO2, GPIO_FN_GPO0, GPIO_FN_GPO1, GPIO_FN_GPO2, GPIO_FN_STATUS0, @@ -126,19 +122,15 @@ enum { GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, - GPIO_FN_SCIFA4_TXD, - GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, - GPIO_FN_SCIFA4_RTS_, - GPIO_FN_SCIFA4_CTS_, + GPIO_FN_XWUP, GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, GPIO_FN_FSIBOSLD, GPIO_FN_FSIBISLD, GPIO_FN_VACK, GPIO_FN_XTAL1L, - GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, - GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, + GPIO_FN_FSICOSLDT2, + GPIO_FN_FSICOSLDT1, GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, @@ -204,10 +196,9 @@ enum { GPIO_FN_BBIF2_RXD, GPIO_FN_BBIF2_SYNC, GPIO_FN_BBIF2_SCK, - GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, - GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, - GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, - GPIO_FN_SCIFA3_TXD, + GPIO_FN_MFG3_IN2, + GPIO_FN_MFG3_IN1, + GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1, GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, @@ -252,22 +243,17 @@ enum { GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, - GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, - GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, - GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, - GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, - GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, - GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, - GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, - GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, - GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, - GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ + GPIO_FN_MSIOF2_MCK0, + GPIO_FN_MSIOF2_MCK1, + GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_PORT157_MSIOF2_RXD, + GPIO_FN_DINT_, GPIO_FN_TS_SCK3, + GPIO_FN_NMI, GPIO_FN_TPU3TO0, - GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, - GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, - GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, - GPIO_FN_PORT196_SCIFA5_TXD, - GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, + GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_BBIF2_TSCK1, + GPIO_FN_BBIF2_TXD1, + GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_D16, @@ -296,36 +282,34 @@ enum { GPIO_FN_DACK1, GPIO_FN_OVCN, GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, - GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, - GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, - GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, - GPIO_FN_SCIFA1_RXD, - GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, - GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, - GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, - GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, - GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, - GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ + GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_IDIN, + GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, + GPIO_FN_MSIOF1_TSYNC, + GPIO_FN_MSIOF1_TSCK, + GPIO_FN_MSIOF1_RXD, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2, GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, - GPIO_FN_SCIFA6_TXD, GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ GPIO_FN_TPU4TO0, GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, - GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ - GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, - GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ - GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, - GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ - GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, - GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ - GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, - GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ - GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ + GPIO_FN_MFG2_IN1, + GPIO_FN_MSIOF2R_RXD, + GPIO_FN_MFG2_IN2, + GPIO_FN_MSIOF2R_TXD, + GPIO_FN_MFG1_OUT1, + GPIO_FN_TPU1TO0, + GPIO_FN_MFG3_OUT2, + GPIO_FN_TPU3TO1, + GPIO_FN_MFG2_OUT1, + GPIO_FN_TPU2TO0, GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, From 6fe59fa6fc7761df4cec644b87b3788f0587aaa5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 16:30:34 +0100 Subject: [PATCH 187/307] ARM: shmobile: sh73a0: Remove I2C function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index b843cd7f83ec..3d7950c95eba 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -115,9 +115,9 @@ enum { GPIO_FN_GPO4, GPIO_FN_STATUS2, GPIO_FN_VINT, GPIO_FN_TCKON, - GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ + GPIO_FN_XDVFS1, GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, - GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ + GPIO_FN_XDVFS2, GPIO_FN_PORT28_TPU1TO1, GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, @@ -203,10 +203,8 @@ enum { GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, - GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ - GPIO_FN_PORT115_I2C_SCL3, - GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ - GPIO_FN_PORT116_I2C_SDA3, + GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, + GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, GPIO_FN_HSI_TX_FLAG, GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD, @@ -292,8 +290,8 @@ enum { GPIO_FN_MSIOF1_RXD, GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2, GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ - GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, - GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, + GPIO_FN_MSIOF1_MCK0, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ @@ -310,9 +308,9 @@ enum { GPIO_FN_TPU3TO1, GPIO_FN_MFG2_OUT1, GPIO_FN_TPU2TO0, - GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, + GPIO_FN_MSIOF2R_TSCK, GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ - GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, + GPIO_FN_MSIOF2R_TSYNC, GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0, GPIO_FN_SDHID0_0, From 4c609d01fde27676bfed2a7bc9af5be0d8556e0a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 16:30:34 +0100 Subject: [PATCH 188/307] ARM: shmobile: sh73a0: Remove FSI function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 29 ++++++-------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 3d7950c95eba..563a48d7409e 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -105,7 +105,7 @@ enum { GPIO_FN_GPI7, GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, - GPIO_FN_GPO5, GPIO_FN_FSICOSLDT3, + GPIO_FN_GPO5, GPIO_FN_PORT16_VIO_CKOR, GPIO_FN_PORT19_VIO_CKO2, GPIO_FN_GPO0, @@ -123,29 +123,16 @@ enum { GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, GPIO_FN_XWUP, - GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, - GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, - GPIO_FN_FSIBOSLD, - GPIO_FN_FSIBISLD, GPIO_FN_VACK, GPIO_FN_XTAL1L, - GPIO_FN_FSICOSLDT2, - GPIO_FN_FSICOSLDT1, - GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, - GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, - GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, - GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, - GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ - GPIO_FN_FSIAOMC, - GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, + GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, + GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, - GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, - GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, - GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ - GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, - GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ - GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, - GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, + GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, + GPIO_FN_BBIF2_TXD2, + GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, + GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, + GPIO_FN_TPU0TO0, GPIO_FN_A0, GPIO_FN_BS_, GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, From 9c10a2096244fa42eb74edd504de943d02d0c17a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:32:00 +0100 Subject: [PATCH 189/307] ARM: shmobile: sh73a0: Remove pull-up function GPIOS Those GPIOs have been deprecated by the pinconf API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 41 -------------------- 1 file changed, 41 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 563a48d7409e..5b9620e3421a 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -397,47 +397,6 @@ enum { GPIO_FN_EDBGREQ_PD, GPIO_FN_EDBGREQ_PU, - /* Functions with pull-ups */ - GPIO_FN_KEYIN0_PU, - GPIO_FN_KEYIN1_PU, - GPIO_FN_KEYIN2_PU, - GPIO_FN_KEYIN3_PU, - GPIO_FN_KEYIN4_PU, - GPIO_FN_KEYIN5_PU, - GPIO_FN_KEYIN6_PU, - GPIO_FN_KEYIN7_PU, - GPIO_FN_SDHICD0_PU, - GPIO_FN_SDHID0_0_PU, - GPIO_FN_SDHID0_1_PU, - GPIO_FN_SDHID0_2_PU, - GPIO_FN_SDHID0_3_PU, - GPIO_FN_SDHICMD0_PU, - GPIO_FN_SDHIWP0_PU, - GPIO_FN_SDHID1_0_PU, - GPIO_FN_SDHID1_1_PU, - GPIO_FN_SDHID1_2_PU, - GPIO_FN_SDHID1_3_PU, - GPIO_FN_SDHICMD1_PU, - GPIO_FN_SDHID2_0_PU, - GPIO_FN_SDHID2_1_PU, - GPIO_FN_SDHID2_2_PU, - GPIO_FN_SDHID2_3_PU, - GPIO_FN_SDHICMD2_PU, - GPIO_FN_MMCCMD0_PU, - GPIO_FN_MMCCMD1_PU, - GPIO_FN_MMCD0_0_PU, - GPIO_FN_MMCD0_1_PU, - GPIO_FN_MMCD0_2_PU, - GPIO_FN_MMCD0_3_PU, - GPIO_FN_MMCD0_4_PU, - GPIO_FN_MMCD0_5_PU, - GPIO_FN_MMCD0_6_PU, - GPIO_FN_MMCD0_7_PU, - GPIO_FN_FSIACK_PU, - GPIO_FN_FSIAILR_PU, - GPIO_FN_FSIAIBT_PU, - GPIO_FN_FSIAISLD_PU, - /* end of GPIO */ GPIO_NR, }; From 385a94a40be99acbabdca44da0adb1e671a715d0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:55:16 +0100 Subject: [PATCH 190/307] ARM: shmobile: sh73a0: Remove KEYSC function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 53 +++++++++----------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 5b9620e3421a..f1b85ffd640e 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -134,22 +134,21 @@ enum { GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, GPIO_FN_TPU0TO0, GPIO_FN_A0, GPIO_FN_BS_, - GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, - GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, - GPIO_FN_A14, GPIO_FN_KEYOUT5, - GPIO_FN_A15, GPIO_FN_KEYOUT4, - GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, - GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, - GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, - GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, - GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, - GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, - GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, - GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, - GPIO_FN_A26, GPIO_FN_KEYIN6, - GPIO_FN_KEYIN7, + GPIO_FN_A12, GPIO_FN_TPU4TO2, + GPIO_FN_A13, GPIO_FN_TPU0TO1, + GPIO_FN_A14, + GPIO_FN_A15, + GPIO_FN_A16, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, GPIO_FN_D2_NAF2, @@ -199,23 +198,21 @@ enum { GPIO_FN_VIO_HD, GPIO_FN_VIO2_HD, GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, - GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ - GPIO_FN_PORT131_KEYOUT11, - GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ - GPIO_FN_PORT132_KEYOUT10, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2, GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, - GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, - GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ - GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ + GPIO_FN_VIO_D6, + GPIO_FN_VIO_D7, + GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0, + GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1, GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, - GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ - GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ + GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4, + GPIO_FN_VIO_D13, GPIO_FN_VIO2_D5, - GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ + GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6, GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_VIO2_D7, GPIO_FN_VIO_CLK, @@ -223,7 +220,6 @@ enum { GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD, GPIO_FN_VIO_CKO, GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ - GPIO_FN_PORT149_KEYOUT9, GPIO_FN_MFG0_IN2, GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, @@ -390,7 +386,6 @@ enum { GPIO_FN_IRQ9_MEM_INT, GPIO_FN_IRQ9_MCP_INT, GPIO_FN_A11, - GPIO_FN_KEYOUT8, GPIO_FN_TPU4TO3, GPIO_FN_RESETA_N_PU_ON, GPIO_FN_RESETA_N_PU_OFF, From ffa2a9d504b6145cf355a98b686254847d62a9a3 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:55:16 +0100 Subject: [PATCH 191/307] ARM: shmobile: sh73a0: Remove BSC function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 29 +++----------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index f1b85ffd640e..218e6b78397b 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -149,31 +149,10 @@ enum { GPIO_FN_A24, GPIO_FN_MSIOF0_RXD, GPIO_FN_A25, GPIO_FN_MSIOF0_SS2, GPIO_FN_A26, - GPIO_FN_D0_NAF0, - GPIO_FN_D1_NAF1, - GPIO_FN_D2_NAF2, - GPIO_FN_D3_NAF3, - GPIO_FN_D4_NAF4, - GPIO_FN_D5_NAF5, - GPIO_FN_D6_NAF6, - GPIO_FN_D7_NAF7, - GPIO_FN_D8_NAF8, - GPIO_FN_D9_NAF9, - GPIO_FN_D10_NAF10, - GPIO_FN_D11_NAF11, - GPIO_FN_D12_NAF12, - GPIO_FN_D13_NAF13, - GPIO_FN_D14_NAF14, - GPIO_FN_D15_NAF15, - GPIO_FN_CS4_, - GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, - GPIO_FN_CS5B_, GPIO_FN_FCE1_, - GPIO_FN_CS6B_, GPIO_FN_DACK0, - GPIO_FN_FCE0_, GPIO_FN_CS6A_, + GPIO_FN_FCE1_, + GPIO_FN_DACK0, + GPIO_FN_FCE0_, GPIO_FN_WAIT_, GPIO_FN_DREQ0, - GPIO_FN_RD__FSC, - GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, - GPIO_FN_WE1_, GPIO_FN_FRB, GPIO_FN_CKO, GPIO_FN_NBRSTOUT_, @@ -219,7 +198,7 @@ enum { GPIO_FN_VIO2_CLK, GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD, GPIO_FN_VIO_CKO, - GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ + GPIO_FN_A27, GPIO_FN_MFG0_IN1, GPIO_FN_MFG0_IN2, GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, From 097eb1c400b56a80e777536bd643185049b6a255 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:55:16 +0100 Subject: [PATCH 192/307] ARM: shmobile: sh73a0: Remove USB function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 218e6b78397b..d488e2b26e3f 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -94,8 +94,7 @@ enum { GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, /* Table 25-1 (Function 0-7) */ - GPIO_FN_VBUS_0 = 310, - GPIO_FN_GPI0, + GPIO_FN_GPI0 = 310, GPIO_FN_GPI1, GPIO_FN_GPI2, GPIO_FN_GPI3, From d363ca43f1ecec7a670a16470cdc5353cde39691 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Mar 2013 18:55:16 +0100 Subject: [PATCH 193/307] ARM: shmobile: sh73a0: Remove IrDA function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/sh73a0.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index d488e2b26e3f..fbc1584d6712 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -124,13 +124,13 @@ enum { GPIO_FN_XWUP, GPIO_FN_VACK, GPIO_FN_XTAL1L, - GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, + GPIO_FN_PORT49_IROUT, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_BBIF2_TXD2, - GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, - GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, + GPIO_FN_TPU3TO3, + GPIO_FN_TPU3TO2, GPIO_FN_TPU0TO0, GPIO_FN_A0, GPIO_FN_BS_, GPIO_FN_A12, GPIO_FN_TPU4TO2, @@ -255,10 +255,10 @@ enum { GPIO_FN_MSIOF1_MCK1, GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, - GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ + GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ GPIO_FN_TPU4TO0, - GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, - GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_VIO_CKO2, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2R_RXD, GPIO_FN_MFG2_IN2, From d3a6b8672df9935787471d281e2efb3d0cf8f43c Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 16:30:34 +0100 Subject: [PATCH 194/307] ARM: shmobile: r8a7740: Remove LCD0 and LCD1 function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7740.h | 39 ------------------- 1 file changed, 39 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index 59d252f4cf97..0c417da9be79 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -241,48 +241,9 @@ enum { /* LCD0 */ GPIO_FN_LCDC0_SELECT, - GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, - GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, - GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, - GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, - GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, - GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, - GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, - - GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ - GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ - - GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ - GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ - - GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, - GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, - GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, - GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ - - GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, - GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, - GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, - GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ /* LCD1 */ GPIO_FN_LCDC1_SELECT, - GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, - GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, - GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, - GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, - GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, - GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, - GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, - GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, - GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, - GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, - - GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ - GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ - - GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ - GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ /* RSPI */ GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, From ceb882ba296438a421a48a1fb833f5099c5fd8d5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:38:10 +0100 Subject: [PATCH 195/307] ARM: shmobile: r8a7740: Remove SDHI and MMCIF function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7740.h | 35 ------------------- 1 file changed, 35 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index 0c417da9be79..c2583610ad36 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -307,26 +307,6 @@ enum { GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ GPIO_FN_SIM_D_PORT199, - /* SDHI0 */ - GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, - GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, - GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, - - /* SDHI1 */ - GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, - GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, - GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, - - /* SDHI2 */ - GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, - GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, - - GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ - GPIO_FN_SDHI2_WP_PORT25, - - GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ - GPIO_FN_SDHI2_CD_PORT202, - /* MSIOF2 */ GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, @@ -378,21 +358,6 @@ enum { GPIO_FN_MEMC_DREQ1, GPIO_FN_MEMC_A0, - /* MMC */ - GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, - GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, - GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, - GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, - GPIO_FN_MMC0_CLK_PORT66, - GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ - - GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, - GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, - GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, - GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, - GPIO_FN_MMC1_CLK_PORT103, - GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ - /* MSIOF0 */ GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, From f19be10872e9971a1dd2860d575de1a802467e9d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 9 Jan 2013 22:32:25 +0100 Subject: [PATCH 196/307] ARM: shmobile: r8a7779: Remove DU1_DOTCLKOUT1 GPIO The function is not documented in the r8a7779 datasheet. Remove it. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 8ab0cd6ad6b0..badba5703f0b 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -308,7 +308,7 @@ enum { GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D, GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM, GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, - GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2, + GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2, GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1, GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2, GPIO_FN_HRTS0_B, From e4610a8d099d66c37cca5decc66add887b6301e9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Jan 2013 16:30:34 +0100 Subject: [PATCH 197/307] ARM: shmobile: r8a7779: Remove DU function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 88 +++++++++---------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index badba5703f0b..c25f66b5aaaa 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -119,76 +119,76 @@ enum { GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0, GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS, GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17, - GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0, + GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0, - GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0, + GPIO_FN_TX5_C, GPIO_FN_LCDOUT1, GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C, - GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3, - GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5, - GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7, - GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2, + GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3, + GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5, + GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7, + GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2, GPIO_FN_AUDATA2, /* IPSR3 */ - GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2, - GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3, - GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5, - GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7, - GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1, - GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1, + GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2, + GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10, + GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12, + GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14, + GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1, + GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B, - GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18, - GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20, - GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22, - GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN, + GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_LCDOUT18, + GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20, + GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22, + GPIO_FN_LCDOUT23, GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B, - GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1, + GPIO_FN_QCLK, GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B, GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B, - GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS, - GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, - GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_QSTH_QHS, + GPIO_FN_QSTB_QHE, + GPIO_FN_QCPV_QDE, GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON, /* IPSR4 */ - GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C, - GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C, - GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0, + GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C, + GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C, + GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK, GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B, - GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0, + GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0, GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC, - GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3, - GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5, - GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7, - GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2, + GPIO_FN_CTS0_D, GPIO_FN_VI2_G0, + GPIO_FN_VI2_G1, GPIO_FN_VI2_G2, + GPIO_FN_VI2_G3, GPIO_FN_VI2_G4, + GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6, - GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3, + GPIO_FN_TX0_D, GPIO_FN_VI2_DATA3_VI2_B3, GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7, - GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3, - GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5, - GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7, - GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4, + GPIO_FN_RX0_D, GPIO_FN_VI2_G6, + GPIO_FN_VI2_G7, GPIO_FN_VI2_R0, + GPIO_FN_VI2_R1, GPIO_FN_VI2_R2, + GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4, GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D, /* IPSR5 */ - GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B, + GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B, GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D, - GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5, - GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7, - GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D, - GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1, - GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD, - GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC, - GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC, - GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + GPIO_FN_VI2_R4, GPIO_FN_VI2_R5, + GPIO_FN_VI2_R6, GPIO_FN_VI2_R7, + GPIO_FN_SCL2_D, GPIO_FN_SDA2_D, + GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1, + GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD, + GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC, + GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC, + GPIO_FN_VI3_VSYNC, GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD, GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN, - GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6, + GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6, GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1, GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, - GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B, + GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B, GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, From 6c4950ad7f48b23ae4a993e2fbfb18c3a4cd7630 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:38:10 +0100 Subject: [PATCH 198/307] ARM: shmobile: r8a7779: Remove SDHI and MMCIF function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 104 +++++++++--------- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index c25f66b5aaaa..11fdb1bc6271 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -72,16 +72,16 @@ enum { /* IPSR0 */ GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0, - GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2, - GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, - GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3, - GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D, + GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, + GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, + GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, + GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D, GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B, GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0, GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1, - GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4, + GPIO_FN_A24, GPIO_FN_FD4, GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, - GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2, + GPIO_FN_FD5, GPIO_FN_HSPI_RX2, GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B, GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0, GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2, @@ -89,16 +89,16 @@ enum { GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C, /* IPSR1 */ - GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6, - GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7, - GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE, - GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD, + GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, + GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_FD7, + GPIO_FN_EX_CS2, GPIO_FN_FALE, + GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B, GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B, - GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0, + GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B, GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9, - GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1, + GPIO_FN_EX_CS5, GPIO_FN_FD1, GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E, GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2, GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4, @@ -154,26 +154,26 @@ enum { GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C, GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, - GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK, + GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0, - GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC, + GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC, GPIO_FN_CTS0_D, GPIO_FN_VI2_G0, GPIO_FN_VI2_G1, GPIO_FN_VI2_G2, GPIO_FN_VI2_G3, GPIO_FN_VI2_G4, GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2, - GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6, + GPIO_FN_SCL1_B, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6, GPIO_FN_TX0_D, GPIO_FN_VI2_DATA3_VI2_B3, - GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7, + GPIO_FN_SDA1_B, GPIO_FN_SCK5, GPIO_FN_AUDATA7, GPIO_FN_RX0_D, GPIO_FN_VI2_G6, GPIO_FN_VI2_G7, GPIO_FN_VI2_R0, GPIO_FN_VI2_R1, GPIO_FN_VI2_R2, GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4, - GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D, + GPIO_FN_SCL2_B, GPIO_FN_TX5, GPIO_FN_SCK0_D, /* IPSR5 */ GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B, - GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D, + GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D, GPIO_FN_VI2_R4, GPIO_FN_VI2_R5, GPIO_FN_VI2_R6, GPIO_FN_VI2_R7, GPIO_FN_SCL2_D, GPIO_FN_SDA2_D, @@ -182,14 +182,14 @@ enum { GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC, GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC, GPIO_FN_VI3_VSYNC, - GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD, + GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN, GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6, GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1, GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B, - GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, + GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0, @@ -222,13 +222,13 @@ enum { GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C, GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C, - GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD, - GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0, - GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1, - GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2, - GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3, - GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD, - GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2, + GPIO_FN_ATACS01, GPIO_FN_SCK1_B, + GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, + GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, + GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, + GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, + GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, + GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_DACK2, GPIO_FN_CTS1_B, /* IPSR8 */ @@ -245,44 +245,44 @@ enum { GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31, GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE, GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA, - GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C, + GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C, GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C, GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B, - GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B, + GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_HSCK1_B, GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B, GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C, /* IPSR9 */ GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO, GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM, - GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3, - GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2, - GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6, - GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7, - GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0, + GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3, + GPIO_FN_VI0_DATA4_VI0_B4, + GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6, + GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7, + GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0, GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2, GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1, GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1, - GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0, - GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7, + GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0, + GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4, - GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6, - GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B, + GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6, + GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0, - GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7, - GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9, + GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7, + GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9, /* IPSR10 */ GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B, GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1, GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11, GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK, - GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12, - GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3, + GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12, + GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_IRQ3, GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK, - GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14, + GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14, GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0, - GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15, + GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15, GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC, GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK, GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO, @@ -294,19 +294,19 @@ enum { GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3, /* IPSR11 */ - GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST, + GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST, GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1, - GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS, - GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2, + GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS, + GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B, - GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN, + GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN, GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4, - GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST, + GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST, GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5, - GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK, + GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK, GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6, - GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D, - GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM, + GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D, + GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM, GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2, GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1, From 7b69780d311a56639d1c3b790fa6d1daa7981b7f Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:38:10 +0100 Subject: [PATCH 199/307] ARM: shmobile: r8a7779: Remove SCIF function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 144 +++++++++--------- 1 file changed, 71 insertions(+), 73 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 11fdb1bc6271..e901316d9b2d 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -71,58 +71,58 @@ enum { GPIO_FN_A19, /* IPSR0 */ - GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0, + GPIO_FN_USB_PENC2, GPIO_FN_PWM1, GPIO_FN_PWMFSW0, GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, - GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, - GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D, - GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B, - GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0, + GPIO_FN_HCTS1, GPIO_FN_A0, + GPIO_FN_FD3, GPIO_FN_A20, + GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_HSPI_CLK2_B, + GPIO_FN_A22, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0, GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1, GPIO_FN_A24, GPIO_FN_FD4, GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, GPIO_FN_FD5, GPIO_FN_HSPI_RX2, - GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B, - GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0, + GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, GPIO_FN_CS0, GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2, GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0, - GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C, + GPIO_FN_VI1_R7, GPIO_FN_HRTS1, /* IPSR1 */ - GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, + GPIO_FN_EX_CS0, GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_FD7, GPIO_FN_EX_CS2, GPIO_FN_FALE, GPIO_FN_ATACS00, GPIO_FN_EX_CS3, - GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B, - GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B, + GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, + GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, - GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B, - GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9, + GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, + GPIO_FN_HTX1, GPIO_FN_SSI_SCK9, GPIO_FN_EX_CS5, GPIO_FN_FD1, - GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E, - GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2, - GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4, - GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0, - GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK, + GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, + GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2, + GPIO_FN_MLB_SIG, GPIO_FN_PWM3, + GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0, + GPIO_FN_SDATA, GPIO_FN_SUB_TCK, GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18, GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34, /* IPSR2 */ - GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C, + GPIO_FN_HRX0, GPIO_FN_SCKZ, GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11, GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35, - GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5, - GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO, + GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5, + GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO, GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16, - GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1, - GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C, + GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, + GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C, GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0, - GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS, + GPIO_FN_MDATA, GPIO_FN_SUB_TMS, GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17, GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0, - GPIO_FN_TX5_C, GPIO_FN_LCDOUT1, GPIO_FN_DACK0, - GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C, + GPIO_FN_LCDOUT1, GPIO_FN_DACK0, + GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3, GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5, GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7, @@ -137,43 +137,42 @@ enum { GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1, GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B, - GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_LCDOUT18, + GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18, GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20, GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22, GPIO_FN_LCDOUT23, - GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B, + GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B, GPIO_FN_QCLK, - GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B, + GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B, GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B, GPIO_FN_QSTH_QHS, GPIO_FN_QSTB_QHE, GPIO_FN_QCPV_QDE, - GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON, + GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON, /* IPSR4 */ - GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C, - GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C, - GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, + GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, + GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, + GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, - GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B, + GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0, - GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC, - GPIO_FN_CTS0_D, GPIO_FN_VI2_G0, + GPIO_FN_AUDSYNC, + GPIO_FN_VI2_G0, GPIO_FN_VI2_G1, GPIO_FN_VI2_G2, GPIO_FN_VI2_G3, GPIO_FN_VI2_G4, GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2, - GPIO_FN_SCL1_B, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6, - GPIO_FN_TX0_D, GPIO_FN_VI2_DATA3_VI2_B3, - GPIO_FN_SDA1_B, GPIO_FN_SCK5, GPIO_FN_AUDATA7, - GPIO_FN_RX0_D, GPIO_FN_VI2_G6, + GPIO_FN_SCL1_B, GPIO_FN_AUDATA6, + GPIO_FN_VI2_DATA3_VI2_B3, + GPIO_FN_SDA1_B, GPIO_FN_AUDATA7, + GPIO_FN_VI2_G6, GPIO_FN_VI2_G7, GPIO_FN_VI2_R0, GPIO_FN_VI2_R1, GPIO_FN_VI2_R2, GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4, - GPIO_FN_SCL2_B, GPIO_FN_TX5, GPIO_FN_SCK0_D, + GPIO_FN_SCL2_B, /* IPSR5 */ GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B, - GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D, GPIO_FN_VI2_R4, GPIO_FN_VI2_R5, GPIO_FN_VI2_R6, GPIO_FN_VI2_R7, GPIO_FN_SCL2_D, GPIO_FN_SDA2_D, @@ -182,15 +181,15 @@ enum { GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC, GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC, GPIO_FN_VI3_VSYNC, - GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, + GPIO_FN_VI2_CLK, GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, - GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN, + GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN, GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6, GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1, - GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, - GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B, + GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, + GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, - GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0, GPIO_FN_MOUT0, @@ -208,9 +207,9 @@ enum { GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B, GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C, GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10, - GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP, - GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5, - GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX, + GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP, + GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5, + GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B, /* IPSR7 */ @@ -222,35 +221,34 @@ enum { GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C, GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C, - GPIO_FN_ATACS01, GPIO_FN_SCK1_B, - GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, - GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, - GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, - GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, - GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, - GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_DACK2, - GPIO_FN_CTS1_B, + GPIO_FN_ATACS01, + GPIO_FN_ATACS11, GPIO_FN_CC5_TDO, + GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST, + GPIO_FN_ATAG1, GPIO_FN_CC5_TMS, + GPIO_FN_ATARD1, GPIO_FN_CC5_TCK, + GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI, + GPIO_FN_DREQ2, GPIO_FN_DACK2, /* IPSR8 */ - GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK, + GPIO_FN_HSPI_CLK0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK, GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20, GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0, - GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI, + GPIO_FN_USB_OVC1, GPIO_FN_AD_DI, GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21, GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0, - GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO, + GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO, GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22, GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0, - GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7, + GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7, GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31, GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE, GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA, - GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C, - GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C, + GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, + GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B, - GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_HSCK1_B, + GPIO_FN_HSCK1_B, GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B, - GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C, + GPIO_FN_PWMFSW0_C, /* IPSR9 */ GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO, @@ -273,7 +271,7 @@ enum { GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9, /* IPSR10 */ - GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B, + GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B, GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1, GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11, GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK, @@ -308,21 +306,21 @@ enum { GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D, GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM, GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, - GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2, + GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1, - GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2, + GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_HRTS0_B, /* IPSR12 */ GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1, - GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3, + GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3, GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B, GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C, GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5, - GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B, + GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B, GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB, - GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7, - GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B, + GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7, + GPIO_FN_GPS_MAG, GPIO_FN_FCE, }; struct platform_device; From 89fd785f2ad74f8b4a658a5b5608a559ac3dcfd5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Mar 2013 14:38:10 +0100 Subject: [PATCH 200/307] ARM: shmobile: r8a7779: Remove HSPI function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index e901316d9b2d..f3ae551bf2b7 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -76,15 +76,15 @@ enum { GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, GPIO_FN_HCTS1, GPIO_FN_A0, GPIO_FN_FD3, GPIO_FN_A20, - GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_HSPI_CLK2_B, - GPIO_FN_A22, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0, - GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1, + GPIO_FN_A21, + GPIO_FN_A22, GPIO_FN_VI1_R0, + GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1, GPIO_FN_A24, GPIO_FN_FD4, - GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, - GPIO_FN_FD5, GPIO_FN_HSPI_RX2, + GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, + GPIO_FN_FD5, GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, GPIO_FN_CS0, - GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2, + GPIO_FN_CS1_A26, GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0, GPIO_FN_VI1_R7, GPIO_FN_HRTS1, @@ -176,19 +176,19 @@ enum { GPIO_FN_VI2_R4, GPIO_FN_VI2_R5, GPIO_FN_VI2_R6, GPIO_FN_VI2_R7, GPIO_FN_SCL2_D, GPIO_FN_SDA2_D, - GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1, + GPIO_FN_VI2_CLKENB, GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD, GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC, GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC, GPIO_FN_VI3_VSYNC, GPIO_FN_VI2_CLK, - GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, + GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN, GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6, - GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1, + GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, GPIO_FN_VI2_DATA7_VI2_B7, - GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, + GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0, @@ -216,11 +216,11 @@ enum { GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B, GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B, GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B, - GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78, + GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78, GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B, - GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, - GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C, - GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C, + GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, + GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, + GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_ATACS01, GPIO_FN_ATACS11, GPIO_FN_CC5_TDO, GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST, @@ -230,15 +230,15 @@ enum { GPIO_FN_DREQ2, GPIO_FN_DACK2, /* IPSR8 */ - GPIO_FN_HSPI_CLK0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK, + GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK, GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20, - GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0, + GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI, GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21, - GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0, + GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO, GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22, - GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0, + GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7, GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31, GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE, @@ -278,13 +278,13 @@ enum { GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12, GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_IRQ3, GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK, - GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14, + GPIO_FN_ARM_TRACEDATA_14, GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0, - GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15, + GPIO_FN_ARM_TRACEDATA_15, GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC, - GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK, + GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK, GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO, - GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D, + GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D, GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D, GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4, GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC, @@ -300,12 +300,12 @@ enum { GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN, GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST, - GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5, + GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK, - GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6, - GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D, + GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6, + GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM, - GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, + GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1, GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, From 9cb5c048ca1139ea6292ea00ee9657cb157cce8b Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:59:26 +0100 Subject: [PATCH 201/307] ARM: shmobile: r8a7779: Remove USB function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index f3ae551bf2b7..e50bf53b0dec 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -71,7 +71,7 @@ enum { GPIO_FN_A19, /* IPSR0 */ - GPIO_FN_USB_PENC2, GPIO_FN_PWM1, GPIO_FN_PWMFSW0, + GPIO_FN_PWM1, GPIO_FN_PWMFSW0, GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, GPIO_FN_HCTS1, GPIO_FN_A0, @@ -191,7 +191,7 @@ enum { GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, - GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0, + GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0, GPIO_FN_MOUT0, /* IPSR6 */ @@ -230,10 +230,10 @@ enum { GPIO_FN_DREQ2, GPIO_FN_DACK2, /* IPSR8 */ - GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK, + GPIO_FN_AD_CLK, GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20, GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, - GPIO_FN_USB_OVC1, GPIO_FN_AD_DI, + GPIO_FN_AD_DI, GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21, GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO, From b1dbdbda766ab6e517606461adf6fbebd6769607 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:59:26 +0100 Subject: [PATCH 202/307] ARM: shmobile: r8a7779: Remove LBSC function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index e50bf53b0dec..688c0d223286 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -83,22 +83,20 @@ enum { GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, GPIO_FN_FD5, GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B, - GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, GPIO_FN_CS0, - GPIO_FN_CS1_A26, + GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0, GPIO_FN_VI1_R7, GPIO_FN_HRTS1, /* IPSR1 */ - GPIO_FN_EX_CS0, - GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_FD7, - GPIO_FN_EX_CS2, GPIO_FN_FALE, - GPIO_FN_ATACS00, GPIO_FN_EX_CS3, + GPIO_FN_FD6, GPIO_FN_FD7, + GPIO_FN_FALE, + GPIO_FN_ATACS00, GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, - GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, + GPIO_FN_SSI_SDATA9, GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_HTX1, GPIO_FN_SSI_SCK9, - GPIO_FN_EX_CS5, GPIO_FN_FD1, + GPIO_FN_FD1, GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, From a4339a9cb46644e19278e4dd5d89b262a37cb0b0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 13:59:26 +0100 Subject: [PATCH 203/307] ARM: shmobile: r8a7779: Remove INTC function GPIOs Those GPIOs have been deprecated by the pinctrl API. They are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 688c0d223286..8ea0ad18cdff 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -213,12 +213,12 @@ enum { /* IPSR7 */ GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B, GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B, - GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B, + GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78, - GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B, + GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, - GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, - GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, + GPIO_FN_TCLK1_C, + GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_ATACS01, GPIO_FN_ATACS11, GPIO_FN_CC5_TDO, GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST, @@ -256,8 +256,8 @@ enum { GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0, - GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2, - GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1, + GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2, + GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0, GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, @@ -273,8 +273,8 @@ enum { GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1, GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11, GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK, - GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12, - GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_IRQ3, + GPIO_FN_ARM_TRACEDATA_12, + GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK, GPIO_FN_ARM_TRACEDATA_14, GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0, From d75bc78b508d0a95d7738290d8ec9923691f4301 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 31 Jan 2013 02:45:01 +0100 Subject: [PATCH 204/307] r8a7779: Add Display Unit clock support Signed-off-by: Phil Edworthy [Rename device from to rcarfb to rcar-du] Signed-off-by: Laurent Pinchart [Manual conflict resolution] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7779.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 0f66d356e1bc..d9edeaf66007 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -88,7 +88,7 @@ static struct clk div4_clks[DIV4_NR] = { enum { MSTP323, MSTP322, MSTP321, MSTP320, MSTP115, - MSTP101, MSTP100, + MSTP103, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, MSTP014, @@ -101,6 +101,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ + [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ @@ -184,6 +185,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ + CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ }; void __init r8a7779_clock_init(void) From 443580486e3b96578928c1c91e8fbdcf0c9c9c7f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 23:28:34 +0900 Subject: [PATCH 205/307] irqchip: Renesas INTC External IRQ pin driver This patch adds a driver for external IRQ pins connected to the INTC block on recent SoCs from Renesas. The INTC hardware block usually contains a rather wide range of features ranging from external IRQ pin handling to legacy interrupt controller support. On older SoCs the INTC is used as a general purpose interrupt controller both for external IRQ pins and on-chip devices. On more recent ARM based SoCs with Cortex-A9 the main interrupt controller is the GIC, but IRQ trigger setup still need to happen in the INTC hardware block. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the INTC to the GIC. Tested on sh73a0 and r8a7779. The hardware varies quite a bit with SoC model, for instance register width and bitfield widths vary wildly. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 8 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by: Magnus Damm Acked-by: Thomas Gleixner Signed-off-by: Simon Horman --- drivers/irqchip/Kconfig | 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-intc-irqpin.c | 464 ++++++++++++++++++ .../platform_data/irq-renesas-intc-irqpin.h | 10 + 4 files changed, 479 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-intc-irqpin.c create mode 100644 include/linux/platform_data/irq-renesas-intc-irqpin.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index a350969e5efe..0f5f1c3825bc 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -25,6 +25,10 @@ config ARM_VIC_NR The maximum number of VICs available in the system, for power management. +config RENESAS_INTC_IRQPIN + bool + select IRQ_DOMAIN + config VERSATILE_FPGA_IRQ bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 98e3b87bdf1b..1aaa4073ab60 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o +obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c new file mode 100644 index 000000000000..1e5058a56517 --- /dev/null +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -0,0 +1,464 @@ +/* + * Renesas INTC External IRQ Pin Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */ + +#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */ +#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */ +#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ +#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ +#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ +#define INTC_IRQPIN_REG_NR 5 + +/* INTC external IRQ PIN hardware register access: + * + * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) + * PRIO is read-write 32-bit with 4-bits per IRQ (**) + * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) + * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) + * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) + * + * (*) May be accessed by more than one driver instance - lock needed + * (**) Read-modify-write access by one driver instance - lock needed + * (***) Accessed by one driver instance only - no locking needed + */ + +struct intc_irqpin_iomem { + void __iomem *iomem; + unsigned long (*read)(void __iomem *iomem); + void (*write)(void __iomem *iomem, unsigned long data); + int width; +}; + +struct intc_irqpin_irq { + int hw_irq; + int irq; + struct intc_irqpin_priv *p; +}; + +struct intc_irqpin_priv { + struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; + struct intc_irqpin_irq irq[INTC_IRQPIN_MAX]; + struct renesas_intc_irqpin_config config; + unsigned int number_of_irqs; + struct platform_device *pdev; + struct irq_chip irq_chip; + struct irq_domain *irq_domain; +}; + +static unsigned long intc_irqpin_read32(void __iomem *iomem) +{ + return ioread32(iomem); +} + +static unsigned long intc_irqpin_read8(void __iomem *iomem) +{ + return ioread8(iomem); +} + +static void intc_irqpin_write32(void __iomem *iomem, unsigned long data) +{ + iowrite32(data, iomem); +} + +static void intc_irqpin_write8(void __iomem *iomem, unsigned long data) +{ + iowrite8(data, iomem); +} + +static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, + int reg) +{ + struct intc_irqpin_iomem *i = &p->iomem[reg]; + return i->read(i->iomem); +} + +static inline void intc_irqpin_write(struct intc_irqpin_priv *p, + int reg, unsigned long data) +{ + struct intc_irqpin_iomem *i = &p->iomem[reg]; + i->write(i->iomem, data); +} + +static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, + int reg, int hw_irq) +{ + return BIT((p->iomem[reg].width - 1) - hw_irq); +} + +static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, + int reg, int hw_irq) +{ + intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); +} + +static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */ + +static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, + int reg, int shift, + int width, int value) +{ + unsigned long flags; + unsigned long tmp; + + raw_spin_lock_irqsave(&intc_irqpin_lock, flags); + + tmp = intc_irqpin_read(p, reg); + tmp &= ~(((1 << width) - 1) << shift); + tmp |= value << shift; + intc_irqpin_write(p, reg, tmp); + + raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags); +} + +static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, + int irq, int do_mask) +{ + int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ + int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ + + intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, + shift, bitfield_width, + do_mask ? 0 : (1 << bitfield_width) - 1); +} + +static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) +{ + int bitfield_width = p->config.sense_bitfield_width; + int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ + + dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); + + if (value >= (1 << bitfield_width)) + return -EINVAL; + + intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, + bitfield_width, value); + return 0; +} + +static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) +{ + dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", + str, i->irq, i->hw_irq, + irq_find_mapping(i->p->irq_domain, i->hw_irq)); +} + +static void intc_irqpin_irq_enable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "enable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); +} + +static void intc_irqpin_irq_disable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "disable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); +} + +static void intc_irqpin_irq_enable_force(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int irq = p->irq[irqd_to_hwirq(d)].irq; + + intc_irqpin_irq_enable(d); + irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); +} + +static void intc_irqpin_irq_disable_force(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int irq = p->irq[irqd_to_hwirq(d)].irq; + + irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); + intc_irqpin_irq_disable(d); +} + +#define INTC_IRQ_SENSE_VALID 0x10 +#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) + +static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = { + [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00), + [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01), + [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02), + [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03), + [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04), +}; + +static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK]; + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + + if (!(value & INTC_IRQ_SENSE_VALID)) + return -EINVAL; + + return intc_irqpin_set_sense(p, irqd_to_hwirq(d), + value ^ INTC_IRQ_SENSE_VALID); +} + +static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) +{ + struct intc_irqpin_irq *i = dev_id; + struct intc_irqpin_priv *p = i->p; + unsigned long bit; + + intc_irqpin_dbg(i, "demux1"); + bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); + + if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { + intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); + intc_irqpin_dbg(i, "demux2"); + generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq)); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct intc_irqpin_priv *p = h->host_data; + + intc_irqpin_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; +} + +static struct irq_domain_ops intc_irqpin_irq_domain_ops = { + .map = intc_irqpin_irq_domain_map, +}; + +static int intc_irqpin_probe(struct platform_device *pdev) +{ + struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data; + struct intc_irqpin_priv *p; + struct intc_irqpin_iomem *i; + struct resource *io[INTC_IRQPIN_REG_NR]; + struct resource *irq; + struct irq_chip *irq_chip; + void (*enable_fn)(struct irq_data *d); + void (*disable_fn)(struct irq_data *d); + const char *name = dev_name(&pdev->dev); + int ret; + int k; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + ret = -ENOMEM; + goto err0; + } + + /* deal with driver instance configuration */ + if (pdata) + memcpy(&p->config, pdata, sizeof(*pdata)); + if (!p->config.sense_bitfield_width) + p->config.sense_bitfield_width = 4; /* default to 4 bits */ + + p->pdev = pdev; + platform_set_drvdata(pdev, p); + + /* get hold of manadatory IOMEM */ + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { + io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); + if (!io[k]) { + dev_err(&pdev->dev, "not enough IOMEM resources\n"); + ret = -EINVAL; + goto err1; + } + } + + /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */ + for (k = 0; k < INTC_IRQPIN_MAX; k++) { + irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); + if (!irq) + break; + + p->irq[k].hw_irq = k; + p->irq[k].p = p; + p->irq[k].irq = irq->start; + } + + p->number_of_irqs = k; + if (p->number_of_irqs < 1) { + dev_err(&pdev->dev, "not enough IRQ resources\n"); + ret = -EINVAL; + goto err1; + } + + /* ioremap IOMEM and setup read/write callbacks */ + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { + i = &p->iomem[k]; + + switch (resource_size(io[k])) { + case 1: + i->width = 8; + i->read = intc_irqpin_read8; + i->write = intc_irqpin_write8; + break; + case 4: + i->width = 32; + i->read = intc_irqpin_read32; + i->write = intc_irqpin_write32; + break; + default: + dev_err(&pdev->dev, "IOMEM size mismatch\n"); + ret = -EINVAL; + goto err2; + } + + i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k])); + if (!i->iomem) { + dev_err(&pdev->dev, "failed to remap IOMEM\n"); + ret = -ENXIO; + goto err2; + } + } + + /* mask all interrupts using priority */ + for (k = 0; k < p->number_of_irqs; k++) + intc_irqpin_mask_unmask_prio(p, k, 1); + + /* use more severe masking method if requested */ + if (p->config.control_parent) { + enable_fn = intc_irqpin_irq_enable_force; + disable_fn = intc_irqpin_irq_disable_force; + } else { + enable_fn = intc_irqpin_irq_enable; + disable_fn = intc_irqpin_irq_disable; + } + + irq_chip = &p->irq_chip; + irq_chip->name = name; + irq_chip->irq_mask = disable_fn; + irq_chip->irq_unmask = enable_fn; + irq_chip->irq_enable = enable_fn; + irq_chip->irq_disable = disable_fn; + irq_chip->irq_set_type = intc_irqpin_irq_set_type; + irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; + + p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, + p->number_of_irqs, + p->config.irq_base, + &intc_irqpin_irq_domain_ops, p); + if (!p->irq_domain) { + ret = -ENXIO; + dev_err(&pdev->dev, "cannot initialize irq domain\n"); + goto err2; + } + + /* request and set priority on interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (request_irq(p->irq[k].irq, intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, "failed to request low IRQ\n"); + ret = -ENOENT; + goto err3; + } + intc_irqpin_mask_unmask_prio(p, k, 0); + } + + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); + + /* warn in case of mismatch if irq base is specified */ + if (p->config.irq_base) { + k = irq_find_mapping(p->irq_domain, 0); + if (p->config.irq_base != k) + dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", + p->config.irq_base, k); + } + + return 0; + +err3: + for (; k >= 0; k--) + free_irq(p->irq[k - 1].irq, &p->irq[k - 1]); + + irq_domain_remove(p->irq_domain); +err2: + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) + iounmap(p->iomem[k].iomem); +err1: + kfree(p); +err0: + return ret; +} + +static int intc_irqpin_remove(struct platform_device *pdev) +{ + struct intc_irqpin_priv *p = platform_get_drvdata(pdev); + int k; + + for (k = 0; k < p->number_of_irqs; k++) + free_irq(p->irq[k].irq, &p->irq[k]); + + irq_domain_remove(p->irq_domain); + + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) + iounmap(p->iomem[k].iomem); + + kfree(p); + return 0; +} + +static struct platform_driver intc_irqpin_device_driver = { + .probe = intc_irqpin_probe, + .remove = intc_irqpin_remove, + .driver = { + .name = "renesas_intc_irqpin", + } +}; + +static int __init intc_irqpin_init(void) +{ + return platform_driver_register(&intc_irqpin_device_driver); +} +postcore_initcall(intc_irqpin_init); + +static void __exit intc_irqpin_exit(void) +{ + platform_driver_unregister(&intc_irqpin_device_driver); +} +module_exit(intc_irqpin_exit); + +MODULE_AUTHOR("Magnus Damm"); +MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/irq-renesas-intc-irqpin.h b/include/linux/platform_data/irq-renesas-intc-irqpin.h new file mode 100644 index 000000000000..00ccac34dac8 --- /dev/null +++ b/include/linux/platform_data/irq-renesas-intc-irqpin.h @@ -0,0 +1,10 @@ +#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__ +#define __IRQ_RENESAS_INTC_IRQPIN_H__ + +struct renesas_intc_irqpin_config { + unsigned int sense_bitfield_width; + unsigned int irq_base; + bool control_parent; +}; + +#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */ From 1f4f11c671dacc219fae538ecf691fd212e295a6 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 12:00:59 +0900 Subject: [PATCH 206/307] ARM: shmobile: irq_pin() for static IRQ pin assignment Add the macro irq_pin() to let board-specific code using platform devices tie in external IRQn pins in a common way. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/irqs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 992ed213cec1..b2074e2acb15 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -12,4 +12,8 @@ #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) +/* External IRQ pins */ +#define IRQPIN_BASE 2000 +#define irq_pin(nr) ((nr) + IRQPIN_BASE) + #endif /* __ASM_MACH_IRQS_H */ From 341eb5465f67437ad37ef2f6302b581beda4614a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 12:01:09 +0900 Subject: [PATCH 207/307] ARM: shmobile: INTC External IRQ pin driver on sh73a0 Adjust the sh73a0 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ31. This removes quite a bit of special-case code in intc-sh73a0.c but the number of lines get replaced with platform device information in setup-sh73a0.c. The PFC code is also adjusted to make gpio_to_irq() return the correct interrupt number. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/board-kzm9g.c | 14 +-- arch/arm/mach-shmobile/intc-sh73a0.c | 117 ------------------------ arch/arm/mach-shmobile/setup-sh73a0.c | 126 ++++++++++++++++++++++++++ drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 6 +- 5 files changed, 137 insertions(+), 127 deletions(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 9255546e7bf6..f964accbce24 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -16,6 +16,7 @@ config ARCH_SH73A0 select CPU_V7 select I2C select SH_CLK_CPG + select RENESAS_INTC_IRQPIN config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 7f3a6b7e7b7c..d34d12ae496b 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -81,7 +81,7 @@ static struct resource smsc9221_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x260), /* IRQ3 */ + .start = irq_pin(3), /* IRQ3 */ .flags = IORESOURCE_IRQ, }, }; @@ -115,7 +115,7 @@ static struct resource usb_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x220), /* IRQ1 */ + .start = irq_pin(1), /* IRQ1 */ .flags = IORESOURCE_IRQ, }, }; @@ -138,7 +138,7 @@ struct usbhs_private { struct renesas_usbhs_platform_info info; }; -#define IRQ15 intcs_evt2irq(0x03e0) +#define IRQ15 irq_pin(15) #define USB_PHY_MODE (1 << 4) #define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) #define USB_PHY_ON (1 << 1) @@ -563,25 +563,25 @@ static struct i2c_board_info i2c0_devices[] = { }, { I2C_BOARD_INFO("ak8975", 0x0c), - .irq = intcs_evt2irq(0x3380), /* IRQ28 */ + .irq = irq_pin(28), /* IRQ28 */ }, { I2C_BOARD_INFO("adxl34x", 0x1d), - .irq = intcs_evt2irq(0x3340), /* IRQ26 */ + .irq = irq_pin(26), /* IRQ26 */ }, }; static struct i2c_board_info i2c1_devices[] = { { I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = intcs_evt2irq(0x300), /* IRQ8 */ + .irq = irq_pin(8), /* IRQ8 */ }, }; static struct i2c_board_info i2c3_devices[] = { { I2C_BOARD_INFO("pcf8575", 0x20), - .irq = intcs_evt2irq(0x3260), /* IRQ19 */ + .irq = irq_pin(19), /* IRQ19 */ .platform_data = &pcf8575_pdata, }, }; diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index a81a1d804e2e..19a26f4579b3 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } -#define RELOC_BASE 0x1200 - -/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */ -#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE) - -INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, - INTCS_VECT_RELOC, "sh73a0-intca-irq-pins"); - -static int to_gic_irq(struct irq_data *data) -{ - unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE; - - if (vect >= 0x3200) - vect -= 0x3000; - else - vect -= 0x0200; - - return gic_spi((vect >> 5) + 1); -} - -static int to_intca_reloc_irq(struct irq_data *data) -{ - return data->irq + (RELOC_BASE >> 5); -} - -#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq)) -#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p) - -static void intca_gic_enable(struct irq_data *data) -{ - irq_cb(irq_unmask, to_intca_reloc_irq(data)); - irq_cb(irq_unmask, to_gic_irq(data)); -} - -static void intca_gic_disable(struct irq_data *data) -{ - irq_cb(irq_mask, to_gic_irq(data)); - irq_cb(irq_mask, to_intca_reloc_irq(data)); -} - -static void intca_gic_mask_ack(struct irq_data *data) -{ - irq_cb(irq_mask, to_gic_irq(data)); - irq_cb(irq_mask_ack, to_intca_reloc_irq(data)); -} - -static void intca_gic_eoi(struct irq_data *data) -{ - irq_cb(irq_eoi, to_gic_irq(data)); -} - -static int intca_gic_set_type(struct irq_data *data, unsigned int type) -{ - return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type); -} - -#ifdef CONFIG_SMP -static int intca_gic_set_affinity(struct irq_data *data, - const struct cpumask *cpumask, - bool force) -{ - return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force); -} -#endif - -struct irq_chip intca_gic_irq_chip = { - .name = "INTCA-GIC", - .irq_mask = intca_gic_disable, - .irq_unmask = intca_gic_enable, - .irq_mask_ack = intca_gic_mask_ack, - .irq_eoi = intca_gic_eoi, - .irq_enable = intca_gic_enable, - .irq_disable = intca_gic_disable, - .irq_shutdown = intca_gic_disable, - .irq_set_type = intca_gic_set_type, - .irq_set_wake = sh73a0_set_wake, -#ifdef CONFIG_SMP - .irq_set_affinity = intca_gic_set_affinity, -#endif -}; - -static int to_intc_vect(int irq) -{ - unsigned int irq_pin = irq - gic_spi(1); - unsigned int offs; - - if (irq_pin < 16) - offs = 0x0200; - else - offs = 0x3000; - - return offs + (irq_pin << 5); -} - -static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id) -{ - generic_handle_irq(intcs_evt2irq(to_intc_vect(irq))); - return IRQ_HANDLED; -} - -static struct irqaction sh73a0_irq_pin_cascade[32]; - #define PINTER0_PHYS 0xe69000a0 #define PINTER1_PHYS 0xe69000a4 #define PINTER0_VIRT IOMEM(0xe69000a0) @@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void) void __iomem *gic_dist_base = IOMEM(0xf0001000); void __iomem *gic_cpu_base = IOMEM(0xf0000100); void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); - int k, n; gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = sh73a0_set_wake; register_intc_controller(&intcs_desc); - register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intc_pint0_desc); register_intc_controller(&intc_pint1_desc); @@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void) sh73a0_intcs_cascade.dev_id = intevtsa; setup_irq(gic_spi(50), &sh73a0_intcs_cascade); - /* IRQ pins require special handling through INTCA and GIC */ - for (k = 0; k < 32; k++) { - sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade"; - sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux; - setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); - - n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); - WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n); - irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, - handle_level_irq, "level"); - set_irq_flags(n, IRQF_VALID); /* yuck */ - } - /* PINT pins are sanely tied to the GIC as SPI */ sh73a0_pint0_cascade.name = "PINT0 cascade"; sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 2257a915746d..638735f78e36 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -811,6 +812,127 @@ static struct platform_device ipmmu_device = { .num_resources = ARRAY_SIZE(ipmmu_resources), }; +struct renesas_intc_irqpin_config irqpin0_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ +}; + +static struct resource irqpin0_resources[] = { + DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ + DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ + DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ + DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ + DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ + DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ + DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ + DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ + DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ +}; + +static struct platform_device irqpin0_device = { + .name = "renesas_intc_irqpin", + .id = 0, + .resource = irqpin0_resources, + .num_resources = ARRAY_SIZE(irqpin0_resources), + .dev = { + .platform_data = &irqpin0_platform_data, + }, +}; + +struct renesas_intc_irqpin_config irqpin1_platform_data = { + .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ + .control_parent = true, /* Disable spurious IRQ10 */ +}; + +static struct resource irqpin1_resources[] = { + DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ + DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ + DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ + DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ + DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ + DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ + DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ + DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ + DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ + DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ + DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ + DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ + DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ +}; + +static struct platform_device irqpin1_device = { + .name = "renesas_intc_irqpin", + .id = 1, + .resource = irqpin1_resources, + .num_resources = ARRAY_SIZE(irqpin1_resources), + .dev = { + .platform_data = &irqpin1_platform_data, + }, +}; + +struct renesas_intc_irqpin_config irqpin2_platform_data = { + .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ +}; + +static struct resource irqpin2_resources[] = { + DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ + DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ + DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ + DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ + DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ + DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ + DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ + DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ + DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ + DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ + DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ + DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ + DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ +}; + +static struct platform_device irqpin2_device = { + .name = "renesas_intc_irqpin", + .id = 2, + .resource = irqpin2_resources, + .num_resources = ARRAY_SIZE(irqpin2_resources), + .dev = { + .platform_data = &irqpin2_platform_data, + }, +}; + +struct renesas_intc_irqpin_config irqpin3_platform_data = { + .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ +}; + +static struct resource irqpin3_resources[] = { + DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ + DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ + DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ + DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ + DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ + DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ + DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ + DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ + DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ + DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ + DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ + DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ +}; + +static struct platform_device irqpin3_device = { + .name = "renesas_intc_irqpin", + .id = 3, + .resource = irqpin3_resources, + .num_resources = ARRAY_SIZE(irqpin3_resources), + .dev = { + .platform_data = &irqpin3_platform_data, + }, +}; + static struct platform_device *sh73a0_devices_dt[] __initdata = { &scif0_device, &scif1_device, @@ -839,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = { &dma0_device, &mpdma0_device, &pmu_device, + &irqpin0_device, + &irqpin1_device, + &irqpin2_device, + &irqpin3_device, }; #define SRCR2 IOMEM(0xe61580b0) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 709008e94124..6f15c03077a0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2733,9 +2733,9 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ -#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) -#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) +/* External IRQ pins mapped at IRQPIN_BASE */ +#define EXT_IRQ16L(n) irq_pin(n) +#define EXT_IRQ16H(n) irq_pin(n) static struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), From 8e56e6d5bfad8d07befe1026e49ff0046ef0b147 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 12:01:18 +0900 Subject: [PATCH 208/307] ARM: shmobile: INTC External IRQ pin driver on r8a7779 Update the r8a7779 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ3. The r8a7779 SoC can like older SH SoCs configure to use the IRQ0 -> IRQ3 signals as individual interrupts or a combined IRL mode. Without this patch the r8a7779 SoC code does not fully support external IRQ pins in individual IRQ mode. The r8a7779 PFC code does not yet have gpio_to_irq() support so no need to update such code. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by: Magnus Damm Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/intc-r8a7779.c | 53 +++++++++++++++++++- 3 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index f964accbce24..75d413c004b6 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -32,6 +32,7 @@ config ARCH_R8A7779 select SH_CLK_CPG select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI + select RENESAS_INTC_IRQPIN config ARCH_EMEV2 bool "Emma Mobile EV2" diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 86fcdf9fde1b..03f73def2fc6 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -61,6 +61,7 @@ extern void r8a7740_pm_init(void); extern void r8a7779_init_delay(void); extern void r8a7779_init_irq(void); +extern void r8a7779_init_irq_extpin(int irlm); extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index f9cc4bc9c798..fb0363ca4635 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -19,13 +19,16 @@ */ #include #include +#include #include #include #include #include -#include +#include #include +#include #include +#include #include #include #include @@ -39,6 +42,54 @@ #define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) +struct renesas_intc_irqpin_config irqpin0_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ + .sense_bitfield_width = 2, +}; + +static struct resource irqpin0_resources[] = { + DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ + DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ + DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ + DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ + DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ + DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ +}; + +static struct platform_device irqpin0_device = { + .name = "renesas_intc_irqpin", + .id = 0, + .resource = irqpin0_resources, + .num_resources = ARRAY_SIZE(irqpin0_resources), + .dev = { + .platform_data = &irqpin0_platform_data, + }, +}; + +void __init r8a7779_init_irq_extpin(int irlm) +{ + void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); + unsigned long tmp; + + if (icr0) { + tmp = ioread32(icr0); + if (irlm) + tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ + else + tmp &= ~(1 << 23); /* IRL mode - not supported */ + tmp |= (1 << 21); /* LVLMODE = 1 */ + iowrite32(tmp, icr0); + iounmap(icr0); + + if (irlm) + platform_device_register(&irqpin0_device); + } else + pr_warn("r8a7779: unable to setup external irq pin mode\n"); +} + static int r8a7779_set_wake(struct irq_data *data, unsigned int on) { return 0; /* always allow wakeup */ From 862d309883c69d67e1a2095e6f9e8ef35bf72dd6 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:58:44 +0900 Subject: [PATCH 209/307] irqchip: intc-irqpin: Whitespace fixes Remove whitespace damage and add newline between variables and code. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 1e5058a56517..4b5933fc0e3d 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -57,13 +57,13 @@ struct intc_irqpin_iomem { unsigned long (*read)(void __iomem *iomem); void (*write)(void __iomem *iomem, unsigned long data); int width; -}; +}; struct intc_irqpin_irq { int hw_irq; int irq; struct intc_irqpin_priv *p; -}; +}; struct intc_irqpin_priv { struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; @@ -99,6 +99,7 @@ static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, int reg) { struct intc_irqpin_iomem *i = &p->iomem[reg]; + return i->read(i->iomem); } @@ -106,6 +107,7 @@ static inline void intc_irqpin_write(struct intc_irqpin_priv *p, int reg, unsigned long data) { struct intc_irqpin_iomem *i = &p->iomem[reg]; + i->write(i->iomem, data); } @@ -405,7 +407,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", p->config.irq_base, k); } - + return 0; err3: From 33f958f2a71c44164698d1cae5463c0b85296a2c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:58:54 +0900 Subject: [PATCH 210/307] irqchip: intc-irqpin: Cache mapped IRQ Cache IRQ in domain_irq variable instead of making use of irq_find_mapping(). While at it rename the irq variable to requested_irq. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 30 ++++++++++++----------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 4b5933fc0e3d..0ac2bf683378 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -61,7 +61,8 @@ struct intc_irqpin_iomem { struct intc_irqpin_irq { int hw_irq; - int irq; + int requested_irq; + int domain_irq; struct intc_irqpin_priv *p; }; @@ -171,8 +172,7 @@ static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) { dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", - str, i->irq, i->hw_irq, - irq_find_mapping(i->p->irq_domain, i->hw_irq)); + str, i->requested_irq, i->hw_irq, i->domain_irq); } static void intc_irqpin_irq_enable(struct irq_data *d) @@ -196,7 +196,7 @@ static void intc_irqpin_irq_disable(struct irq_data *d) static void intc_irqpin_irq_enable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int irq = p->irq[irqd_to_hwirq(d)].irq; + int irq = p->irq[irqd_to_hwirq(d)].requested_irq; intc_irqpin_irq_enable(d); irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); @@ -205,7 +205,7 @@ static void intc_irqpin_irq_enable_force(struct irq_data *d) static void intc_irqpin_irq_disable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int irq = p->irq[irqd_to_hwirq(d)].irq; + int irq = p->irq[irqd_to_hwirq(d)].requested_irq; irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); intc_irqpin_irq_disable(d); @@ -246,7 +246,7 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); intc_irqpin_dbg(i, "demux2"); - generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq)); + generic_handle_irq(i->domain_irq); return IRQ_HANDLED; } return IRQ_NONE; @@ -257,6 +257,9 @@ static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, { struct intc_irqpin_priv *p = h->host_data; + p->irq[hw].domain_irq = virq; + p->irq[hw].hw_irq = hw; + intc_irqpin_dbg(&p->irq[hw], "map"); irq_set_chip_data(virq, h->host_data); irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); @@ -314,9 +317,8 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (!irq) break; - p->irq[k].hw_irq = k; p->irq[k].p = p; - p->irq[k].irq = irq->start; + p->irq[k].requested_irq = irq->start; } p->number_of_irqs = k; @@ -389,7 +391,8 @@ static int intc_irqpin_probe(struct platform_device *pdev) /* request and set priority on interrupts one by one */ for (k = 0; k < p->number_of_irqs; k++) { - if (request_irq(p->irq[k].irq, intc_irqpin_irq_handler, + if (request_irq(p->irq[k].requested_irq, + intc_irqpin_irq_handler, 0, name, &p->irq[k])) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; @@ -402,17 +405,16 @@ static int intc_irqpin_probe(struct platform_device *pdev) /* warn in case of mismatch if irq base is specified */ if (p->config.irq_base) { - k = irq_find_mapping(p->irq_domain, 0); - if (p->config.irq_base != k) + if (p->config.irq_base != p->irq[0].domain_irq) dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", - p->config.irq_base, k); + p->config.irq_base, p->irq[0].domain_irq); } return 0; err3: for (; k >= 0; k--) - free_irq(p->irq[k - 1].irq, &p->irq[k - 1]); + free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); irq_domain_remove(p->irq_domain); err2: @@ -430,7 +432,7 @@ static int intc_irqpin_remove(struct platform_device *pdev) int k; for (k = 0; k < p->number_of_irqs; k++) - free_irq(p->irq[k].irq, &p->irq[k]); + free_irq(p->irq[k].requested_irq, &p->irq[k]); irq_domain_remove(p->irq_domain); From d1b6aecde4ab146d115abcaf3bb1940d8e980b5a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:59:04 +0900 Subject: [PATCH 211/307] irqchip: intc-irqpin: Add force comments Add comments to describe the special case for "force" versions of enable and disable functions. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 0ac2bf683378..59c0cbccf212 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -199,6 +199,11 @@ static void intc_irqpin_irq_enable_force(struct irq_data *d) int irq = p->irq[irqd_to_hwirq(d)].requested_irq; intc_irqpin_irq_enable(d); + + /* enable interrupt through parent interrupt controller, + * assumes non-shared interrupt with 1:1 mapping + * needed for busted IRQs on some SoCs like sh73a0 + */ irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); } @@ -207,6 +212,10 @@ static void intc_irqpin_irq_disable_force(struct irq_data *d) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); int irq = p->irq[irqd_to_hwirq(d)].requested_irq; + /* disable interrupt through parent interrupt controller, + * assumes non-shared interrupt with 1:1 mapping + * needed for busted IRQs on some SoCs like sh73a0 + */ irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); intc_irqpin_irq_disable(d); } From 08eba5ba4f321c4b1806ecad0e626904f89263a1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:59:13 +0900 Subject: [PATCH 212/307] irqchip: intc-irqpin: Make use of devm functions Use devm_kzalloc(), devm_ioremap_nocache() and devm_request_irq() to simplify error handling. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 41 +++++++---------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 59c0cbccf212..21f46027f39a 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -294,7 +294,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) int ret; int k; - p = kzalloc(sizeof(*p), GFP_KERNEL); + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); if (!p) { dev_err(&pdev->dev, "failed to allocate driver data\n"); ret = -ENOMEM; @@ -316,7 +316,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (!io[k]) { dev_err(&pdev->dev, "not enough IOMEM resources\n"); ret = -EINVAL; - goto err1; + goto err0; } } @@ -334,7 +334,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (p->number_of_irqs < 1) { dev_err(&pdev->dev, "not enough IRQ resources\n"); ret = -EINVAL; - goto err1; + goto err0; } /* ioremap IOMEM and setup read/write callbacks */ @@ -355,14 +355,15 @@ static int intc_irqpin_probe(struct platform_device *pdev) default: dev_err(&pdev->dev, "IOMEM size mismatch\n"); ret = -EINVAL; - goto err2; + goto err0; } - i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k])); + i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start, + resource_size(io[k])); if (!i->iomem) { dev_err(&pdev->dev, "failed to remap IOMEM\n"); ret = -ENXIO; - goto err2; + goto err0; } } @@ -395,17 +396,17 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (!p->irq_domain) { ret = -ENXIO; dev_err(&pdev->dev, "cannot initialize irq domain\n"); - goto err2; + goto err0; } /* request and set priority on interrupts one by one */ for (k = 0; k < p->number_of_irqs; k++) { - if (request_irq(p->irq[k].requested_irq, - intc_irqpin_irq_handler, - 0, name, &p->irq[k])) { + if (devm_request_irq(&pdev->dev, p->irq[k].requested_irq, + intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; - goto err3; + goto err1; } intc_irqpin_mask_unmask_prio(p, k, 0); } @@ -421,16 +422,8 @@ static int intc_irqpin_probe(struct platform_device *pdev) return 0; -err3: - for (; k >= 0; k--) - free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); - - irq_domain_remove(p->irq_domain); -err2: - for (k = 0; k < INTC_IRQPIN_REG_NR; k++) - iounmap(p->iomem[k].iomem); err1: - kfree(p); + irq_domain_remove(p->irq_domain); err0: return ret; } @@ -438,17 +431,9 @@ static int intc_irqpin_probe(struct platform_device *pdev) static int intc_irqpin_remove(struct platform_device *pdev) { struct intc_irqpin_priv *p = platform_get_drvdata(pdev); - int k; - - for (k = 0; k < p->number_of_irqs; k++) - free_irq(p->irq[k].requested_irq, &p->irq[k]); irq_domain_remove(p->irq_domain); - for (k = 0; k < INTC_IRQPIN_REG_NR; k++) - iounmap(p->iomem[k].iomem); - - kfree(p); return 0; } From 0ca8712285e9e762ce4f5faf9f803b52e48c6837 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:59:23 +0900 Subject: [PATCH 213/307] irqchip: intc-irqpin: GPL header for platform data Add GPL header to platform data include file. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- .../platform_data/irq-renesas-intc-irqpin.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/platform_data/irq-renesas-intc-irqpin.h b/include/linux/platform_data/irq-renesas-intc-irqpin.h index 00ccac34dac8..e4cb911066a6 100644 --- a/include/linux/platform_data/irq-renesas-intc-irqpin.h +++ b/include/linux/platform_data/irq-renesas-intc-irqpin.h @@ -1,3 +1,22 @@ +/* + * Renesas INTC External IRQ Pin Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + #ifndef __IRQ_RENESAS_INTC_IRQPIN_H__ #define __IRQ_RENESAS_INTC_IRQPIN_H__ From fbc83b7f59dd8ed1154286b6de00b6d03c24a3c4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 27 Feb 2013 17:15:01 +0900 Subject: [PATCH 214/307] irqchip: Renesas IRQC driver This patch adds a driver for external IRQ pins connected to the IRQC hardware block on recent SoCs from Renesas. The IRQC hardware block is used together with more recent ARM based SoCs using the GIC. As usual the GIC requires external IRQ trigger setup somewhere else which in this particular case happens to be IRQC. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the IRQC to the GIC. Tested on r8a73a4 but is designed to work with a wide range of SoCs. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 32 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by: Magnus Damm Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/Kconfig | 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-irqc.c | 298 ++++++++++++++++++ .../linux/platform_data/irq-renesas-irqc.h | 27 ++ 4 files changed, 330 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-irqc.c create mode 100644 include/linux/platform_data/irq-renesas-irqc.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 0f5f1c3825bc..4a33351c25dc 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -29,6 +29,10 @@ config RENESAS_INTC_IRQPIN bool select IRQ_DOMAIN +config RENESAS_IRQC + bool + select IRQ_DOMAIN + config VERSATILE_FPGA_IRQ bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 1aaa4073ab60..e41ceb9bec22 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o +obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c new file mode 100644 index 000000000000..95d69bfac982 --- /dev/null +++ b/drivers/irqchip/irq-renesas-irqc.c @@ -0,0 +1,298 @@ +/* + * Renesas IRQC Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ + +#define IRQC_REQ_STS 0x00 +#define IRQC_EN_STS 0x04 +#define IRQC_EN_SET 0x08 +#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) +#define DETECT_STATUS 0x100 +#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) + +struct irqc_irq { + int hw_irq; + int requested_irq; + int domain_irq; + struct irqc_priv *p; +}; + +struct irqc_priv { + void __iomem *iomem; + void __iomem *cpu_int_base; + struct irqc_irq irq[IRQC_IRQ_MAX]; + struct renesas_irqc_config config; + unsigned int number_of_irqs; + struct platform_device *pdev; + struct irq_chip irq_chip; + struct irq_domain *irq_domain; +}; + +static void irqc_dbg(struct irqc_irq *i, char *str) +{ + dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", + str, i->requested_irq, i->hw_irq, i->domain_irq); +} + +static void irqc_irq_enable(struct irq_data *d) +{ + struct irqc_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + irqc_dbg(&p->irq[hw_irq], "enable"); + iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET); +} + +static void irqc_irq_disable(struct irq_data *d) +{ + struct irqc_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + irqc_dbg(&p->irq[hw_irq], "disable"); + iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); +} + +#define INTC_IRQ_SENSE_VALID 0x10 +#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) + +static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { + [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), + [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), + [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ + [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ + [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ +}; + +static int irqc_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct irqc_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK]; + unsigned long tmp; + + irqc_dbg(&p->irq[hw_irq], "sense"); + + if (!(value & INTC_IRQ_SENSE_VALID)) + return -EINVAL; + + tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); + tmp &= ~0x3f; + tmp |= value ^ INTC_IRQ_SENSE_VALID; + iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); + return 0; +} + +static irqreturn_t irqc_irq_handler(int irq, void *dev_id) +{ + struct irqc_irq *i = dev_id; + struct irqc_priv *p = i->p; + unsigned long bit = BIT(i->hw_irq); + + irqc_dbg(i, "demux1"); + + if (ioread32(p->iomem + DETECT_STATUS) & bit) { + iowrite32(bit, p->iomem + DETECT_STATUS); + irqc_dbg(i, "demux2"); + generic_handle_irq(i->domain_irq); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct irqc_priv *p = h->host_data; + + p->irq[hw].domain_irq = virq; + p->irq[hw].hw_irq = hw; + + irqc_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; +} + +static struct irq_domain_ops irqc_irq_domain_ops = { + .map = irqc_irq_domain_map, +}; + +static int irqc_probe(struct platform_device *pdev) +{ + struct renesas_irqc_config *pdata = pdev->dev.platform_data; + struct irqc_priv *p; + struct resource *io; + struct resource *irq; + struct irq_chip *irq_chip; + const char *name = dev_name(&pdev->dev); + int ret; + int k; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + ret = -ENOMEM; + goto err0; + } + + /* deal with driver instance configuration */ + if (pdata) + memcpy(&p->config, pdata, sizeof(*pdata)); + + p->pdev = pdev; + platform_set_drvdata(pdev, p); + + /* get hold of manadatory IOMEM */ + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!io) { + dev_err(&pdev->dev, "not enough IOMEM resources\n"); + ret = -EINVAL; + goto err1; + } + + /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */ + for (k = 0; k < IRQC_IRQ_MAX; k++) { + irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); + if (!irq) + break; + + p->irq[k].p = p; + p->irq[k].requested_irq = irq->start; + } + + p->number_of_irqs = k; + if (p->number_of_irqs < 1) { + dev_err(&pdev->dev, "not enough IRQ resources\n"); + ret = -EINVAL; + goto err1; + } + + /* ioremap IOMEM and setup read/write callbacks */ + p->iomem = ioremap_nocache(io->start, resource_size(io)); + if (!p->iomem) { + dev_err(&pdev->dev, "failed to remap IOMEM\n"); + ret = -ENXIO; + goto err2; + } + + p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */ + + irq_chip = &p->irq_chip; + irq_chip->name = name; + irq_chip->irq_mask = irqc_irq_disable; + irq_chip->irq_unmask = irqc_irq_enable; + irq_chip->irq_enable = irqc_irq_enable; + irq_chip->irq_disable = irqc_irq_disable; + irq_chip->irq_set_type = irqc_irq_set_type; + irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; + + p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, + p->number_of_irqs, + p->config.irq_base, + &irqc_irq_domain_ops, p); + if (!p->irq_domain) { + ret = -ENXIO; + dev_err(&pdev->dev, "cannot initialize irq domain\n"); + goto err2; + } + + /* request interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (request_irq(p->irq[k].requested_irq, irqc_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, "failed to request IRQ\n"); + ret = -ENOENT; + goto err3; + } + } + + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); + + /* warn in case of mismatch if irq base is specified */ + if (p->config.irq_base) { + if (p->config.irq_base != p->irq[0].domain_irq) + dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", + p->config.irq_base, p->irq[0].domain_irq); + } + + return 0; +err3: + for (; k >= 0; k--) + free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); + + irq_domain_remove(p->irq_domain); +err2: + iounmap(p->iomem); +err1: + kfree(p); +err0: + return ret; +} + +static int irqc_remove(struct platform_device *pdev) +{ + struct irqc_priv *p = platform_get_drvdata(pdev); + int k; + + for (k = 0; k < p->number_of_irqs; k++) + free_irq(p->irq[k].requested_irq, &p->irq[k]); + + irq_domain_remove(p->irq_domain); + iounmap(p->iomem); + kfree(p); + return 0; +} + +static struct platform_driver irqc_device_driver = { + .probe = irqc_probe, + .remove = irqc_remove, + .driver = { + .name = "renesas_irqc", + } +}; + +static int __init irqc_init(void) +{ + return platform_driver_register(&irqc_device_driver); +} +postcore_initcall(irqc_init); + +static void __exit irqc_exit(void) +{ + platform_driver_unregister(&irqc_device_driver); +} +module_exit(irqc_exit); + +MODULE_AUTHOR("Magnus Damm"); +MODULE_DESCRIPTION("Renesas IRQC Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/irq-renesas-irqc.h b/include/linux/platform_data/irq-renesas-irqc.h new file mode 100644 index 000000000000..3ae17b3e00ed --- /dev/null +++ b/include/linux/platform_data/irq-renesas-irqc.h @@ -0,0 +1,27 @@ +/* + * Renesas IRQC Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __IRQ_RENESAS_IRQC_H__ +#define __IRQ_RENESAS_IRQC_H__ + +struct renesas_irqc_config { + unsigned int irq_base; +}; + +#endif /* __IRQ_RENESAS_IRQC_H__ */ From 1461f8b62ffac3baaa955f74d4fe4a6166bfb4b3 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:08:31 +0900 Subject: [PATCH 215/307] ARM: shmobile: Make sh73a0 INTC irqpin platform data static The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh73a0.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 638735f78e36..e8cd93a5c550 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -812,7 +812,7 @@ static struct platform_device ipmmu_device = { .num_resources = ARRAY_SIZE(ipmmu_resources), }; -struct renesas_intc_irqpin_config irqpin0_platform_data = { +static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ }; @@ -842,7 +842,7 @@ static struct platform_device irqpin0_device = { }, }; -struct renesas_intc_irqpin_config irqpin1_platform_data = { +static struct renesas_intc_irqpin_config irqpin1_platform_data = { .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ .control_parent = true, /* Disable spurious IRQ10 */ }; @@ -873,7 +873,7 @@ static struct platform_device irqpin1_device = { }, }; -struct renesas_intc_irqpin_config irqpin2_platform_data = { +static struct renesas_intc_irqpin_config irqpin2_platform_data = { .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ }; @@ -903,7 +903,7 @@ static struct platform_device irqpin2_device = { }, }; -struct renesas_intc_irqpin_config irqpin3_platform_data = { +static struct renesas_intc_irqpin_config irqpin3_platform_data = { .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ }; From 7c9e3c7acd107b967495c44b984f855897caf518 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:10:06 +0900 Subject: [PATCH 216/307] ARM: shmobile: Make r8a7779 INTC irqpin platform data static The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/intc-r8a7779.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index fb0363ca4635..b86dc8908724 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -42,7 +42,7 @@ #define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) -struct renesas_intc_irqpin_config irqpin0_platform_data = { +static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ .sense_bitfield_width = 2, }; From 9d833bbe49953a9a07f9ebd7a9ad170c308bd692 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:16:08 +0900 Subject: [PATCH 217/307] irqchip: intc-irqpin: Initial DT support Add initial DT support to the INTC External IRQ Pin driver. At this point only hardware with 4-bit wide sense registers is supported via DT. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 21f46027f39a..fd5dabc2235d 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -278,6 +278,7 @@ static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, static struct irq_domain_ops intc_irqpin_irq_domain_ops = { .map = intc_irqpin_irq_domain_map, + .xlate = irq_domain_xlate_twocell, }; static int intc_irqpin_probe(struct platform_device *pdev) @@ -437,11 +438,19 @@ static int intc_irqpin_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id intc_irqpin_dt_ids[] = { + { .compatible = "renesas,intc-irqpin", }, + {}, +}; +MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); + static struct platform_driver intc_irqpin_device_driver = { .probe = intc_irqpin_probe, .remove = intc_irqpin_remove, .driver = { .name = "renesas_intc_irqpin", + .of_match_table = intc_irqpin_dt_ids, + .owner = THIS_MODULE, } }; From 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:23:39 +0900 Subject: [PATCH 218/307] irqchip: irqc: Add DT support Add DT support to the IRQC External IRQ Pin driver. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-irqc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c index 95d69bfac982..927bff373aac 100644 --- a/drivers/irqchip/irq-renesas-irqc.c +++ b/drivers/irqchip/irq-renesas-irqc.c @@ -145,6 +145,7 @@ static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, static struct irq_domain_ops irqc_irq_domain_ops = { .map = irqc_irq_domain_map, + .xlate = irq_domain_xlate_twocell, }; static int irqc_probe(struct platform_device *pdev) @@ -273,11 +274,19 @@ static int irqc_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id irqc_dt_ids[] = { + { .compatible = "renesas,irqc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, irqc_dt_ids); + static struct platform_driver irqc_device_driver = { .probe = irqc_probe, .remove = irqc_remove, .driver = { .name = "renesas_irqc", + .of_match_table = irqc_dt_ids, + .owner = THIS_MODULE, } }; From aee14423e79eddf3c4fa97d7015164d150b75e45 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 16 Jan 2013 08:54:18 +0100 Subject: [PATCH 219/307] ARM: shmobile: use GPIO SD-card detection on armadillo800eva Switch SDHI0 and SDHI1 SD-card interfaces on armadillo800eva to using GPIO card detection, which provides maximum power saving and automatically selects IRQ or polling mode, depending on the CD GPIO capability. Signed-off-by: Guennadi Liakhovetski Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-armadillo800eva.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 04eff93df793..60694e866d1a 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -579,10 +579,10 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\ - MMC_CAP_NEEDS_POLL, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, + .cd_gpio = GPIO_PORT167, }; static struct resource sdhi0_resources[] = { @@ -623,7 +623,9 @@ static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, + /* Port72 cannot generate IRQs, will be used in polling mode. */ + .cd_gpio = GPIO_PORT72, }; static struct resource sdhi1_resources[] = { From 3a5eed5f9e0734c4d3b5b42f7db443a33e2ba665 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 13 Feb 2013 11:34:03 +0100 Subject: [PATCH 220/307] ARM: shmobile: switch SDHI0 to GPIO regulator on armadillo800eva When regulators are used with MMC devices, explicitly provided OCR masks are ignored, they can be removed from platform data. Also switch SDHI0 from fixed regulator with hard-wired GPIO levels to a proper GPIO regulator instance to enable dynamic voltage switching. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- .../arm/mach-shmobile/board-armadillo800eva.c | 101 +++++++++++++++--- 1 file changed, 86 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 60694e866d1a..f322a18b55b6 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -28,8 +28,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -555,17 +557,94 @@ static struct platform_device gpio_keys_device = { }, }; -/* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */ -static struct regulator_consumer_supply fixed3v3_power_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = { REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), REGULATOR_SUPPLY("vmmc", "sh_mmcif"), REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), }; +/* Fixed 3.3V regulator to be used by SDHI0 */ +static struct regulator_consumer_supply vcc_sdhi0_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), +}; + +static struct regulator_init_data vcc_sdhi0_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), + .consumer_supplies = vcc_sdhi0_consumers, +}; + +static struct fixed_voltage_config vcc_sdhi0_info = { + .supply_name = "SDHI0 Vcc", + .microvolts = 3300000, + .gpio = GPIO_PORT75, + .enable_high = 1, + .init_data = &vcc_sdhi0_init_data, +}; + +static struct platform_device vcc_sdhi0 = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &vcc_sdhi0_info, + }, +}; + +/* 1.8 / 3.3V SDHI0 VccQ regulator */ +static struct regulator_consumer_supply vccq_sdhi0_consumers[] = { + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +}; + +static struct regulator_init_data vccq_sdhi0_init_data = { + .constraints = { + .input_uV = 3300000, + .min_uV = 1800000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vccq_sdhi0_consumers), + .consumer_supplies = vccq_sdhi0_consumers, +}; + +static struct gpio vccq_sdhi0_gpios[] = { + {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, +}; + +static struct gpio_regulator_state vccq_sdhi0_states[] = { + { .value = 3300000, .gpios = (0 << 0) }, + { .value = 1800000, .gpios = (1 << 0) }, +}; + +static struct gpio_regulator_config vccq_sdhi0_info = { + .supply_name = "vqmmc", + + .enable_gpio = GPIO_PORT74, + .enable_high = 1, + .enabled_at_boot = 0, + + .gpios = vccq_sdhi0_gpios, + .nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios), + + .states = vccq_sdhi0_states, + .nr_states = ARRAY_SIZE(vccq_sdhi0_states), + + .type = REGULATOR_VOLTAGE, + .init_data = &vccq_sdhi0_init_data, +}; + +static struct platform_device vccq_sdhi0 = { + .name = "gpio-regulator", + .id = -1, + .dev = { + .platform_data = &vccq_sdhi0_info, + }, +}; + /* SDHI0 */ /* * FIXME @@ -580,7 +659,6 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, - .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, .cd_gpio = GPIO_PORT167, }; @@ -622,7 +700,6 @@ static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, - .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, /* Port72 cannot generate IRQs, will be used in polling mode. */ .cd_gpio = GPIO_PORT72, @@ -673,7 +750,6 @@ static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = { /* MMCIF */ static struct sh_mmcif_plat_data sh_mmcif_plat = { .sup_pclk = 0, - .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, @@ -926,6 +1002,8 @@ static struct platform_device *eva_devices[] __initdata = { &fsi_wm8978_device, &fsi_hdmi_device, &i2c_gpio_device, + &vcc_sdhi0, + &vccq_sdhi0, }; static const struct pinctrl_map eva_pinctrl_map[] = { @@ -1060,13 +1138,6 @@ static void __init eva_init(void) usb = &usbhsf_device; } - /* SDHI0 */ - gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */ - gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */ - gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */ - - /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */ - /* CEU0 */ gpio_request(GPIO_FN_VIO0_D7, NULL); gpio_request(GPIO_FN_VIO0_D6, NULL); From 626a645eb75415255aad3162f4da3f6988f0c8ec Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 12 Feb 2013 18:15:33 +0100 Subject: [PATCH 221/307] ARM: shmobile: streamline mackerel SD and MMC devices This patch fixes the following issues with SD and MMC interfaces on mackerel: 1. replace custom card-detection functions with standard GPIO CD API 2. resources don't have to be numbered 3. add SDHI interrupt names 4. remove OCR masks, where regulators are used 5. only specify SDHI CD interrupts on interfaces where a CD pin is present - SDHI0 6. don't instantiate an MMCIF device and initialise MMCIF pins if SDHI1 is selected Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 113 ++++++++++++------------ 1 file changed, 57 insertions(+), 56 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 336ccb4a0f2a..fb058c763a7d 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -963,15 +963,6 @@ static struct platform_device nand_flash_device = { }, }; -/* - * The card detect pin of the top SD/MMC slot (CN7) is active low and is - * connected to GPIO A22 of SH7372 (GPIO 41). - */ -static int slot_cn7_get_cd(struct platform_device *pdev) -{ - return !gpio_get_value(41); -} - /* SDHI0 */ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, @@ -982,21 +973,21 @@ static struct sh_mobile_sdhi_info sdhi0_info = { }; static struct resource sdhi0_resources[] = { - [0] = { + { .name = "SDHI0", .start = 0xe6850000, .end = 0xe68500ff, .flags = IORESOURCE_MEM, - }, - [1] = { + }, { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */, .flags = IORESOURCE_IRQ, - }, - [2] = { + }, { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, .flags = IORESOURCE_IRQ, - }, - [3] = { + }, { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, .flags = IORESOURCE_IRQ, }, @@ -1014,34 +1005,28 @@ static struct platform_device sdhi0_device = { #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) /* SDHI1 */ + +/* GPIO_PORT41 can trigger IRQ8, but it is used by USBHS1, we have to poll */ static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, - .tmio_ocr_mask = MMC_VDD_165_195, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL, - .get_cd = slot_cn7_get_cd, + .cd_gpio = GPIO_PORT41, }; static struct resource sdhi1_resources[] = { - [0] = { + { .name = "SDHI1", .start = 0xe6860000, .end = 0xe68600ff, .flags = IORESOURCE_MEM, - }, - [1] = { - .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, - .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ - .flags = IORESOURCE_IRQ, - }, - [2] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ .flags = IORESOURCE_IRQ, - }, - [3] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ .flags = IORESOURCE_IRQ, @@ -1059,43 +1044,32 @@ static struct platform_device sdhi1_device = { }; #endif +/* SDHI2 */ + /* * The card detect pin of the top SD/MMC slot (CN23) is active low and is - * connected to GPIO SCIFB_SCK of SH7372 (162). + * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162). */ -static int slot_cn23_get_cd(struct platform_device *pdev) -{ - return !gpio_get_value(162); -} - -/* SDHI2 */ static struct sh_mobile_sdhi_info sdhi2_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL, - .get_cd = slot_cn23_get_cd, + .cd_gpio = GPIO_PORT162, }; static struct resource sdhi2_resources[] = { - [0] = { + { .name = "SDHI2", .start = 0xe6870000, .end = 0xe68700ff, .flags = IORESOURCE_MEM, - }, - [1] = { - .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, - .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */ - .flags = IORESOURCE_IRQ, - }, - [2] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ .flags = IORESOURCE_IRQ, - }, - [3] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ .flags = IORESOURCE_IRQ, @@ -1134,11 +1108,12 @@ static struct resource sh_mmcif_resources[] = { static struct sh_mmcif_plat_data sh_mmcif_plat = { .sup_pclk = 0, - .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NEEDS_POLL, - .get_cd = slot_cn7_get_cd, + .use_cd_gpio = true, + /* card detect pin for SD/MMC slot (CN7) */ + .cd_gpio = GPIO_PORT41, .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; @@ -1263,9 +1238,10 @@ static struct platform_device *mackerel_devices[] __initdata = { &sdhi0_device, #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) &sdhi1_device, +#else + &sh_mmcif_device, #endif &sdhi2_device, - &sh_mmcif_device, &ceu_device, &mackerel_camera, &hdmi_device, @@ -1372,10 +1348,11 @@ static void __init mackerel_init(void) { "A3SP", &usbhs0_device, }, { "A3SP", &usbhs1_device, }, { "A3SP", &nand_flash_device, }, - { "A3SP", &sh_mmcif_device, }, { "A3SP", &sdhi0_device, }, #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) { "A3SP", &sdhi1_device, }, +#else + { "A3SP", &sh_mmcif_device, }, #endif { "A3SP", &sdhi2_device, }, { "A4R", &ceu_device, }, @@ -1486,11 +1463,35 @@ static void __init mackerel_init(void) /* SDHI0 PORT172 card-detect IRQ26 */ gpio_request(GPIO_FN_IRQ26_172, NULL); - /* card detect pin for MMC slot (CN7) */ - gpio_request_one(41, GPIOF_IN, NULL); +#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) + /* enable SDHI1 */ + gpio_request(GPIO_FN_SDHICMD1, NULL); + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHID1_3, NULL); + gpio_request(GPIO_FN_SDHID1_2, NULL); + gpio_request(GPIO_FN_SDHID1_1, NULL); + gpio_request(GPIO_FN_SDHID1_0, NULL); +#else + /* MMCIF */ + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request(GPIO_FN_MMCCLK0, NULL); +#endif - /* card detect pin for microSD slot (CN23) */ - gpio_request_one(162, GPIOF_IN, NULL); + /* enable SDHI2 */ + gpio_request(GPIO_FN_SDHICMD2, NULL); + gpio_request(GPIO_FN_SDHICLK2, NULL); + gpio_request(GPIO_FN_SDHID2_3, NULL); + gpio_request(GPIO_FN_SDHID2_2, NULL); + gpio_request(GPIO_FN_SDHID2_1, NULL); + gpio_request(GPIO_FN_SDHID2_0, NULL); /* FLCTL */ gpio_request(GPIO_FN_D0_NAF0, NULL); From b3425eb9df0a57f0b4ce0ad66831028f6ffe1615 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Feb 2013 23:26:54 +0100 Subject: [PATCH 222/307] ARM: shmobile: mark mackerel sh_mmcif_device __maybe_unused Patch eac036ef9e "ARM: shmobile: streamline mackerel SD and MMC devices" made the use of the sh_mmcif_device variable for mackarel optional, but the definition is always provided, causing a build warning. arch/arm/mach-shmobile/board-mackerel.c:1120:31: warning: 'sh_mmcif_device' defined but not used [-Wunused-variable] Marking the variable as __maybe_unused will do the right thing here. Signed-off-by: Arnd Bergmann Cc: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index fb058c763a7d..ef22ec4dafae 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1118,7 +1118,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; -static struct platform_device sh_mmcif_device = { +static struct platform_device sh_mmcif_device __maybe_unused = { .name = "sh_mmcif", .id = 0, .dev = { From 73d6a69e3b3ae168fcb8d797e427c1b5fe132a40 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 29 Jan 2013 11:40:18 +0900 Subject: [PATCH 223/307] ARM: shmobile: marzen: Reference DT implementation Provide alternate board code for the marzen to demonstrate how DT may be used given the current state of driver device tree support. This is intended to act as a reference for mach-shmobile developers. Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/r8a7779-marzen-reference.dts | 47 ++++++++++++ arch/arm/mach-shmobile/Kconfig | 13 ++++ arch/arm/mach-shmobile/Makefile | 1 + .../mach-shmobile/board-marzen-reference.c | 75 +++++++++++++++++++ 5 files changed, 137 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts create mode 100644 arch/arm/mach-shmobile/board-marzen-reference.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c6255884cbb..7965b9ad99d9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ ccu9540.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7779-marzen-reference.dtb \ sh73a0-kzm9g.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts new file mode 100644 index 000000000000..72be4c87cfb5 --- /dev/null +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -0,0 +1,47 @@ +/* + * Reference Device Tree Source for the Marzen board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "r8a7779.dtsi" + +/ { + model = "marzen"; + compatible = "renesas,marzen-reference", "renesas,r8a7779"; + + chosen { + bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + fixedregulator3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lan0@18000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x18000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = <0 28 0x4>; + reg-io-width = <4>; + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 9255546e7bf6..b15d4ffcd9a2 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -102,6 +102,19 @@ config MACH_MARZEN select ARCH_REQUIRE_GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR +config MACH_MARZEN_REFERENCE + bool "MARZEN board - Reference Device Tree Implementation" + depends on ARCH_R8A7779 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select USE_OF + ---help--- + Use reference implementation of Marzen board support + which makes use of device tree at the expense + of not supporting a number of devices. + + This is intended to aid developers + config MACH_KZM9D bool "KZM9D board" depends on ARCH_EMEV2 diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index b646ff4d742a..3705d4f7096b 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_KOTA2) += board-kota2.o obj-$(CONFIG_MACH_BONITO) += board-bonito.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o +obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c new file mode 100644 index 000000000000..480d882e42c7 --- /dev/null +++ b/arch/arm/mach-shmobile/board-marzen-reference.c @@ -0,0 +1,75 @@ +/* + * marzen board support - Reference DT implementation + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * Copyright (C) 2013 Simon Horman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +static const struct pinctrl_map marzen_pinctrl_map[] = { + /* SCIF2 (CN18: DEBUG0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", + "scif2_data_c", "scif2"), + /* SCIF4 (CN19: DEBUG1) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779", + "scif4_data", "scif4"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_cd", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", + "sdhi0_wp", "sdhi0"), + /* SMSC */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", + "intc_irq1_b", "intc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", + "lbsc_ex_cs0", "lbsc"), +}; + +static void __init marzen_init(void) +{ + pinctrl_register_mappings(marzen_pinctrl_map, + ARRAY_SIZE(marzen_pinctrl_map)); + r8a7779_pinmux_init(); + + r8a7779_add_standard_devices_dt(); +} + +static const char *marzen_boards_compat_dt[] __initdata = { + "renesas,marzen-reference", + NULL, +}; + +DT_MACHINE_START(MARZEN, "marzen") + .smp = smp_ops(r8a7779_smp_ops), + .map_io = r8a7779_map_io, + .init_early = r8a7779_init_delay, + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = r8a7779_init_irq_dt, + .init_machine = marzen_init, + .init_time = shmobile_timer_init, + .dt_compat = marzen_boards_compat_dt, +MACHINE_END From b8b82b2983e5b7bccca3a037c886e2aad86aaeea Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 22 Nov 2012 00:34:25 +0900 Subject: [PATCH 224/307] ARM: shmobile: kzm9g: Reference DT implementation Provide alternate board code for the kzm9g to demonstrate how DT may be used given the current state of driver device tree support. This is intended to act as a reference for mach-shmobile developers. Some notes: * Brings up the GIC interrupt handler using device tree * Brings up the following device using device tree: - MMCIF (MMC) * Does not bring up the INTC interrupt controller at all, thus external devices may not be used. In particular, the SMSC ethernet device may not be used and thus NFS root may not be used. * Uses existing C code and not device tree to initialise the following, which are needed for a working board: - SCIF (Serial) - CMT (Clock) - PFC (GPIO) To use this alternate board code instead of the normal board code, CONFIG_MACH_KZM9G_REFERENCE should be selected in the kernel config. And the sh73a0-kzm9g-reference.dtb flattened device tree blob should be used. Includes fix by Thierry Reding to no longer use gic_handle_irq() Includes fixes by Guennadi Liakhovetski for recent pinmux changes. Cc: Guennadi Liakhovetski Cc: Thierry Reding Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 41 +++++++++ arch/arm/mach-shmobile/Kconfig | 10 +++ arch/arm/mach-shmobile/Makefile | 1 + .../arm/mach-shmobile/board-kzm9g-reference.c | 87 +++++++++++++++++++ 5 files changed, 140 insertions(+) create mode 100644 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts create mode 100644 arch/arm/mach-shmobile/board-kzm9g-reference.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7965b9ad99d9..ee9fbe4d9912 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -138,6 +138,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ r8a7779-marzen-reference.dtb \ sh73a0-kzm9g.dtb \ + sh73a0-kzm9g-reference.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ socfpga_vt.dtb diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts new file mode 100644 index 000000000000..06f52f98f90d --- /dev/null +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -0,0 +1,41 @@ +/* + * Device Tree Source for the KZM-A9-GT board + * + * Copyright (C) 2012 Horms Solutions Ltd. + * + * Based on sh73a0-kzm9g.dts + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "sh73a0-reference.dtsi" + +/ { + model = "KZM-A9-GT"; + compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; + + chosen { + bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; + }; + + memory { + device_type = "memory"; + reg = <0x41000000 0x1e800000>; + }; + + fixedregulator1v8: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&mmcif { + vmmc-supply = <&fixedregulator1v8>; + vqmmc-supply = <&fixedregulator1v8>; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index b15d4ffcd9a2..0c48af9b1a0f 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -129,6 +129,16 @@ config MACH_KZM9G select SND_SOC_AK4642 if SND_SIMPLE_CARD select USE_OF +config MACH_KZM9G_REFERENCE + bool "KZM-A9-GT board - Reference Device Tree Implementation" + depends on MACH_KZM9G + ---help--- + Use reference implementation of KZM-A9-GT board support + which makes as greater use of device tree at the expense + of not supporting a number of devices. + + This is intended to aid developers + comment "SH-Mobile System Configuration" config CPU_HAS_INTEVT diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 3705d4f7096b..c621edfa6ead 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o +obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o # Framework support obj-$(CONFIG_SMP) += $(smp-y) diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c new file mode 100644 index 000000000000..caba1bb62f84 --- /dev/null +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -0,0 +1,87 @@ +/* + * KZM-A9-GT board support - Reference Device Tree Implementation + * + * Copyright (C) 2012 Horms Solutions Ltd. + * + * Based on board-kzm9g.c + * Copyright (C) 2012 Kuninori Morimoto + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct pinctrl_map kzm_pinctrl_map[] = { + PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", + "i2c3_1", "i2c3"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", + "scifa4_data", "scifa4"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", + "scifa4_ctrl", "scifa4"), +}; + +static void __init kzm_init(void) +{ + sh73a0_add_standard_devices_dt(); + pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); + +#ifdef CONFIG_CACHE_L2X0 + /* Early BRESP enable, Shared attribute override enable, 64K*8way */ + l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); +#endif +} + +static void kzm9g_restart(char mode, const char *cmd) +{ +#define RESCNT2 IOMEM(0xe6188020) + /* Do soft power on reset */ + writel((1 << 31), RESCNT2); +} + +static const char *kzm9g_boards_compat_dt[] __initdata = { + "renesas,kzm9g-reference", + NULL, +}; + +/* Please note that the clock initialisation shcheme used in + * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt() + * does not work with SMP as there is a yet to be resolved lock-up in + * workqueue initialisation. + * + * CONFIG_SMP should be disabled when using this code. + */ +DT_MACHINE_START(KZM9G_DT, "kzm9g-reference") + .smp = smp_ops(sh73a0_smp_ops), + .map_io = sh73a0_map_io, + .init_early = sh73a0_init_delay, + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = irqchip_init, + .init_machine = kzm_init, + .init_late = shmobile_init_late, + .init_time = shmobile_timer_init, + .restart = kzm9g_restart, + .dt_compat = kzm9g_boards_compat_dt, +MACHINE_END From 275cc1d4fcef076bb8f2ef01cf1540cd62b35eb9 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 8 Feb 2013 19:38:31 +0100 Subject: [PATCH 225/307] ARM: shmobile: parse DT and configure pinmux early on kzm9g-reference GPIOs can be provided by the pinctrl subsystem, which can be initialised by DT. Therefore DT has to be parsed before requesting GPIOs. Also non-DT pinmux has to be configured early. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index caba1bb62f84..add537c51b45 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -47,6 +47,7 @@ static void __init kzm_init(void) { sh73a0_add_standard_devices_dt(); pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); + sh73a0_pinmux_init(); #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ From f017d0119f59d442506cf884c7a43a9d12799a4e Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 8 Feb 2013 19:38:27 +0100 Subject: [PATCH 226/307] ARM: shmobile: SDHI and MMCIF interfaces to kzm9g-reference Add SDHI0 and SDHI2 interfaces to kzm9g-reference. With no pinctrl DT support we cannot use GPIO card-detection and regulator switching. Also update the MMCIF DT node to use all 8 data lines and avoid redundant information in DT. Cc: Laurent Pinchart [ horms+renesas@verge.net.au: Updated for pinmux changes by Laurent Pinchart ] Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 42 +++++++++++++++++-- .../arm/mach-shmobile/board-kzm9g-reference.c | 36 ++++++++++++++++ 2 files changed, 75 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 06f52f98f90d..7fad4b9b2f43 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -27,15 +27,51 @@ memory { reg = <0x41000000 0x1e800000>; }; - fixedregulator1v8: fixedregulator@0 { + reg_1p8v: regulator@0 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_2p8v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + sdhi0: sdhi@0xee100000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xee100000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 83 4 + 0 84 4 + 0 85 4>; + vmmc-supply = <®_2p8v>; + bus-width = <4>; + toshiba,mmc-has-idle-wait; + }; + + sdhi2: sdhi@0xee140000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xee140000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 104 4 + 0 105 4>; + vmmc-supply = <®_2p8v>; + bus-width = <4>; + broken-cd; + toshiba,mmc-wrprotect-disable; + toshiba,mmc-has-idle-wait; }; }; &mmcif { - vmmc-supply = <&fixedregulator1v8>; - vqmmc-supply = <&fixedregulator1v8>; + bus-width = <8>; + vmmc-supply = <®_1p8v>; }; diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index add537c51b45..3056698d8bc8 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -28,19 +28,48 @@ #include #include #include +#include #include #include #include #include #include +static unsigned long pin_pullup_conf[] = { + PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), +}; + static const struct pinctrl_map kzm_pinctrl_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", "i2c3_1", "i2c3"), + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_ctrl_0", "mmc0"), + PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "PORT279", pin_pullup_conf), + PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + "mmc0_data8_0", pin_pullup_conf), + /* SCIFA4 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_data", "scifa4"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_ctrl", "scifa4"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_cd", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + "sdhi0_wp", "sdhi0"), + /* SDHI2 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", + "sdhi2_data4", "sdhi2"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", + "sdhi2_ctrl", "sdhi2"), }; static void __init kzm_init(void) @@ -49,6 +78,13 @@ static void __init kzm_init(void) pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); sh73a0_pinmux_init(); + /* enable SD */ + gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); + gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + + gpio_request(GPIO_FN_SDHICLK2, NULL); + gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); From f33d1c34766ea96f6113d4d42fd1d1ec7a166e47 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 15 Jan 2013 18:23:36 +0100 Subject: [PATCH 227/307] ARM: shmobile: simplify kzm9g Kconfig dependencies Reference kernel configurations for armadillo800eva and kzm9g boards do not have to depend on their respective "legacy" configurations, doing device instantiation in .c, they can be configured and built independently. Signed-off-by: Guennadi Liakhovetski Acked-by: Laurent Pinchart Acked-by: Linus Walleij [horms+renesas@verge.net.au: created separate patch for kzm9g portion] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0c48af9b1a0f..ab2bb71db9b2 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -131,7 +131,11 @@ config MACH_KZM9G config MACH_KZM9G_REFERENCE bool "KZM-A9-GT board - Reference Device Tree Implementation" - depends on MACH_KZM9G + depends on ARCH_SH73A0 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SND_SOC_AK4642 if SND_SIMPLE_CARD + select USE_OF ---help--- Use reference implementation of KZM-A9-GT board support which makes as greater use of device tree at the expense From e30755f41d64ba95a23f4107cfbce83834778ae6 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: [PATCH 228/307] ARM: shmobile: kzm9g: Remove warning about SMP Remove warning about SMP not working with the clock initialisation used for kzm9g reference. This is resolved by not selecting CONFIG_PREEMPT. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-kzm9g-reference.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index 3056698d8bc8..4da3501c7f52 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -103,13 +103,6 @@ static const char *kzm9g_boards_compat_dt[] __initdata = { NULL, }; -/* Please note that the clock initialisation shcheme used in - * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt() - * does not work with SMP as there is a yet to be resolved lock-up in - * workqueue initialisation. - * - * CONFIG_SMP should be disabled when using this code. - */ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference") .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, From 5377762e2e004314bf9b83abf7f631b310d1fc40 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: [PATCH 229/307] ARM: shmobile: kzm9g: Trim reference DT_MACHINE_START Remove .init_late and .restart from DT_MACHINE_START for kzm9g reference as these are not necessary to bring the board up which is the main aim of kzm9g reference. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-kzm9g-reference.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index 4da3501c7f52..e93473c84c56 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -91,13 +91,6 @@ static void __init kzm_init(void) #endif } -static void kzm9g_restart(char mode, const char *cmd) -{ -#define RESCNT2 IOMEM(0xe6188020) - /* Do soft power on reset */ - writel((1 << 31), RESCNT2); -} - static const char *kzm9g_boards_compat_dt[] __initdata = { "renesas,kzm9g-reference", NULL, @@ -110,8 +103,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference") .nr_irqs = NR_IRQS_LEGACY, .init_irq = irqchip_init, .init_machine = kzm_init, - .init_late = shmobile_init_late, .init_time = shmobile_timer_init, - .restart = kzm9g_restart, .dt_compat = kzm9g_boards_compat_dt, MACHINE_END From 0b6794ef6ef9d8594f049b407b01d5e281acfe6e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 25 Feb 2013 01:39:44 -0800 Subject: [PATCH 230/307] ARM: shmobile: marzen: Use gic_iid macro for ICCIAR / interrupt ID ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID enabled to use gic_iid macro. This patch exchange current GIC interrupt setting from gic_spi() to gic_iid() Signed-off-by: Kuninori Morimoto [ horms+renesas@verge.net.au: Split irq.h portion into a separate patch ] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-marzen.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 5852331743e7..2333a2d7c937 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -67,7 +67,7 @@ static struct resource smsc911x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(28), /* IRQ 1 */ + .start = gic_iid(0x3c), /* IRQ 1 */ .flags = IORESOURCE_IRQ, }, }; @@ -97,7 +97,7 @@ static struct resource sdhi0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(104), + .start = gic_iid(0x88), .flags = IORESOURCE_IRQ, }, }; @@ -215,7 +215,7 @@ static struct resource ehci0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(44), + .start = gic_iid(0x4c), .flags = IORESOURCE_IRQ, }, }; @@ -239,7 +239,7 @@ static struct resource ehci1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(45), + .start = gic_iid(0x4d), .flags = IORESOURCE_IRQ, }, }; @@ -269,7 +269,7 @@ static struct resource ohci0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(44), + .start = gic_iid(0x4c), .flags = IORESOURCE_IRQ, }, }; @@ -293,7 +293,7 @@ static struct resource ohci1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(45), + .start = gic_iid(0x4d), .flags = IORESOURCE_IRQ, }, }; From 48296a13e7f411402f080d0603724623fa3eee14 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 22:48:36 +0900 Subject: [PATCH 231/307] ARM: shmobile: kzm9g: correct smsc regulator registration Correct the name of smsc devices used for regulator registration allowing the regulators to be found and used. This eliminates the need for CONFIG_REGULATOR_DUMMY when CONFIG_REGULATOR is set. Cc: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-kzm9g.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index c1c0401ff6a4..d2ace3a9f603 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -63,8 +63,8 @@ /* Dummy supplies, where voltage doesn't matter */ static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x"), - REGULATOR_SUPPLY("vdd33a", "smsc911x"), + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), }; /* From c791c036f844622bff767637be6df64b28634305 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 19 Mar 2013 13:47:39 +0100 Subject: [PATCH 232/307] ARM: shmobile: kzm9g: SDHI0 and SDHI1 use a 3.3V power supply kzm9g supplies 3.3V to its SDHI0 and SDHI2 interfaces. Specifying 2.8V prevents some (e.g. certain SDIO) cards from working. This patch fixes the voltage and removes redundant OCR masks from platform data. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 12 ++++++------ arch/arm/mach-shmobile/board-kzm9g.c | 10 ++++------ 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 7fad4b9b2f43..cadcf30e9641 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -36,11 +36,11 @@ reg_1p8v: regulator@0 { regulator-boot-on; }; - reg_2p8v: regulator@1 { + reg_3p3v: regulator@1 { compatible = "regulator-fixed"; - regulator-name = "fixed-2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; @@ -52,7 +52,7 @@ sdhi0: sdhi@0xee100000 { interrupts = <0 83 4 0 84 4 0 85 4>; - vmmc-supply = <®_2p8v>; + vmmc-supply = <®_3p3v>; bus-width = <4>; toshiba,mmc-has-idle-wait; }; @@ -63,7 +63,7 @@ sdhi2: sdhi@0xee140000 { interrupt-parent = <&gic>; interrupts = <0 104 4 0 105 4>; - vmmc-supply = <®_2p8v>; + vmmc-supply = <®_3p3v>; bus-width = <4>; broken-cd; toshiba,mmc-wrprotect-disable; diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index d2ace3a9f603..e924b815c0c8 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -375,8 +375,8 @@ static struct platform_device mmc_device = { .resource = sh_mmcif_resources, }; -/* Fixed 2.8V regulators to be used by SDHI0 and SDHI2 */ -static struct regulator_consumer_supply fixed2v8_power_consumers[] = +/* Fixed 3.3V regulators to be used by SDHI0 and SDHI2 */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = { REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), @@ -390,7 +390,6 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, .tmio_caps = MMC_CAP_SD_HIGHSPEED, - .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, }; static struct resource sdhi0_resources[] = { @@ -434,7 +433,6 @@ static struct sh_mobile_sdhi_info sdhi2_info = { TMIO_MMC_USE_GPIO_CD | TMIO_MMC_WRPROTECT_DISABLE, .tmio_caps = MMC_CAP_SD_HIGHSPEED, - .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, .cd_gpio = 13, }; @@ -716,8 +714,8 @@ static void __init kzm_init(void) { regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, ARRAY_SIZE(fixed1v8_power_consumers), 1800000); - regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers, - ARRAY_SIZE(fixed2v8_power_consumers), 2800000); + regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); From 546e5d3ef6f2f17c63de01f1cf43cdb51c1e9a6b Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 19 Mar 2013 13:47:43 +0100 Subject: [PATCH 233/307] ARM: shmobile: sh73a0: move SDHI and MMCIF DT nodes to sh73a0.dtsi To avoid having to repeat common DT node properties in all .dts files move them to SoC's .dtsi file, setting their status to "disabled." Individual boards will pick up devices, that they want to use and change their DT node status to enabled. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 41 +++++++----------- arch/arm/boot/dts/sh73a0-reference.dtsi | 24 ----------- arch/arm/boot/dts/sh73a0.dtsi | 44 ++++++++++++++++++++ 3 files changed, 59 insertions(+), 50 deletions(-) delete mode 100644 arch/arm/boot/dts/sh73a0-reference.dtsi diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index cadcf30e9641..f33b5ccb7446 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "sh73a0-reference.dtsi" +/include/ "sh73a0.dtsi" / { model = "KZM-A9-GT"; @@ -44,34 +44,23 @@ reg_3p3v: regulator@1 { regulator-always-on; regulator-boot-on; }; - - sdhi0: sdhi@0xee100000 { - compatible = "renesas,shmobile-sdhi"; - reg = <0xee100000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 83 4 - 0 84 4 - 0 85 4>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - toshiba,mmc-has-idle-wait; - }; - - sdhi2: sdhi@0xee140000 { - compatible = "renesas,shmobile-sdhi"; - reg = <0xee140000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 104 4 - 0 105 4>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - broken-cd; - toshiba,mmc-wrprotect-disable; - toshiba,mmc-has-idle-wait; - }; }; &mmcif { bus-width = <8>; vmmc-supply = <®_1p8v>; + status = "okay"; +}; + +&sdhi0 { + vmmc-supply = <®_3p3v>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi2 { + vmmc-supply = <®_3p3v>; + bus-width = <4>; + broken-cd; + status = "okay"; }; diff --git a/arch/arm/boot/dts/sh73a0-reference.dtsi b/arch/arm/boot/dts/sh73a0-reference.dtsi deleted file mode 100644 index d4bb0125b2b2..000000000000 --- a/arch/arm/boot/dts/sh73a0-reference.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Device Tree Source for the SH73A0 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "sh73a0.dtsi" - -/ { - compatible = "renesas,sh73a0"; - - mmcif: mmcif@0x10010000 { - compatible = "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 140 0x4 - 0 141 0x4>; - reg-io-width = <4>; - }; -}; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 8a59465d0231..c89be386cd37 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -97,4 +97,48 @@ i2c4: i2c@0xe6828000 { 0 189 0x4 0 190 0x4>; }; + + mmcif: mmcif@0x10010000 { + compatible = "renesas,sh-mmcif"; + reg = <0xe6bd0000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 140 0x4 + 0 141 0x4>; + reg-io-width = <4>; + status = "disabled"; + }; + + sdhi0: sdhi@0xee100000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xee100000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 83 4 + 0 84 4 + 0 85 4>; + toshiba,mmc-has-idle-wait; + status = "disabled"; + }; + + /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ + sdhi1: sdhi@0xee120000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xee120000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 88 4 + 0 89 4>; + toshiba,mmc-wrprotect-disable; + toshiba,mmc-has-idle-wait; + status = "disabled"; + }; + + sdhi2: sdhi@0xee140000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xee140000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 104 4 + 0 105 4>; + toshiba,mmc-wrprotect-disable; + toshiba,mmc-has-idle-wait; + status = "disabled"; + }; }; From a9060f89d9ad4e806c69acb1ea5ebdaeaa91e54b Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 18 Mar 2013 19:26:40 +0100 Subject: [PATCH 234/307] ARM: shmobile: armadillo800eva: add a fixed voltage regulator for SDHI1 The SDHI1 power supply on armadillo800eva can be switched on and off. In the current version this is not used and the regulator is hard-wired to "on." This patch switches SDHI1 to a proper fixed-voltage regulator, using a GPIO to enable and disable it. Both SDHI0 and SDHI1 ports shall now be specifying the MMC_CAP_POWER_OFF_CARD MMC capability. Both interfaces tested with an SDIO card. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- .../arm/mach-shmobile/board-armadillo800eva.c | 45 +++++++++++++++---- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index f322a18b55b6..7a78f9486684 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -559,8 +559,6 @@ static struct platform_device gpio_keys_device = { /* Fixed 3.3V regulator to be used by SDHI1, MMCIF */ static struct regulator_consumer_supply fixed3v3_power_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), REGULATOR_SUPPLY("vmmc", "sh_mmcif"), REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), }; @@ -645,6 +643,35 @@ static struct platform_device vccq_sdhi0 = { }, }; +/* Fixed 3.3V regulator to be used by SDHI1 */ +static struct regulator_consumer_supply vcc_sdhi1_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), +}; + +static struct regulator_init_data vcc_sdhi1_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi1_consumers), + .consumer_supplies = vcc_sdhi1_consumers, +}; + +static struct fixed_voltage_config vcc_sdhi1_info = { + .supply_name = "SDHI1 Vcc", + .microvolts = 3300000, + .gpio = GPIO_PORT16, + .enable_high = 1, + .init_data = &vcc_sdhi1_init_data, +}; + +static struct platform_device vcc_sdhi1 = { + .name = "reg-fixed-voltage", + .id = 2, + .dev = { + .platform_data = &vcc_sdhi1_info, + }, +}; + /* SDHI0 */ /* * FIXME @@ -658,7 +685,8 @@ static struct platform_device vccq_sdhi0 = { static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, .cd_gpio = GPIO_PORT167, }; @@ -699,7 +727,8 @@ static struct platform_device sdhi0_device = { static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, /* Port72 cannot generate IRQs, will be used in polling mode. */ .cd_gpio = GPIO_PORT72, @@ -992,6 +1021,8 @@ static struct platform_device *eva_devices[] __initdata = { &lcdc0_device, &gpio_keys_device, &sh_eth_device, + &vcc_sdhi0, + &vccq_sdhi0, &sdhi0_device, &sh_mmcif_device, &hdmi_device, @@ -1002,8 +1033,6 @@ static struct platform_device *eva_devices[] __initdata = { &fsi_wm8978_device, &fsi_hdmi_device, &i2c_gpio_device, - &vcc_sdhi0, - &vccq_sdhi0, }; static const struct pinctrl_map eva_pinctrl_map[] = { @@ -1198,9 +1227,7 @@ static void __init eva_init(void) pinctrl_register_mappings(eva_sdhi1_pinctrl_map, ARRAY_SIZE(eva_sdhi1_pinctrl_map)); - /* SDSLOT2_PON */ - gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL); - + platform_device_register(&vcc_sdhi1); platform_device_register(&sdhi1_device); } From 54ca74ef09a98fcbd77887bb6ff38986ff593955 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 18 Mar 2013 19:26:44 +0100 Subject: [PATCH 235/307] ARM: shmobile: kzm9g: add fixed voltage regulators for SDHI0 and SDHI2 Both SDHI0 and SDHI2 power supplies on kzm9g can be switched on and off. In the current version this is not used and the regulators are hard-wired to "on." This patch switches SDHI0 and SDHI2 to proper fixed-voltage regulators, using GPIOs to enable and disable them. Both ports shall now be specifying the MMC_CAP_POWER_OFF_CARD MMC capability. Only SDHI0 has been tested with an SDIO card, since SDHI2 is a microSD slot. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-kzm9g.c | 76 +++++++++++++++++++++++----- 1 file changed, 62 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index e924b815c0c8..77a66ac12417 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -375,13 +375,64 @@ static struct platform_device mmc_device = { .resource = sh_mmcif_resources, }; -/* Fixed 3.3V regulators to be used by SDHI0 and SDHI2 */ -static struct regulator_consumer_supply fixed3v3_power_consumers[] = +/* Fixed 3.3V regulators to be used by SDHI0 */ +static struct regulator_consumer_supply vcc_sdhi0_consumers[] = { REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +}; + +static struct regulator_init_data vcc_sdhi0_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), + .consumer_supplies = vcc_sdhi0_consumers, +}; + +static struct fixed_voltage_config vcc_sdhi0_info = { + .supply_name = "SDHI0 Vcc", + .microvolts = 3300000, + .gpio = 15, + .enable_high = 1, + .init_data = &vcc_sdhi0_init_data, +}; + +static struct platform_device vcc_sdhi0 = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &vcc_sdhi0_info, + }, +}; + +/* Fixed 3.3V regulators to be used by SDHI2 */ +static struct regulator_consumer_supply vcc_sdhi2_consumers[] = +{ REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"), +}; + +static struct regulator_init_data vcc_sdhi2_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi2_consumers), + .consumer_supplies = vcc_sdhi2_consumers, +}; + +static struct fixed_voltage_config vcc_sdhi2_info = { + .supply_name = "SDHI2 Vcc", + .microvolts = 3300000, + .gpio = 14, + .enable_high = 1, + .init_data = &vcc_sdhi2_init_data, +}; + +static struct platform_device vcc_sdhi2 = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &vcc_sdhi2_info, + }, }; /* SDHI */ @@ -389,7 +440,8 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, - .tmio_caps = MMC_CAP_SD_HIGHSPEED, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_POWER_OFF_CARD, }; static struct resource sdhi0_resources[] = { @@ -432,7 +484,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = { .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD | TMIO_MMC_WRPROTECT_DISABLE, - .tmio_caps = MMC_CAP_SD_HIGHSPEED, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD, .cd_gpio = 13, }; @@ -592,6 +644,8 @@ static struct platform_device *kzm_devices[] __initdata = { &usbhs_device, &lcdc_device, &mmc_device, + &vcc_sdhi0, + &vcc_sdhi2, &sdhi0_device, &sdhi2_device, &gpio_keys_device, @@ -712,11 +766,9 @@ device_initcall(as3711_enable_lcdc_backlight); static void __init kzm_init(void) { - regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, + regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers, ARRAY_SIZE(fixed1v8_power_consumers), 1800000); - regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, - ARRAY_SIZE(fixed3v3_power_consumers), 3300000); - regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); @@ -734,10 +786,6 @@ static void __init kzm_init(void) /* enable SD */ gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ - - /* enable Micro SD */ - gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ From a463f731766e8273f44ba397233bfc7ecf752f98 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 19 Mar 2013 18:38:50 +0100 Subject: [PATCH 236/307] ARM: shmobile: kzm9g-reference: fix device-tree bindings and device names Fix several device-tree bindings, that haven't been updated for newest versions of respective drivers, and device names and pin numbers, left over from non-DT and old pinctrl versions. Signed-off-by: Guennadi Liakhovetski Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 12 ++++----- .../arm/mach-shmobile/board-kzm9g-reference.c | 27 +++++++++---------- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c89be386cd37..3e4d383ac6d9 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -109,36 +109,36 @@ mmcif: mmcif@0x10010000 { }; sdhi0: sdhi@0xee100000 { - compatible = "renesas,shmobile-sdhi"; + compatible = "renesas,r8a7740-sdhi"; reg = <0xee100000 0x100>; interrupt-parent = <&gic>; interrupts = <0 83 4 0 84 4 0 85 4>; - toshiba,mmc-has-idle-wait; + cap-sd-highspeed; status = "disabled"; }; /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ sdhi1: sdhi@0xee120000 { - compatible = "renesas,shmobile-sdhi"; + compatible = "renesas,r8a7740-sdhi"; reg = <0xee120000 0x100>; interrupt-parent = <&gic>; interrupts = <0 88 4 0 89 4>; toshiba,mmc-wrprotect-disable; - toshiba,mmc-has-idle-wait; + cap-sd-highspeed; status = "disabled"; }; sdhi2: sdhi@0xee140000 { - compatible = "renesas,shmobile-sdhi"; + compatible = "renesas,r8a7740-sdhi"; reg = <0xee140000 0x100>; interrupt-parent = <&gic>; interrupts = <0 104 4 0 105 4>; toshiba,mmc-wrprotect-disable; - toshiba,mmc-has-idle-wait; + cap-sd-highspeed; status = "disabled"; }; }; diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index e93473c84c56..aefa50d385b7 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -40,16 +40,16 @@ static unsigned long pin_pullup_conf[] = { }; static const struct pinctrl_map kzm_pinctrl_map[] = { - PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0", "i2c3_1", "i2c3"), /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", "mmc0_ctrl_0", "mmc0"), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", "PORT279", pin_pullup_conf), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", + PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", "mmc0_data8_0", pin_pullup_conf), /* SCIFA4 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", @@ -57,18 +57,18 @@ static const struct pinctrl_map kzm_pinctrl_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_ctrl", "scifa4"), /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", "sdhi0_wp", "sdhi0"), /* SDHI2 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0", "sdhi2_data4", "sdhi2"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0", "sdhi2_ctrl", "sdhi2"), }; @@ -80,10 +80,9 @@ static void __init kzm_init(void) /* enable SD */ gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ - gpio_request(GPIO_FN_SDHICLK2, NULL); - gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ From ac22dde76c80a3ffa3c3c24cf16bb8076b20b767 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 21 Mar 2013 20:18:12 +0900 Subject: [PATCH 237/307] Revert "ARM: shmobile: streamline mackerel SD and MMC devices" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 626a645eb75415255aad3162f4da3f6988f0c8ec. This appears to be incompatible with "ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs" Reverting this change resolves the following build failure: arch/arm/mach-shmobile/board-mackerel.c: In function ‘mackerel_init’: arch/arm/mach-shmobile/board-mackerel.c:1468: error: ‘GPIO_FN_SDHICMD1’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1468: error: (Each undeclared identifier is reported only once arch/arm/mach-shmobile/board-mackerel.c:1468: error: for each function it appears in.) arch/arm/mach-shmobile/board-mackerel.c:1469: error: ‘GPIO_FN_SDHICLK1’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1470: error: ‘GPIO_FN_SDHID1_3’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1471: error: ‘GPIO_FN_SDHID1_2’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1472: error: ‘GPIO_FN_SDHID1_1’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1473: error: ‘GPIO_FN_SDHID1_0’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1489: error: ‘GPIO_FN_SDHICMD2’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1490: error: ‘GPIO_FN_SDHICLK2’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1491: error: ‘GPIO_FN_SDHID2_3’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1492: error: ‘GPIO_FN_SDHID2_2’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1493: error: ‘GPIO_FN_SDHID2_1’ undeclared (first use in this function) arch/arm/mach-shmobile/board-mackerel.c:1494: error: ‘GPIO_FN_SDHID2_0’ undeclared (first use in this function) Cc: Guennadi Liakhovetski Cc: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 113 ++++++++++++------------ 1 file changed, 56 insertions(+), 57 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index ef22ec4dafae..1a9c75383ca0 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -963,6 +963,15 @@ static struct platform_device nand_flash_device = { }, }; +/* + * The card detect pin of the top SD/MMC slot (CN7) is active low and is + * connected to GPIO A22 of SH7372 (GPIO 41). + */ +static int slot_cn7_get_cd(struct platform_device *pdev) +{ + return !gpio_get_value(41); +} + /* SDHI0 */ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, @@ -973,21 +982,21 @@ static struct sh_mobile_sdhi_info sdhi0_info = { }; static struct resource sdhi0_resources[] = { - { + [0] = { .name = "SDHI0", .start = 0xe6850000, .end = 0xe68500ff, .flags = IORESOURCE_MEM, - }, { - .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, + }, + [1] = { .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */, .flags = IORESOURCE_IRQ, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDCARD, + }, + [2] = { .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, .flags = IORESOURCE_IRQ, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDIO, + }, + [3] = { .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, .flags = IORESOURCE_IRQ, }, @@ -1005,28 +1014,34 @@ static struct platform_device sdhi0_device = { #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) /* SDHI1 */ - -/* GPIO_PORT41 can trigger IRQ8, but it is used by USBHS1, we have to poll */ static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, + .tmio_ocr_mask = MMC_VDD_165_195, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL, - .cd_gpio = GPIO_PORT41, + .get_cd = slot_cn7_get_cd, }; static struct resource sdhi1_resources[] = { - { + [0] = { .name = "SDHI1", .start = 0xe6860000, .end = 0xe68600ff, .flags = IORESOURCE_MEM, - }, { + }, + [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, + .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ + .flags = IORESOURCE_IRQ, + }, + [2] = { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ .flags = IORESOURCE_IRQ, - }, { + }, + [3] = { .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ .flags = IORESOURCE_IRQ, @@ -1044,32 +1059,43 @@ static struct platform_device sdhi1_device = { }; #endif -/* SDHI2 */ - /* * The card detect pin of the top SD/MMC slot (CN23) is active low and is - * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162). + * connected to GPIO SCIFB_SCK of SH7372 (162). */ +static int slot_cn23_get_cd(struct platform_device *pdev) +{ + return !gpio_get_value(162); +} + +/* SDHI2 */ static struct sh_mobile_sdhi_info sdhi2_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL, - .cd_gpio = GPIO_PORT162, + .get_cd = slot_cn23_get_cd, }; static struct resource sdhi2_resources[] = { - { + [0] = { .name = "SDHI2", .start = 0xe6870000, .end = 0xe68700ff, .flags = IORESOURCE_MEM, - }, { + }, + [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, + .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */ + .flags = IORESOURCE_IRQ, + }, + [2] = { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ .flags = IORESOURCE_IRQ, - }, { + }, + [3] = { .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ .flags = IORESOURCE_IRQ, @@ -1108,12 +1134,11 @@ static struct resource sh_mmcif_resources[] = { static struct sh_mmcif_plat_data sh_mmcif_plat = { .sup_pclk = 0, + .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NEEDS_POLL, - .use_cd_gpio = true, - /* card detect pin for SD/MMC slot (CN7) */ - .cd_gpio = GPIO_PORT41, + .get_cd = slot_cn7_get_cd, .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; @@ -1238,10 +1263,9 @@ static struct platform_device *mackerel_devices[] __initdata = { &sdhi0_device, #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) &sdhi1_device, -#else - &sh_mmcif_device, #endif &sdhi2_device, + &sh_mmcif_device, &ceu_device, &mackerel_camera, &hdmi_device, @@ -1348,11 +1372,10 @@ static void __init mackerel_init(void) { "A3SP", &usbhs0_device, }, { "A3SP", &usbhs1_device, }, { "A3SP", &nand_flash_device, }, + { "A3SP", &sh_mmcif_device, }, { "A3SP", &sdhi0_device, }, #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) { "A3SP", &sdhi1_device, }, -#else - { "A3SP", &sh_mmcif_device, }, #endif { "A3SP", &sdhi2_device, }, { "A4R", &ceu_device, }, @@ -1463,35 +1486,11 @@ static void __init mackerel_init(void) /* SDHI0 PORT172 card-detect IRQ26 */ gpio_request(GPIO_FN_IRQ26_172, NULL); -#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) - /* enable SDHI1 */ - gpio_request(GPIO_FN_SDHICMD1, NULL); - gpio_request(GPIO_FN_SDHICLK1, NULL); - gpio_request(GPIO_FN_SDHID1_3, NULL); - gpio_request(GPIO_FN_SDHID1_2, NULL); - gpio_request(GPIO_FN_SDHID1_1, NULL); - gpio_request(GPIO_FN_SDHID1_0, NULL); -#else - /* MMCIF */ - gpio_request(GPIO_FN_MMCD0_0, NULL); - gpio_request(GPIO_FN_MMCD0_1, NULL); - gpio_request(GPIO_FN_MMCD0_2, NULL); - gpio_request(GPIO_FN_MMCD0_3, NULL); - gpio_request(GPIO_FN_MMCD0_4, NULL); - gpio_request(GPIO_FN_MMCD0_5, NULL); - gpio_request(GPIO_FN_MMCD0_6, NULL); - gpio_request(GPIO_FN_MMCD0_7, NULL); - gpio_request(GPIO_FN_MMCCMD0, NULL); - gpio_request(GPIO_FN_MMCCLK0, NULL); -#endif + /* card detect pin for MMC slot (CN7) */ + gpio_request_one(41, GPIOF_IN, NULL); - /* enable SDHI2 */ - gpio_request(GPIO_FN_SDHICMD2, NULL); - gpio_request(GPIO_FN_SDHICLK2, NULL); - gpio_request(GPIO_FN_SDHID2_3, NULL); - gpio_request(GPIO_FN_SDHID2_2, NULL); - gpio_request(GPIO_FN_SDHID2_1, NULL); - gpio_request(GPIO_FN_SDHID2_0, NULL); + /* card detect pin for microSD slot (CN23) */ + gpio_request_one(162, GPIOF_IN, NULL); /* FLCTL */ gpio_request(GPIO_FN_D0_NAF0, NULL); From 427cc720277c140e6a63a03237f9bf37d8076ac3 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Wed, 27 Mar 2013 14:54:03 +0100 Subject: [PATCH 238/307] irqchip: intc-irqpin: Add support for shared interrupt lines On some hardware we don't have a 1-1 mapping from the external interrupts coming from INTC to the GIC SPI pins. We can however share lines to demux incoming IRQs on these SoCs. This patch enables the intc_irqpin driver to detect requests for shared interrupt lines and demuxes them properly by querying the INTC INTREQx0A registers. If you need multiple shared intc_irqpin device instances, be sure to mask out all interrupts on the INTC that share the one line before you start to register them. Else you run into IRQ floods that would be caused by interrupts for which no handler has been set up yet when the first intc_irqpin device is registered. Signed-off-by: Bastian Hecht Acked-by: Magnus Damm Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 90 +++++++++++++++++++++-- 1 file changed, 83 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index fd5dabc2235d..5a68e5accec1 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -74,6 +74,8 @@ struct intc_irqpin_priv { struct platform_device *pdev; struct irq_chip irq_chip; struct irq_domain *irq_domain; + bool shared_irqs; + u8 shared_irq_mask; }; static unsigned long intc_irqpin_read32(void __iomem *iomem) @@ -193,6 +195,28 @@ static void intc_irqpin_irq_disable(struct irq_data *d) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); } +static void intc_irqpin_shared_irq_enable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); + + p->shared_irq_mask &= ~BIT(hw_irq); +} + +static void intc_irqpin_shared_irq_disable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); + + p->shared_irq_mask |= BIT(hw_irq); +} + static void intc_irqpin_irq_enable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); @@ -261,6 +285,25 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) return IRQ_NONE; } +static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) +{ + struct intc_irqpin_priv *p = dev_id; + unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); + irqreturn_t status = IRQ_NONE; + int k; + + for (k = 0; k < 8; k++) { + if (reg_source & BIT(7 - k)) { + if (BIT(k) & p->shared_irq_mask) + continue; + + status |= intc_irqpin_irq_handler(irq, &p->irq[k]); + } + } + + return status; +} + static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { @@ -292,6 +335,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) void (*enable_fn)(struct irq_data *d); void (*disable_fn)(struct irq_data *d); const char *name = dev_name(&pdev->dev); + int ref_irq; int ret; int k; @@ -372,13 +416,29 @@ static int intc_irqpin_probe(struct platform_device *pdev) for (k = 0; k < p->number_of_irqs; k++) intc_irqpin_mask_unmask_prio(p, k, 1); + /* clear all pending interrupts */ + intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); + + /* scan for shared interrupt lines */ + ref_irq = p->irq[0].requested_irq; + p->shared_irqs = true; + for (k = 1; k < p->number_of_irqs; k++) { + if (ref_irq != p->irq[k].requested_irq) { + p->shared_irqs = false; + break; + } + } + /* use more severe masking method if requested */ if (p->config.control_parent) { enable_fn = intc_irqpin_irq_enable_force; disable_fn = intc_irqpin_irq_disable_force; - } else { + } else if (!p->shared_irqs) { enable_fn = intc_irqpin_irq_enable; disable_fn = intc_irqpin_irq_disable; + } else { + enable_fn = intc_irqpin_shared_irq_enable; + disable_fn = intc_irqpin_shared_irq_disable; } irq_chip = &p->irq_chip; @@ -400,18 +460,34 @@ static int intc_irqpin_probe(struct platform_device *pdev) goto err0; } - /* request and set priority on interrupts one by one */ - for (k = 0; k < p->number_of_irqs; k++) { - if (devm_request_irq(&pdev->dev, p->irq[k].requested_irq, - intc_irqpin_irq_handler, - 0, name, &p->irq[k])) { + if (p->shared_irqs) { + /* request one shared interrupt */ + if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq, + intc_irqpin_shared_irq_handler, + IRQF_SHARED, name, p)) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; goto err1; } - intc_irqpin_mask_unmask_prio(p, k, 0); + } else { + /* request interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (devm_request_irq(&pdev->dev, + p->irq[k].requested_irq, + intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, + "failed to request low IRQ\n"); + ret = -ENOENT; + goto err1; + } + } } + /* unmask all interrupts on prio level */ + for (k = 0; k < p->number_of_irqs; k++) + intc_irqpin_mask_unmask_prio(p, k, 0); + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); /* warn in case of mismatch if irq base is specified */ From eccf0607e450f5c6ca2af5d826d9308e8cdb6848 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:24 +0900 Subject: [PATCH 239/307] ARM: shmobile: Initial r8a73a4 SoC support V3 V3 of initial support for the r8a73a4 SoC including: - Single Cortex-A15 CPU Core - GIC - Architecture timer No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 55 +++++++++++ arch/arm/mach-shmobile/Kconfig | 7 ++ arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/clock-r8a73a4.c | 91 +++++++++++++++++++ arch/arm/mach-shmobile/include/mach/r8a73a4.h | 7 ++ arch/arm/mach-shmobile/setup-r8a73a4.c | 50 ++++++++++ 6 files changed, 211 insertions(+) create mode 100644 arch/arm/boot/dts/r8a73a4.dtsi create mode 100644 arch/arm/mach-shmobile/clock-r8a73a4.c create mode 100644 arch/arm/mach-shmobile/include/mach/r8a73a4.h create mode 100644 arch/arm/mach-shmobile/setup-r8a73a4.c diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi new file mode 100644 index 000000000000..72c58c172e9d --- /dev/null +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -0,0 +1,55 @@ +/* + * Device Tree Source for the r8a73a4 SoC + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a73a4"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xf1001000 0x1000>, + <0xf1002000 0x1000>, + <0xf1004000 0x2000>, + <0xf1006000 0x2000>; + interrupts = <1 9 0xf04>; + + gic-cpuif@4 { + compatible = "arm,gic-cpuif"; + cpuif-id = <4>; + cpu = <&cpu0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 75d413c004b6..663d27b39880 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -18,6 +18,13 @@ config ARCH_SH73A0 select SH_CLK_CPG select RENESAS_INTC_IRQPIN +config ARCH_R8A73A4 + bool "R-Mobile APE6 (R8A73A40)" + select ARM_GIC + select CPU_V7 + select ARM_ARCH_TIMER + select SH_CLK_CPG + config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index b646ff4d742a..c5a43ef7cebf 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -8,6 +8,7 @@ obj-y := timer.o console.o clock.o # CPU objects obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o +obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c new file mode 100644 index 000000000000..15d479dbb132 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -0,0 +1,91 @@ +/* + * r8a73a4 clock framework support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include + +#define CPG_BASE 0xe6150000 +#define CPG_LEN 0x270 + +#define MPCKCR 0xe6150080 + +static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, + .len = CPG_LEN, +}; + +static struct clk extalr_clk = { + .rate = 32768, + .mapping = &cpg_mapping, +}; + +static struct clk extal1_clk = { + .rate = 26000000, + .mapping = &cpg_mapping, +}; + +static struct clk extal2_clk = { + .rate = 48000000, + .mapping = &cpg_mapping, +}; + +static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, + &extal2_clk, +}; + +enum { MSTP_NR }; +static struct clk mstp_clks[MSTP_NR] = { +}; + +static struct clk_lookup lookups[] = { +}; + +void __init r8a73a4_clock_init(void) +{ + void __iomem *cpg_base, *reg; + int k, ret = 0; + + /* fix MPCLK to EXTAL2 for now. + * this is needed until more detailed clock topology is supported + */ + cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); + BUG_ON(!cpg_base); + reg = cpg_base + (MPCKCR - CPG_BASE); + iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ + iounmap(cpg_base); + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + shmobile_clk_init(); + else + panic("failed to setup r8a73a4 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h new file mode 100644 index 000000000000..6db3495479d8 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -0,0 +1,7 @@ +#ifndef __ASM_R8A73A4_H__ +#define __ASM_R8A73A4_H__ + +void r8a73a4_add_standard_devices(void); +void r8a73a4_clock_init(void); + +#endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c new file mode 100644 index 000000000000..69156bce76f7 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -0,0 +1,50 @@ +/* + * r8a73a4 processor support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +void __init r8a73a4_add_standard_devices(void) +{ +} + +#ifdef CONFIG_USE_OF +void __init r8a73a4_add_standard_devices_dt(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *r8a73a4_boards_compat_dt[] __initdata = { + "renesas,r8a73a4", + NULL, +}; + +DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") + .init_irq = irqchip_init, + .init_machine = r8a73a4_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a73a4_boards_compat_dt, +MACHINE_END +#endif /* CONFIG_USE_OF */ From e481a528901d0cd18b5b5fcbdc55207ea3b6ef68 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:33 +0900 Subject: [PATCH 240/307] ARM: shmobile: r8a73a4 SCIF support V3 V3 of SCIF serial port support for the r8a73a4 SoC. This is done by adding platform devices for SCIFA0 -> SCIFA1 as well as SCIFB0 -> SCIFB3 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a73a4.c | 15 ++++++++- arch/arm/mach-shmobile/setup-r8a73a4.c | 43 ++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 15d479dbb132..037713bdff3f 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -28,6 +28,7 @@ #define CPG_LEN 0x270 #define MPCKCR 0xe6150080 +#define SMSTPCR2 0xe6150138 static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, @@ -55,11 +56,23 @@ static struct clk *main_clks[] = { &extal2_clk, }; -enum { MSTP_NR }; +enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ }; static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), }; void __init r8a73a4_clock_init(void) diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 69156bce76f7..746a3dc4474d 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -21,13 +21,56 @@ #include #include #include +#include #include #include #include #include +#define SCIF_COMMON(scif_type, baseaddr, irq) \ + .type = scif_type, \ + .mapbase = baseaddr, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scbrr_algo_id = SCBRR_ALGO_4, \ + .irqs = SCIx_IRQ_MUXED(irq) + +#define SCIFA_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ +} + +#define SCIFB_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ + .scscr = SCSCR_RE | SCSCR_TE, \ +} + +enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; + +static const struct plat_sci_port scif[] = { + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ + SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ + SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */ + SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ + SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ + SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ +}; + +static inline void r8a73a4_register_scif(int idx) +{ + platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], + sizeof(struct plat_sci_port)); +} + void __init r8a73a4_add_standard_devices(void) { + r8a73a4_register_scif(SCIFA0); + r8a73a4_register_scif(SCIFA1); + r8a73a4_register_scif(SCIFB0); + r8a73a4_register_scif(SCIFB1); + r8a73a4_register_scif(SCIFB2); + r8a73a4_register_scif(SCIFB3); } #ifdef CONFIG_USE_OF From 984ca295010ad0113b986a404931566f9b1791d4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:42 +0900 Subject: [PATCH 241/307] ARM: shmobile: r8a73a4 IRQC support V2 Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 32 ++++++++++ arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/setup-r8a73a4.c | 84 ++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 72c58c172e9d..4c68ba15727c 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -52,4 +52,36 @@ timer { <1 11 0xf08>, <1 10 0xf08>; }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, + <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, + <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, + <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, + <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, + <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, + <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, + <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; + }; + + irqc1: interrupt-controller@e61c0200 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0200 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, + <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, + <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, + <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, + <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, + <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, + <0 56 4>, <0 57 4>; + }; + }; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 663d27b39880..17a59cde826e 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -24,6 +24,7 @@ config ARCH_R8A73A4 select CPU_V7 select ARM_ARCH_TIMER select SH_CLK_CPG + select RENESAS_IRQC config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 746a3dc4474d..da5ae1611518 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -63,6 +64,87 @@ static inline void r8a73a4_register_scif(int idx) sizeof(struct plat_sci_port)); } +static const struct renesas_irqc_config irqc0_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ +}; + +static const struct resource irqc0_resources[] = { + DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ + DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ + DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ + DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ + DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ + DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ + DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ + DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ + DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ + DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ + DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ + DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ + DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ + DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ + DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ + DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ + DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ + DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ + DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ + DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ + DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ + DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ + DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ + DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ + DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ + DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ + DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ + DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ + DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ +}; + +static const struct renesas_irqc_config irqc1_data = { + .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ +}; + +static const struct resource irqc1_resources[] = { + DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ + DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ + DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ + DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ + DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ + DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ + DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ + DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ + DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ + DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ + DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ + DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ + DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ + DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ + DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ + DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ + DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ + DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ + DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ + DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ + DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ + DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ + DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ + DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ + DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ + DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ + DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ +}; + +#define r8a73a4_register_irqc(idx) \ + platform_device_register_resndata(&platform_bus, "renesas_irqc", \ + idx, irqc##idx##_resources, \ + ARRAY_SIZE(irqc##idx##_resources), \ + &irqc##idx##_data, \ + sizeof(struct renesas_irqc_config)) + void __init r8a73a4_add_standard_devices(void) { r8a73a4_register_scif(SCIFA0); @@ -71,6 +153,8 @@ void __init r8a73a4_add_standard_devices(void) r8a73a4_register_scif(SCIFB1); r8a73a4_register_scif(SCIFB2); r8a73a4_register_scif(SCIFB3); + r8a73a4_register_irqc(0); + r8a73a4_register_irqc(1); } #ifdef CONFIG_USE_OF From d313d068d4b5801ea9c0c66bed66f37c64ad6807 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:52 +0900 Subject: [PATCH 242/307] ARM: shmobile: r8a73a4 PFC support Add a platform device for the r8a73a4 PFC. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/include/mach/r8a73a4.h | 1 + arch/arm/mach-shmobile/setup-r8a73a4.c | 10 ++++++++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 17a59cde826e..0e4a820bcbe8 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -20,6 +20,7 @@ config ARCH_SH73A0 config ARCH_R8A73A4 bool "R-Mobile APE6 (R8A73A40)" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 select ARM_ARCH_TIMER diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index 6db3495479d8..f043103e32c9 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -3,5 +3,6 @@ void r8a73a4_add_standard_devices(void); void r8a73a4_clock_init(void); +void r8a73a4_pinmux_init(void); #endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index da5ae1611518..c2d86f30cde4 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -28,6 +28,16 @@ #include #include +static const struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xe6050000, 0x9000), +}; + +void __init r8a73a4_pinmux_init(void) +{ + platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources, + ARRAY_SIZE(pfc_resources)); +} + #define SCIF_COMMON(scif_type, baseaddr, irq) \ .type = scif_type, \ .mapbase = baseaddr, \ From 7653c318b73d8553d4c13bb7e371878ddc19f80d Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 28 Feb 2013 13:21:58 +0100 Subject: [PATCH 243/307] ARM: shmobile: sh73a0: wait for completion when kicking the clock To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to be set and to make sure the setting has taken effect, it has to be read back repeatedly until it is cleared by the hardware. This patch adds the waiting part, that was missing until now. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm --- arch/arm/mach-shmobile/clock-sh73a0.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 71843dd39e16..34b5c5ae4cbd 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #define FRQCRA IOMEM(0xe6150000) @@ -234,14 +235,24 @@ static struct clk *main_clks[] = { &sh73a0_extalr_clk, }; +static int frqcr_kick(void) +{ + int i; + + /* set KICK bit in FRQCRB to update hardware setting, check success */ + __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB); + for (i = 1000; i; i--) + if (__raw_readl(FRQCRB) & (1 << 31)) + cpu_relax(); + else + return i; + + return -ETIMEDOUT; +} + static void div4_kick(struct clk *clk) { - unsigned long value; - - /* set KICK bit in FRQCRB to update hardware setting */ - value = __raw_readl(FRQCRB); - value |= (1 << 31); - __raw_writel(value, FRQCRB); + frqcr_kick(); } static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, From ccb7cc749f78166178184f77dd95ea24db9d5bb0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 21 Mar 2013 03:01:36 -0700 Subject: [PATCH 244/307] ARM: shmobile: add R8A7778 basis support Add initial support for the R8A7778 R-Car M1A SoC. No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. It is based on v1.0 datasheet Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 35 ++++ arch/arm/mach-shmobile/Kconfig | 6 + arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/clock-r8a7778.c | 91 ++++++++++ arch/arm/mach-shmobile/include/mach/r8a7778.h | 28 +++ arch/arm/mach-shmobile/setup-r8a7778.c | 167 ++++++++++++++++++ 6 files changed, 328 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7778.dtsi create mode 100644 arch/arm/mach-shmobile/clock-r8a7778.c create mode 100644 arch/arm/mach-shmobile/include/mach/r8a7778.h create mode 100644 arch/arm/mach-shmobile/setup-r8a7778.c diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi new file mode 100644 index 000000000000..474373559bdc --- /dev/null +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -0,0 +1,35 @@ +/* + * Device Tree Source for Renesas r8a7778 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * based on r8a7779 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a7778"; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + }; + }; + + gic: interrupt-controller@fe438000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfe438000 0x1000>, + <0xfe430000 0x100>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0e4a820bcbe8..49cba4a511df 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -33,6 +33,12 @@ config ARCH_R8A7740 select CPU_V7 select SH_CLK_CPG +config ARCH_R8A7778 + bool "R-Car M1 (R8A77780)" + select CPU_V7 + select SH_CLK_CPG + select ARM_GIC + config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index c5a43ef7cebf..2d42de46db8d 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o +obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c new file mode 100644 index 000000000000..387e3b74cc8c --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -0,0 +1,91 @@ +/* + * r8a7778 clock framework support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * based on r8a7779 + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define MSTPCR0 IOMEM(0xffc80030) +#define MSTPCR1 IOMEM(0xffc80034) +#define MSTPCR3 IOMEM(0xffc8003c) +#define MSTPSR1 IOMEM(0xffc80044) +#define MSTPSR4 IOMEM(0xffc80048) +#define MSTPSR6 IOMEM(0xffc8004c) +#define MSTPCR4 IOMEM(0xffc80050) +#define MSTPCR5 IOMEM(0xffc80054) +#define MSTPCR6 IOMEM(0xffc80058) + +/* ioremap() through clock mapping mandatory to avoid + * collision with ARM coherent DMA virtual memory range. + */ + +static struct clk_mapping cpg_mapping = { + .phys = 0xffc80000, + .len = 0x80, +}; + +static struct clk clkp = { + .rate = 62500000, /* FIXME: shortcut */ + .flags = CLK_ENABLE_ON_INIT, + .mapping = &cpg_mapping, +}; + +static struct clk *main_clks[] = { + &clkp, +}; + +enum { + MSTP016, MSTP015, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ +}; + +static struct clk_lookup lookups[] = { + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ +}; + +void __init r8a7778_clock_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + shmobile_clk_init(); + else + panic("failed to setup r8a7778 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h new file mode 100644 index 000000000000..a755dcafef4d --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ASM_R8A7778_H__ +#define __ASM_R8A7778_H__ + +extern void r8a7778_add_standard_devices(void); +extern void r8a7778_add_standard_devices_dt(void); +extern void r8a7778_init_delay(void); +extern void r8a7778_init_irq(void); +extern void r8a7778_init_irq_dt(void); +extern void r8a7778_clock_init(void); + +#endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c new file mode 100644 index 000000000000..811ccf3c77a4 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -0,0 +1,167 @@ +/* + * r8a7778 processor support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TMU */ +static struct resource sh_tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80008, 12), + DEFINE_RES_IRQ(gic_iid(0x40)), +}; + +static struct sh_timer_config sh_tmu0_platform_data = { + .name = "TMU00", + .channel_offset = 0x4, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource sh_tmu1_resources[] = { + DEFINE_RES_MEM(0xffd80014, 12), + DEFINE_RES_IRQ(gic_iid(0x41)), +}; + +static struct sh_timer_config sh_tmu1_platform_data = { + .name = "TMU01", + .channel_offset = 0x10, + .timer_bit = 1, + .clocksource_rating = 200, +}; + +#define PLATFORM_INFO(n, i) \ +{ \ + .parent = &platform_bus, \ + .name = #n, \ + .id = i, \ + .res = n ## i ## _resources, \ + .num_res = ARRAY_SIZE(n ## i ##_resources), \ + .data = &n ## i ##_platform_data, \ + .size_data = sizeof(n ## i ## _platform_data), \ +} + +struct platform_device_info platform_devinfo[] = { + PLATFORM_INFO(sh_tmu, 0), + PLATFORM_INFO(sh_tmu, 1), +}; + +void __init r8a7778_add_standard_devices(void) +{ + int i; + +#ifdef CONFIG_CACHE_L2X0 + void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); + if (base) { + /* + * Early BRESP enable, Shared attribute override enable, 64K*16way + * don't call iounmap(base) + */ + l2x0_init(base, 0x40470000, 0x82000fff); + } +#endif + + for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++) + platform_device_register_full(&platform_devinfo[i]); +} + +#define INT2SMSKCR0 0x82288 /* 0xfe782288 */ +#define INT2SMSKCR1 0x8228c /* 0xfe78228c */ + +#define INT2NTSR0 0x00018 /* 0xfe700018 */ +#define INT2NTSR1 0x0002c /* 0xfe70002c */ +static void __init r8a7778_init_irq_common(void) +{ + void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); + + BUG_ON(!base); + + /* route all interrupts to ARM */ + __raw_writel(0x73ffffff, base + INT2NTSR0); + __raw_writel(0xffffffff, base + INT2NTSR1); + + /* unmask all known interrupts in INTCS2 */ + __raw_writel(0x08330773, base + INT2SMSKCR0); + __raw_writel(0x00311110, base + INT2SMSKCR1); + + iounmap(base); +} + +void __init r8a7778_init_irq(void) +{ + void __iomem *gic_dist_base; + void __iomem *gic_cpu_base; + + gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); + gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); + BUG_ON(!gic_dist_base || !gic_cpu_base); + + /* use GIC to handle interrupts */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); + + r8a7778_init_irq_common(); +} + +void __init r8a7778_init_delay(void) +{ + shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ +} + +#ifdef CONFIG_USE_OF +void __init r8a7778_init_irq_dt(void) +{ + irqchip_init(); + r8a7778_init_irq_common(); +} + +static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { + {}, +}; + +void __init r8a7778_add_standard_devices_dt(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + r8a7778_auxdata_lookup, NULL); +} + +static const char *r8a7778_compat_dt[] __initdata = { + "renesas,r8a7778", + NULL, +}; + +DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") + .init_early = r8a7778_init_delay, + .init_irq = r8a7778_init_irq_dt, + .init_machine = r8a7778_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7778_compat_dt, +MACHINE_END + +#endif /* CONFIG_USE_OF */ From db331fc8fc715fa6af05bf5e9d428be2ec306475 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 21 Mar 2013 03:02:38 -0700 Subject: [PATCH 245/307] ARM: shmobile: r8a7778 SCIF support Add SCIF serial port support to the r8a7778 SoC by adding platform devices together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7778.c | 13 +++++++++++++ arch/arm/mach-shmobile/setup-r8a7778.c | 26 ++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index 387e3b74cc8c..f1277f45381e 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -58,16 +58,29 @@ static struct clk *main_clks[] = { }; enum { + MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */ [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ }; static struct clk_lookup lookups[] = { /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ }; diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 811ccf3c77a4..01c62bedf9cf 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,26 @@ #include #include +/* SCIF */ +#define SCIF_INFO(baseaddr, irq) \ +{ \ + .mapbase = baseaddr, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ + .scbrr_algo_id = SCBRR_ALGO_2, \ + .type = PORT_SCIF, \ + .irqs = SCIx_IRQ_MUXED(irq), \ +} + +static struct plat_sci_port scif_platform_data[] = { + SCIF_INFO(0xffe40000, gic_iid(0x66)), + SCIF_INFO(0xffe41000, gic_iid(0x67)), + SCIF_INFO(0xffe42000, gic_iid(0x68)), + SCIF_INFO(0xffe43000, gic_iid(0x69)), + SCIF_INFO(0xffe44000, gic_iid(0x6a)), + SCIF_INFO(0xffe45000, gic_iid(0x6b)), +}; + /* TMU */ static struct resource sh_tmu0_resources[] = { DEFINE_RES_MEM(0xffd80008, 12), @@ -88,6 +109,11 @@ void __init r8a7778_add_standard_devices(void) } #endif + for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) + platform_device_register_data(&platform_bus, "sh-sci", i, + &scif_platform_data[i], + sizeof(struct plat_sci_port)); + for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++) platform_device_register_full(&platform_devinfo[i]); } From 558f874029c904ca694a69e96b4b48c4d54686a3 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 21 Mar 2013 17:05:40 +0100 Subject: [PATCH 246/307] ARM: shmobile: sh73a0: add irqpin DT nodes Add DT nodes for the 4 irqpin interrupt controllers on sh73a0. We add them to sh73a0.dtsi, which is also used by configurations, doing all their device instantiation from board the .c code. We rely on the fact, that such configurations don't instantiate devices from the device-tree. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 81 +++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 8a59465d0231..7e71e3a85767 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -38,6 +38,87 @@ gic: interrupt-controller@f0001000 { <0xf0000100 0x100>; }; + irqpin0: irqpin@e6900000 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900000 4>, + <0xe6900010 4>, + <0xe6900020 1>, + <0xe6900040 1>, + <0xe6900060 1>; + interrupt-parent = <&gic>; + interrupts = <0 1 0x4 + 0 2 0x4 + 0 3 0x4 + 0 4 0x4 + 0 5 0x4 + 0 6 0x4 + 0 7 0x4 + 0 8 0x4>; + }; + + irqpin1: irqpin@e6900004 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupt-parent = <&gic>; + interrupts = <0 9 0x4 + 0 10 0x4 + 0 11 0x4 + 0 12 0x4 + 0 13 0x4 + 0 14 0x4 + 0 15 0x4 + 0 16 0x4>; + control-parent; + }; + + irqpin2: irqpin@e6900008 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900008 4>, + <0xe6900018 4>, + <0xe6900028 1>, + <0xe6900048 1>, + <0xe6900068 1>; + interrupt-parent = <&gic>; + interrupts = <0 17 0x4 + 0 18 0x4 + 0 19 0x4 + 0 20 0x4 + 0 21 0x4 + 0 22 0x4 + 0 23 0x4 + 0 24 0x4>; + }; + + irqpin3: irqpin@e690000c { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe690000c 4>, + <0xe690001c 4>, + <0xe690002c 1>, + <0xe690004c 1>, + <0xe690006c 1>; + interrupt-parent = <&gic>; + interrupts = <0 25 0x4 + 0 26 0x4 + 0 27 0x4 + 0 28 0x4 + 0 29 0x4 + 0 30 0x4 + 0 31 0x4 + 0 32 0x4>; + }; + i2c0: i2c@0xe6820000 { #address-cells = <1>; #size-cells = <0>; From 6722f6cb763203cab775297b6e9d00834af0d6d7 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Mar 2013 22:58:18 +0900 Subject: [PATCH 247/307] ARM: shmobile: Disallow PINCTRL without GPIOLIB Modify mach-shmobile to only select PINCTRL in case of ARCH_WANT_OPTIONAL_GPIOLIB is set. This fixes a build error triggered when adding a new SoC lacking GPIO software support (ARCH_WANT_OPTIONAL_GPIOLIB=n): CC drivers/tty/vt/keyboard.o In file included from drivers/pinctrl/core.c:30:0: include/asm-generic/gpio.h: In function 'gpio_get_value_cansleep': include/asm-generic/gpio.h:270:2: error: implicit declaration of function '__gpio_get_value' include/asm-generic/gpio.h: In function 'gpio_set_value_cansleep': include/asm-generic/gpio.h:276:2: error: implicit declaration of function '__gpio_set_value' drivers/pinctrl/core.c: In function 'pinctrl_ready_for_gpio_range': drivers/pinctrl/core.c:297:9: error: implicit declaration of function 'gpio_to_chip' drivers/pinctrl/core.c:297:27: warning: initialization makes pointer from integer without a cast drivers/pinctrl/core.c:304:45: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:26: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:39: error: dereferencing pointer to incomplete type make[2]: *** [drivers/pinctrl/core.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make[1]: *** Waiting for unfinished jobs.... LD drivers/sh/built-in.o Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b714695b01b..b63902e7cacd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -725,7 +725,7 @@ config ARCH_SHMOBILE select MULTI_IRQ_HANDLER select NEED_MACH_MEMORY_H select NO_IOPORT - select PINCTRL + select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB select PM_GENERIC_DOMAINS if PM select SPARSE_IRQ help From c91cf2fad00f24bfe268d30b75e4015aaa326c04 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 25 Mar 2013 23:18:15 -0700 Subject: [PATCH 248/307] ARM: shmobile: r8a73a4: add thermal driver support You can get current thermal by > cat /sys/class/thermal/thermal_zone?/temp Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 7 +++++++ arch/arm/mach-shmobile/clock-r8a73a4.c | 13 ++++++++++++- arch/arm/mach-shmobile/setup-r8a73a4.c | 15 +++++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 4c68ba15727c..7db5b504e64c 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -84,4 +84,11 @@ irqc1: interrupt-controller@e61c0200 { <0 56 4>, <0 57 4>; }; + thermal@e61f0000 { + compatible = "renesas,rcar-thermal"; + reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>, + <0xe61f0200 0x38>, <0xe61f0300 0x38>; + interrupt-parent = <&gic>; + interrupts = <0 69 4>; + }; }; diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 037713bdff3f..e710c00c3822 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -29,6 +29,7 @@ #define MPCKCR 0xe6150080 #define SMSTPCR2 0xe6150138 +#define SMSTPCR5 0xe6150144 static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, @@ -56,7 +57,12 @@ static struct clk *main_clks[] = { &extal2_clk, }; -enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP_NR }; +enum { + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, + MSTP522, + MSTP_NR +}; + static struct clk mstp_clks[MSTP_NR] = { [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ @@ -64,6 +70,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ }; static struct clk_lookup lookups[] = { @@ -73,6 +80,10 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), + CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + + /* for DT */ + CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), }; void __init r8a73a4_clock_init(void) diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index c2d86f30cde4..c5a75a7a508f 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -155,6 +155,20 @@ static const struct resource irqc1_resources[] = { &irqc##idx##_data, \ sizeof(struct renesas_irqc_config)) +/* Thermal0 -> Thermal2 */ +static const struct resource thermal0_resources[] = { + DEFINE_RES_MEM(0xe61f0000, 0x14), + DEFINE_RES_MEM(0xe61f0100, 0x38), + DEFINE_RES_MEM(0xe61f0200, 0x38), + DEFINE_RES_MEM(0xe61f0300, 0x38), + DEFINE_RES_IRQ(gic_spi(69)), +}; + +#define r8a73a4_register_thermal() \ + platform_device_register_simple("rcar_thermal", -1, \ + thermal0_resources, \ + ARRAY_SIZE(thermal0_resources)) + void __init r8a73a4_add_standard_devices(void) { r8a73a4_register_scif(SCIFA0); @@ -165,6 +179,7 @@ void __init r8a73a4_add_standard_devices(void) r8a73a4_register_scif(SCIFB3); r8a73a4_register_irqc(0); r8a73a4_register_irqc(1); + r8a73a4_register_thermal(); } #ifdef CONFIG_USE_OF From 0b7d78202260162057248875b1c9bac70d041e58 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Wed, 27 Mar 2013 14:54:04 +0100 Subject: [PATCH 249/307] ARM: shmobile: r8a7740: Migrate from INTC to GIC With the added capabilty of the intc_irqpin driver to handle shared external IRQs, all prerequisites are fulfilled and we are ready to migrate completely to GIC. This includes the following steps: - Kconfig: select ARM_GIC and RENESAS_INTC_IRQPIN - intc-r8a7740: Throw out all legacy INTC code and init the GIC. We need to mask out all shared IRQs as it is needed by the shared intc_irqpin driver. - setup-r8a7740: Add 4 irqpin devices to handle external IRQs and update all IRQ numbers to point to the GIC SPI. - board-armadillo: Update all IRQ numbers to point to the GIC SPI. - pfc-r8a7740: Update all IRQ numbers of the GPIOs to point to the GIC SPI. Signed-off-by: Bastian Hecht Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 2 + .../arm/mach-shmobile/board-armadillo800eva.c | 35 +- arch/arm/mach-shmobile/intc-r8a7740.c | 637 +----------------- arch/arm/mach-shmobile/setup-r8a7740.c | 192 +++++- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 64 +- 5 files changed, 237 insertions(+), 693 deletions(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 49cba4a511df..d569c34b1c86 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -30,8 +30,10 @@ config ARCH_R8A73A4 config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC select CPU_V7 select SH_CLK_CPG + select RENESAS_INTC_IRQPIN config ARCH_R8A7778 bool "R-Car M1 (R8A77780)" diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index f2ec0777cfbe..e451327278af 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -145,7 +145,7 @@ * see * usbhsf_power_ctrl() */ -#define IRQ7 evt2irq(0x02e0) +#define IRQ7 irq_pin(7) #define USBCR1 IOMEM(0xe605810a) #define USBH 0xC6700000 #define USBH_USBCTR 0x10834 @@ -330,7 +330,7 @@ static struct resource usbhsf_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = evt2irq(0x0A20), + .start = gic_spi(51), .flags = IORESOURCE_IRQ, }, }; @@ -363,7 +363,7 @@ static struct resource sh_eth_resources[] = { .end = 0xe9a02000 - 1, .flags = IORESOURCE_MEM, }, { - .start = evt2irq(0x0500), + .start = gic_spi(110), .flags = IORESOURCE_IRQ, }, }; @@ -417,7 +417,7 @@ static struct resource lcdc0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x580), + .start = gic_spi(177), .flags = IORESOURCE_IRQ, }, }; @@ -452,7 +452,7 @@ static struct resource hdmi_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x1700), + .start = gic_spi(131), .flags = IORESOURCE_IRQ, }, [2] = { @@ -514,7 +514,7 @@ static struct resource hdmi_lcdc_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x1780), + .start = gic_spi(178), .flags = IORESOURCE_IRQ, }, }; @@ -574,7 +574,7 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = * We can use IRQ31 as card detect irq, * but it needs chattering removal operation */ -#define IRQ31 evt2irq(0x33E0) +#define IRQ31 irq_pin(31) static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, @@ -596,12 +596,12 @@ static struct resource sdhi0_resources[] = { */ { .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = evt2irq(0x0E20), + .start = gic_spi(118), .flags = IORESOURCE_IRQ, }, { .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = evt2irq(0x0E40), + .start = gic_spi(119), .flags = IORESOURCE_IRQ, }, }; @@ -633,15 +633,15 @@ static struct resource sdhi1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x0E80), + .start = gic_spi(121), .flags = IORESOURCE_IRQ, }, [2] = { - .start = evt2irq(0x0EA0), + .start = gic_spi(122), .flags = IORESOURCE_IRQ, }, [3] = { - .start = evt2irq(0x0EC0), + .start = gic_spi(123), .flags = IORESOURCE_IRQ, }, }; @@ -674,12 +674,12 @@ static struct resource sh_mmcif_resources[] = { }, [1] = { /* MMC ERR */ - .start = evt2irq(0x1AC0), + .start = gic_spi(56), .flags = IORESOURCE_IRQ, }, [2] = { /* MMC NOR */ - .start = evt2irq(0x1AE0), + .start = gic_spi(57), .flags = IORESOURCE_IRQ, }, }; @@ -756,7 +756,7 @@ static struct resource ceu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x0500), + .start = gic_spi(160), .flags = IORESOURCE_IRQ, }, [2] = { @@ -798,7 +798,7 @@ static struct resource fsi_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x1840), + .start = gic_spi(9), .flags = IORESOURCE_IRQ, }, }; @@ -881,7 +881,7 @@ static struct platform_device i2c_gpio_device = { static struct i2c_board_info i2c0_devices[] = { { I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = evt2irq(0x0340), + .irq = irq_pin(10), }, { I2C_BOARD_INFO("wm8978", 0x1a), @@ -1207,7 +1207,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") .map_io = r8a7740_map_io, .init_early = eva_add_early_devices, .init_irq = r8a7740_init_irq, - .handle_irq = shmobile_handle_irq_intc, .init_machine = eva_init, .init_late = shmobile_init_late, .init_time = eva_earlytimer_init, diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c index 9a69a31918ba..b741c8409a5a 100644 --- a/arch/arm/mach-shmobile/intc-r8a7740.c +++ b/arch/arm/mach-shmobile/intc-r8a7740.c @@ -18,620 +18,39 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include #include -#include -#include #include -#include -#include -#include -#include -#include - -/* - * INTCA - */ -enum { - UNUSED_INTCA = 0, - - /* interrupt sources INTCA */ - DIRC, - ATAPI, - IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI, - AP_ARM_COMMTX, AP_ARM_COMMRX, - MFI, MFIS, - BBIF1, BBIF2, - USBHSDMAC, - USBF_OUL_SOF, USBF_IXL_INT, - SGX540, - CMT1_0, CMT1_1, CMT1_2, CMT1_3, - CMT2, - CMT3, - KEYSC, - SCIFA0, SCIFA1, SCIFA2, SCIFA3, - MSIOF2, MSIOF1, - SCIFA4, SCIFA5, SCIFB, - FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, - SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3, - SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3, - AP_ARM_L2CINT, - IRDA, - TPU0, - SCIFA6, SCIFA7, - GbEther, - ICBS0, - DDM, - SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3, - RWDT0, - DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, - DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, - DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, - DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, - DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, - DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, - SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, - HDMI, - USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND, - RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, - SPU2_0, SPU2_1, - FSI, FMSI, - HDMI_SSS, HDMI_KEY, - IPMMU, - AP_ARM_CTIIRQ, AP_ARM_PMURQ, - MFIS2, - CPORTR2S, - CMT14, CMT15, - MMCIF_0, MMCIF_1, MMCIF_2, - SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, - STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4, - - /* interrupt groups INTCA */ - DMAC1_1, DMAC1_2, - DMAC2_1, DMAC2_2, - DMAC3_1, DMAC3_2, - AP_ARM1, AP_ARM2, - SDHI0, SDHI1, SDHI2, - SHWYSTAT, - USBF, USBH1, USBH2, - RSPI, SPU2, FLCTL, IIC1, -}; - -static struct intc_vect intca_vectors[] __initdata = { - INTC_VECT(DIRC, 0x0560), - INTC_VECT(ATAPI, 0x05E0), - INTC_VECT(IIC1_ALI, 0x0780), - INTC_VECT(IIC1_TACKI, 0x07A0), - INTC_VECT(IIC1_WAITI, 0x07C0), - INTC_VECT(IIC1_DTEI, 0x07E0), - INTC_VECT(AP_ARM_COMMTX, 0x0840), - INTC_VECT(AP_ARM_COMMRX, 0x0860), - INTC_VECT(MFI, 0x0900), - INTC_VECT(MFIS, 0x0920), - INTC_VECT(BBIF1, 0x0940), - INTC_VECT(BBIF2, 0x0960), - INTC_VECT(USBHSDMAC, 0x0A00), - INTC_VECT(USBF_OUL_SOF, 0x0A20), - INTC_VECT(USBF_IXL_INT, 0x0A40), - INTC_VECT(SGX540, 0x0A60), - INTC_VECT(CMT1_0, 0x0B00), - INTC_VECT(CMT1_1, 0x0B20), - INTC_VECT(CMT1_2, 0x0B40), - INTC_VECT(CMT1_3, 0x0B60), - INTC_VECT(CMT2, 0x0B80), - INTC_VECT(CMT3, 0x0BA0), - INTC_VECT(KEYSC, 0x0BE0), - INTC_VECT(SCIFA0, 0x0C00), - INTC_VECT(SCIFA1, 0x0C20), - INTC_VECT(SCIFA2, 0x0C40), - INTC_VECT(SCIFA3, 0x0C60), - INTC_VECT(MSIOF2, 0x0C80), - INTC_VECT(MSIOF1, 0x0D00), - INTC_VECT(SCIFA4, 0x0D20), - INTC_VECT(SCIFA5, 0x0D40), - INTC_VECT(SCIFB, 0x0D60), - INTC_VECT(FLCTL_FLSTEI, 0x0D80), - INTC_VECT(FLCTL_FLTENDI, 0x0DA0), - INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0), - INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0), - INTC_VECT(SDHI0_0, 0x0E00), - INTC_VECT(SDHI0_1, 0x0E20), - INTC_VECT(SDHI0_2, 0x0E40), - INTC_VECT(SDHI0_3, 0x0E60), - INTC_VECT(SDHI1_0, 0x0E80), - INTC_VECT(SDHI1_1, 0x0EA0), - INTC_VECT(SDHI1_2, 0x0EC0), - INTC_VECT(SDHI1_3, 0x0EE0), - INTC_VECT(AP_ARM_L2CINT, 0x0FA0), - INTC_VECT(IRDA, 0x0480), - INTC_VECT(TPU0, 0x04A0), - INTC_VECT(SCIFA6, 0x04C0), - INTC_VECT(SCIFA7, 0x04E0), - INTC_VECT(GbEther, 0x0500), - INTC_VECT(ICBS0, 0x0540), - INTC_VECT(DDM, 0x1140), - INTC_VECT(SDHI2_0, 0x1200), - INTC_VECT(SDHI2_1, 0x1220), - INTC_VECT(SDHI2_2, 0x1240), - INTC_VECT(SDHI2_3, 0x1260), - INTC_VECT(RWDT0, 0x1280), - INTC_VECT(DMAC1_1_DEI0, 0x2000), - INTC_VECT(DMAC1_1_DEI1, 0x2020), - INTC_VECT(DMAC1_1_DEI2, 0x2040), - INTC_VECT(DMAC1_1_DEI3, 0x2060), - INTC_VECT(DMAC1_2_DEI4, 0x2080), - INTC_VECT(DMAC1_2_DEI5, 0x20A0), - INTC_VECT(DMAC1_2_DADERR, 0x20C0), - INTC_VECT(DMAC2_1_DEI0, 0x2100), - INTC_VECT(DMAC2_1_DEI1, 0x2120), - INTC_VECT(DMAC2_1_DEI2, 0x2140), - INTC_VECT(DMAC2_1_DEI3, 0x2160), - INTC_VECT(DMAC2_2_DEI4, 0x2180), - INTC_VECT(DMAC2_2_DEI5, 0x21A0), - INTC_VECT(DMAC2_2_DADERR, 0x21C0), - INTC_VECT(DMAC3_1_DEI0, 0x2200), - INTC_VECT(DMAC3_1_DEI1, 0x2220), - INTC_VECT(DMAC3_1_DEI2, 0x2240), - INTC_VECT(DMAC3_1_DEI3, 0x2260), - INTC_VECT(DMAC3_2_DEI4, 0x2280), - INTC_VECT(DMAC3_2_DEI5, 0x22A0), - INTC_VECT(DMAC3_2_DADERR, 0x22C0), - INTC_VECT(SHWYSTAT_RT, 0x1300), - INTC_VECT(SHWYSTAT_HS, 0x1320), - INTC_VECT(SHWYSTAT_COM, 0x1340), - INTC_VECT(USBH_INT, 0x1540), - INTC_VECT(USBH_OHCI, 0x1560), - INTC_VECT(USBH_EHCI, 0x1580), - INTC_VECT(USBH_PME, 0x15A0), - INTC_VECT(USBH_BIND, 0x15C0), - INTC_VECT(HDMI, 0x1700), - INTC_VECT(RSPI_OVRF, 0x1780), - INTC_VECT(RSPI_SPTEF, 0x17A0), - INTC_VECT(RSPI_SPRF, 0x17C0), - INTC_VECT(SPU2_0, 0x1800), - INTC_VECT(SPU2_1, 0x1820), - INTC_VECT(FSI, 0x1840), - INTC_VECT(FMSI, 0x1860), - INTC_VECT(HDMI_SSS, 0x18A0), - INTC_VECT(HDMI_KEY, 0x18C0), - INTC_VECT(IPMMU, 0x1920), - INTC_VECT(AP_ARM_CTIIRQ, 0x1980), - INTC_VECT(AP_ARM_PMURQ, 0x19A0), - INTC_VECT(MFIS2, 0x1A00), - INTC_VECT(CPORTR2S, 0x1A20), - INTC_VECT(CMT14, 0x1A40), - INTC_VECT(CMT15, 0x1A60), - INTC_VECT(MMCIF_0, 0x1AA0), - INTC_VECT(MMCIF_1, 0x1AC0), - INTC_VECT(MMCIF_2, 0x1AE0), - INTC_VECT(SIM_ERI, 0x1C00), - INTC_VECT(SIM_RXI, 0x1C20), - INTC_VECT(SIM_TXI, 0x1C40), - INTC_VECT(SIM_TEI, 0x1C60), - INTC_VECT(STPRO_0, 0x1C80), - INTC_VECT(STPRO_1, 0x1CA0), - INTC_VECT(STPRO_2, 0x1CC0), - INTC_VECT(STPRO_3, 0x1CE0), - INTC_VECT(STPRO_4, 0x1D00), -}; - -static struct intc_group intca_groups[] __initdata = { - INTC_GROUP(DMAC1_1, - DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), - INTC_GROUP(DMAC1_2, - DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR), - INTC_GROUP(DMAC2_1, - DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), - INTC_GROUP(DMAC2_2, - DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR), - INTC_GROUP(DMAC3_1, - DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), - INTC_GROUP(DMAC3_2, - DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR), - INTC_GROUP(AP_ARM1, - AP_ARM_COMMTX, AP_ARM_COMMRX), - INTC_GROUP(AP_ARM2, - AP_ARM_CTIIRQ, AP_ARM_PMURQ), - INTC_GROUP(USBF, - USBF_OUL_SOF, USBF_IXL_INT), - INTC_GROUP(SDHI0, - SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3), - INTC_GROUP(SDHI1, - SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3), - INTC_GROUP(SDHI2, - SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3), - INTC_GROUP(SHWYSTAT, - SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), - INTC_GROUP(USBH1, /* FIXME */ - USBH_INT, USBH_OHCI), - INTC_GROUP(USBH2, /* FIXME */ - USBH_EHCI, - USBH_PME, USBH_BIND), - INTC_GROUP(RSPI, - RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF), - INTC_GROUP(SPU2, - SPU2_0, SPU2_1), - INTC_GROUP(FLCTL, - FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), - INTC_GROUP(IIC1, - IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI), -}; - -static struct intc_mask_reg intca_mask_registers[] __initdata = { - { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8, - { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, - 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, - { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8, - { ATAPI, 0, DIRC, 0, - DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, - { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8, - { 0, 0, 0, 0, - BBIF1, BBIF2, MFIS, MFI } }, - { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8, - { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, - DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, - { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8, - { DDM, 0, 0, 0, - 0, 0, 0, 0 } }, - { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8, - { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, - SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8, - { SCIFB, SCIFA5, SCIFA4, MSIOF1, - 0, 0, MSIOF2, 0 } }, - { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8, - { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0, - FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, - { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8, - { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0, - 0, USBHSDMAC, 0, AP_ARM_L2CINT } }, - { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8, - { CMT1_3, CMT1_2, CMT1_1, CMT1_0, - CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } }, - { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8, - { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, - 0, 0, 0, 0 } }, - { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8, - { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI, - ICBS0, 0, 0, 0 } }, - { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8, - { 0, 0, TPU0, SCIFA6, - SCIFA7, GbEther, 0, 0 } }, - { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8, - { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0, - 0, CMT3, 0, RWDT0 } }, - { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8, - { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, - 0, 0, 0, 0 } }, - /* IMR1A3 / IMCR1A3 */ - { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8, - { 0, 0, USBH_INT, USBH_OHCI, - USBH_EHCI, USBH_PME, USBH_BIND, 0 } }, - /* IMR3A3 / IMCR3A3 */ - { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8, - { HDMI, 0, 0, 0, - RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } }, - { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8, - { SPU2_0, SPU2_1, FSI, FMSI, - 0, HDMI_SSS, HDMI_KEY, 0 } }, - { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8, - { 0, IPMMU, 0, 0, - AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } }, - { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8, - { MFIS2, CPORTR2S, CMT14, CMT15, - 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, - /* IMR8A3 / IMCR8A3 */ - { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8, - { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, - STPRO_0, STPRO_1, STPRO_2, STPRO_3 } }, - { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8, - { STPRO_4, 0, 0, 0, - 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg intca_prio_registers[] __initdata = { - { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } }, - { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, - { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } }, - { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } }, - { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } }, - { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2, - SGX540, CMT1_0 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC, - FLCTL, SDHI0 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, - { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, - AP_ARM_L2CINT, 0 } }, - { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } }, - { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6, - SCIFA7, GbEther } }, - { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, - { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, - { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, - /* IPRBA3 */ - /* IPRCA3 */ - /* IPRDA3 */ - { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } }, - { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } }, - /* IPRGA3 */ - /* IPRHA3 */ - { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } }, - { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } }, - { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, - { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } }, - { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } }, - { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, - { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, - CMT14, CMT15 } }, - { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, - /* IPRQA3 */ - /* IPRRA3 */ - { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI, - SIM_TXI, SIM_TEI } }, - { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1, - STPRO_2, STPRO_3 } }, - { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca", - intca_vectors, intca_groups, - intca_mask_registers, intca_prio_registers, - NULL); - -INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, - INTC_VECT, "r8a7740-intca-irq-pins"); - - -/* - * INTCS - */ -enum { - UNUSED_INTCS = 0, - - INTCS, - - /* interrupt sources INTCS */ - - /* HUDI */ - /* STPRO */ - /* RTDMAC(1) */ - VPU5HA2, - _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT, - /* MFI */ - /* BBIF2 */ - VPU5F, - _2DG_BRK_INT, - /* SGX540 */ - /* 2DDMAC */ - /* IPMMU */ - /* RTDMAC 2 */ - /* KEYSC */ - /* MSIOF */ - IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI, - TMU0_0, TMU0_1, TMU0_2, - CMT0, - /* CMT2 */ - LMB, - CTI, - VOU, - /* RWDT0 */ - ICB, - VIO6C, - CEU20, CEU21, - JPU, - LCDC0, - LCRC, - /* RTDMAC2(1) */ - /* RTDMAC2(2) */ - LCDC1, - /* SPU2 */ - /* FSI */ - /* FMSI */ - TMU1_0, TMU1_1, TMU1_2, - CMT4, - DISP, - DSRV, - /* MFIS2 */ - CPORTS2R, - - /* interrupt groups INTCS */ - _2DG1, - IIC0, TMU1, -}; - -static struct intc_vect intcs_vectors[] = { - /* HUDI */ - /* STPRO */ - /* RTDMAC(1) */ - INTCS_VECT(VPU5HA2, 0x0880), - INTCS_VECT(_2DG_TRAP, 0x08A0), - INTCS_VECT(_2DG_GPM_INT, 0x08C0), - INTCS_VECT(_2DG_CER_INT, 0x08E0), - /* MFI */ - /* BBIF2 */ - INTCS_VECT(VPU5F, 0x0980), - INTCS_VECT(_2DG_BRK_INT, 0x09A0), - /* SGX540 */ - /* 2DDMAC */ - /* IPMMU */ - /* RTDMAC(2) */ - /* KEYSC */ - /* MSIOF */ - INTCS_VECT(IIC0_ALI, 0x0E00), - INTCS_VECT(IIC0_TACKI, 0x0E20), - INTCS_VECT(IIC0_WAITI, 0x0E40), - INTCS_VECT(IIC0_DTEI, 0x0E60), - INTCS_VECT(TMU0_0, 0x0E80), - INTCS_VECT(TMU0_1, 0x0EA0), - INTCS_VECT(TMU0_2, 0x0EC0), - INTCS_VECT(CMT0, 0x0F00), - /* CMT2 */ - INTCS_VECT(LMB, 0x0F60), - INTCS_VECT(CTI, 0x0400), - INTCS_VECT(VOU, 0x0420), - /* RWDT0 */ - INTCS_VECT(ICB, 0x0480), - INTCS_VECT(VIO6C, 0x04E0), - INTCS_VECT(CEU20, 0x0500), - INTCS_VECT(CEU21, 0x0520), - INTCS_VECT(JPU, 0x0560), - INTCS_VECT(LCDC0, 0x0580), - INTCS_VECT(LCRC, 0x05A0), - /* RTDMAC2(1) */ - /* RTDMAC2(2) */ - INTCS_VECT(LCDC1, 0x1780), - /* SPU2 */ - /* FSI */ - /* FMSI */ - INTCS_VECT(TMU1_0, 0x1900), - INTCS_VECT(TMU1_1, 0x1920), - INTCS_VECT(TMU1_2, 0x1940), - INTCS_VECT(CMT4, 0x1980), - INTCS_VECT(DISP, 0x19A0), - INTCS_VECT(DSRV, 0x19C0), - /* MFIS2 */ - INTCS_VECT(CPORTS2R, 0x1A20), - - INTC_VECT(INTCS, 0xf80), -}; - -static struct intc_group intcs_groups[] __initdata = { - INTC_GROUP(_2DG1, /*FIXME*/ - _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP), - INTC_GROUP(IIC0, - IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI), - INTC_GROUP(TMU1, - TMU1_0, TMU1_1, TMU1_2), -}; - -static struct intc_mask_reg intcs_mask_registers[] = { - /* IMR0SA / IMCR0SA */ /* all 0 */ - { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8, - { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2, - 0, 0, 0, 0 /*STPRO*/ } }, - { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8, - { 0/*STPRO*/, 0, CEU21, VPU5F, - 0/*BBIF2*/, 0, 0, 0/*MFI*/ } }, - { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8, - { 0, 0, 0, 0, /*2DDMAC*/ - VIO6C, 0, 0, ICB } }, - { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8, - { 0, 0, VOU, CTI, - JPU, 0, LCRC, LCDC0 } }, - /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/ - /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/ - { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8, - { 0, TMU0_2, TMU0_1, TMU0_0, - 0, 0, 0, 0 } }, - { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8, - { 0, 0, 0, 0, - CEU20, 0, 0, 0 } }, - { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8, - { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0, - 0, 0, 0, 0 } }, - /* IMR10SA / IMCR10SA */ /*IPMMU*/ - { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8, - { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI, - 0, _2DG_BRK_INT, LMB, 0 } }, - /* IMR12SA / IMCR12SA */ - /* IMR13SA / IMCR13SA */ - /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/ - /* IMR1SA3 / IMCR1SA3 */ - /* IMR2SA3 / IMCR2SA3 */ - /* IMR3SA3 / IMCR3SA3 */ - { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8, - { 0, 0, 0, 0, - LCDC1, 0, 0, 0 } }, - /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */ - { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8, - { TMU1_0, TMU1_1, TMU1_2, 0, - CMT4, DISP, DSRV, 0 } }, - { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8, - { 0/*MFIS2*/, CPORTS2R, 0, 0, - 0, 0, 0, 0 } }, - { /* INTAMASK */ 0xffd20104, 0, 16, - { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, INTCS } }, -}; - -/* Priority is needed for INTCA to receive the INTCS interrupt */ -static struct intc_prio_reg intcs_prio_registers[] = { - { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } }, - { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } }, - /* IPRCS */ /*BBIF2*/ - /* IPRDS */ - { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2, - 0/*MFI*/, VPU5F } }, - { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/, - 0/*CMT2*/, CMT0 } }, - { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1, - TMU0_2, _2DG1 } }, - { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/, - _2DG_BRK_INT/*FIXME*/ } }, - { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } }, - { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } }, - { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } }, - { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } }, - /* IPRMS */ /*RWDT0*/ - /* IPRAS3 */ /*RTDMAC2(1)*/ - /* IPRBS3 */ /*RTDMAC2(2)*/ - /* IPRCS3 */ - /* IPRDS3 */ - /* IPRES3 */ - /* IPRFS3 */ - /* IPRGS3 */ - /* IPRHS3 */ - /* IPRIS3 */ - { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } }, - /* IPRKS3 */ /*SPU2/FSI/FMSi*/ - /* IPRLS3 */ - { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, - { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } }, - { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } }, - /* IPRPS3 */ -}; - -static struct resource intcs_resources[] __initdata = { - [0] = { - .start = 0xffd20000, - .end = 0xffd201ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xffd50000, - .end = 0xffd501ff, - .flags = IORESOURCE_MEM, - } -}; - -static struct intc_desc intcs_desc __initdata = { - .name = "r8a7740-intcs", - .resource = intcs_resources, - .num_resources = ARRAY_SIZE(intcs_resources), - .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, - intcs_prio_registers, NULL, NULL), -}; - -static void intcs_demux(unsigned int irq, struct irq_desc *desc) -{ - void __iomem *reg = (void *)irq_get_handler_data(irq); - unsigned int evtcodeas = ioread32(reg); - - generic_handle_irq(intcs_evt2irq(evtcodeas)); -} +#include void __init r8a7740_init_irq(void) { - void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); + void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); + void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); + void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); + void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); - register_intc_controller(&intca_desc); - register_intc_controller(&intca_irq_pins_desc); - register_intc_controller(&intcs_desc); + /* initialize the Generic Interrupt Controller PL390 r0p0 */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); - /* demux using INTEVTSA */ - irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); - irq_set_chained_handler(evt2irq(0xf80), intcs_demux); + /* route signals to GIC */ + iowrite32(0x0, pfc_inta_ctrl); + + /* + * To mask the shared interrupt to SPI 149 we must ensure to set + * PRIO *and* MASK. Else we run into IRQ floods when registering + * the intc_irqpin devices + */ + iowrite32(0x0, intc_prio_base + 0x0); + iowrite32(0x0, intc_prio_base + 0x4); + iowrite32(0x0, intc_prio_base + 0x8); + iowrite32(0x0, intc_prio_base + 0xc); + iowrite8(0xff, intc_msk_base + 0x0); + iowrite8(0xff, intc_msk_base + 0x4); + iowrite8(0xff, intc_msk_base + 0x8); + iowrite8(0xff, intc_msk_base + 0xc); + + iounmap(intc_prio_base); + iounmap(intc_msk_base); + iounmap(pfc_inta_ctrl); } diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 8b85d4d8fab6..228d7aba4a7c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void) platform_device_register(&r8a7740_pfc_device); } +static struct renesas_intc_irqpin_config irqpin0_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ +}; + +static struct resource irqpin0_resources[] = { + DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ + DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ + DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ + DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ + DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ +}; + +static struct platform_device irqpin0_device = { + .name = "renesas_intc_irqpin", + .id = 0, + .resource = irqpin0_resources, + .num_resources = ARRAY_SIZE(irqpin0_resources), + .dev = { + .platform_data = &irqpin0_platform_data, + }, +}; + +static struct renesas_intc_irqpin_config irqpin1_platform_data = { + .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ +}; + +static struct resource irqpin1_resources[] = { + DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ + DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ + DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ + DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ + DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */ +}; + +static struct platform_device irqpin1_device = { + .name = "renesas_intc_irqpin", + .id = 1, + .resource = irqpin1_resources, + .num_resources = ARRAY_SIZE(irqpin1_resources), + .dev = { + .platform_data = &irqpin1_platform_data, + }, +}; + +static struct renesas_intc_irqpin_config irqpin2_platform_data = { + .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ +}; + +static struct resource irqpin2_resources[] = { + DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ + DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */ + DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */ + DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */ + DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */ +}; + +static struct platform_device irqpin2_device = { + .name = "renesas_intc_irqpin", + .id = 2, + .resource = irqpin2_resources, + .num_resources = ARRAY_SIZE(irqpin2_resources), + .dev = { + .platform_data = &irqpin2_platform_data, + }, +}; + +static struct renesas_intc_irqpin_config irqpin3_platform_data = { + .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ +}; + +static struct resource irqpin3_resources[] = { + DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */ + DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ + DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ + DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ + DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */ +}; + +static struct platform_device irqpin3_device = { + .name = "renesas_intc_irqpin", + .id = 3, + .resource = irqpin3_resources, + .num_resources = ARRAY_SIZE(irqpin3_resources), + .dev = { + .platform_data = &irqpin3_platform_data, + }, +}; + /* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { .mapbase = 0xe6c40000, @@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), + .irqs = SCIx_IRQ_MUXED(gic_spi(100)), }; static struct platform_device scif0_device = { @@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), + .irqs = SCIx_IRQ_MUXED(gic_spi(101)), }; static struct platform_device scif1_device = { @@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), + .irqs = SCIx_IRQ_MUXED(gic_spi(102)), }; static struct platform_device scif2_device = { @@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), + .irqs = SCIx_IRQ_MUXED(gic_spi(103)), }; static struct platform_device scif3_device = { @@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), + .irqs = SCIx_IRQ_MUXED(gic_spi(104)), }; static struct platform_device scif4_device = { @@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), + .irqs = SCIx_IRQ_MUXED(gic_spi(105)), }; static struct platform_device scif5_device = { @@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), + .irqs = SCIx_IRQ_MUXED(gic_spi(106)), }; static struct platform_device scif6_device = { @@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), + .irqs = SCIx_IRQ_MUXED(gic_spi(107)), }; static struct platform_device scif7_device = { @@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFB, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), + .irqs = SCIx_IRQ_MUXED(gic_spi(108)), }; static struct platform_device scifb_device = { @@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x0b00), + .start = gic_spi(58), .flags = IORESOURCE_IRQ, }, }; @@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xe80), + .start = gic_spi(198), .flags = IORESOURCE_IRQ, }, }; @@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xea0), + .start = gic_spi(199), .flags = IORESOURCE_IRQ, }, }; @@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xec0), + .start = gic_spi(200), .flags = IORESOURCE_IRQ, }, }; @@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = { }; static struct platform_device *r8a7740_early_devices[] __initdata = { + &irqpin0_device, + &irqpin1_device, + &irqpin2_device, + &irqpin3_device, &scif0_device, &scif1_device, &scif2_device, @@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = { }, { .name = "error_irq", - .start = evt2irq(0x20c0), - .end = evt2irq(0x20c0), + .start = gic_spi(34), + .end = gic_spi(34), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = evt2irq(0x2000), - .end = evt2irq(0x20a0), + .start = gic_spi(28), + .end = gic_spi(33), .flags = IORESOURCE_IRQ, }, }; @@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = { }, { .name = "error_irq", - .start = evt2irq(0x21c0), - .end = evt2irq(0x21c0), + .start = gic_spi(41), + .end = gic_spi(41), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = evt2irq(0x2100), - .end = evt2irq(0x21a0), + .start = gic_spi(35), + .end = gic_spi(40), .flags = IORESOURCE_IRQ, }, }; @@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = { }, { .name = "error_irq", - .start = evt2irq(0x22c0), - .end = evt2irq(0x22c0), + .start = gic_spi(48), + .end = gic_spi(48), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = evt2irq(0x2200), - .end = evt2irq(0x22a0), + .start = gic_spi(42), + .end = gic_spi(47), .flags = IORESOURCE_IRQ, }, }; @@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = { }, { /* IRQ for channels */ - .start = evt2irq(0x0a00), - .end = evt2irq(0x0a00), + .start = gic_spi(49), + .end = gic_spi(49), .flags = IORESOURCE_IRQ, }, }; @@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xe00), - .end = intcs_evt2irq(0xe60), + .start = gic_spi(201), + .end = gic_spi(204), .flags = IORESOURCE_IRQ, }, }; @@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x780), /* IIC1_ALI1 */ - .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ + .start = gic_spi(70), /* IIC1_ALI1 */ + .end = gic_spi(73), /* IIC1_DTEI1 */ .flags = IORESOURCE_IRQ, }, }; @@ -738,8 +863,8 @@ static struct platform_device i2c1_device = { static struct resource pmu_resources[] = { [0] = { - .start = evt2irq(0x19a0), - .end = evt2irq(0x19a0), + .start = gic_spi(83), + .end = gic_spi(83), .flags = IORESOURCE_IRQ, }, }; @@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") .map_io = r8a7740_map_io, .init_early = r8a7740_add_early_devices_dt, .init_irq = r8a7740_init_irq, - .handle_irq = shmobile_handle_irq_intc, .init_machine = r8a7740_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = r8a7740_boards_compat_dt, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 214788c4a606..2b528280e3c1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2545,38 +2545,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = { }; static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ - PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ - PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ - PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ - PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ - PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ - PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ - PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ - PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ - PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ - PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ - PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ - PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ - PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ - PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ - PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ - PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ - PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ - PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ - PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ - PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ - PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ - PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ - PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ - PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ - PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ - PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ - PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ - PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ - PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ - PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ - PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ + PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ + PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ + PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ + PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ + PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ + PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ + PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ + PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ + PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ + PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ + PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ + PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ + PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ + PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ + PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ + PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ + PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ + PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ + PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ + PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ + PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ + PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ + PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ + PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ + PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ + PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ + PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ + PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ + PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ + PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ + PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ + PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ }; struct sh_pfc_soc_info r8a7740_pinmux_info = { From fe7aa82d62d13d97c9a786707c467357cb8bddc3 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 7 Mar 2013 20:00:48 +0100 Subject: [PATCH 250/307] ARM: shmobile: sh73a0: add a TWD clock Add a TWD clock on sh73a0 for the smp_twd driver to properly update the clock's frequency upon cpufreq events. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 34b5c5ae4cbd..a57ec151674e 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -288,6 +288,20 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), }; +static unsigned long twd_recalc(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 4; +} + +static struct sh_clk_ops twd_clk_ops = { + .recalc = twd_recalc, +}; + +static struct clk twd_clk = { + .parent = &div4_clks[DIV4_Z], + .ops = &twd_clk_ops, +}; + enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, DIV6_FSIA, DIV6_FSIB, DIV6_SUB, @@ -482,6 +496,7 @@ static struct clk dsi1phy_clk = { static struct clk *late_main_clks[] = { &dsi0phy_clk, &dsi1phy_clk, + &twd_clk, }; enum { MSTP001, @@ -546,6 +561,7 @@ static struct clk mstp_clks[MSTP_NR] = { static struct clk_lookup lookups[] = { /* main clocks */ CLKDEV_CON_ID("r_clk", &r_clk), + CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ /* DIV6 clocks */ CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), From 1f7ccd88717d993c5189280034f1d3b6b5af9693 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:07 -0700 Subject: [PATCH 251/307] ARM: shmobile: sh73a0: remove DIV4_ZT* clocks DIV4_ZT* clocks are for debugging and trace bus clock. It is not necessary to control it from Linux/Software. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index a57ec151674e..26a580324105 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -269,7 +269,7 @@ static struct clk_div4_table div4_table = { }; enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, - DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; + DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR }; #define DIV4(_reg, _bit, _mask, _flags) \ SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) @@ -282,8 +282,6 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), - [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), - [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), }; From b3186c68805911599cbacceae23f60debb5e2210 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:24 -0700 Subject: [PATCH 252/307] ARM: shmobile: sh7372: remove DIV4_ZT* clocks DIV4_ZT* clocks are for debugging and trace bus clock. It is not necessary to control it from Linux/Software. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh7372.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 45d21fe317f4..6c23e3f22d62 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -342,7 +342,7 @@ static struct clk_div4_table div4_table = { }; enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, - DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, + DIV4_ZX, DIV4_HP, DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_DDRP, DIV4_NR }; @@ -355,8 +355,6 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), - [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0), - [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), @@ -516,8 +514,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), - CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]), - CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), From f5942c76217e3f4c2a62a72c9d64997b8765f9e2 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:41 -0700 Subject: [PATCH 253/307] ARM: shmobile: add struct clk_ratio and fixed ratio clock macro Renesas chip has many clocks inside, and some of them are using fixed ratio via parent clock. Current shmobile clock code is using own divX_recalc function and divX_clk_ops. This patch can reduce these code Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock.c | 13 +++++++ arch/arm/mach-shmobile/include/mach/clock.h | 39 +++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm/mach-shmobile/include/mach/clock.h diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index e816ca9bd213..ad7df629d995 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -23,6 +23,19 @@ #include #include #include +#include +#include + +unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) +{ + struct clk_ratio *p = clk->priv; + + return clk->parent->rate / p->div * p->mul; +}; + +struct sh_clk_ops shmobile_fixed_ratio_clk_ops = { + .recalc = shmobile_fixed_ratio_clk_recalc, +}; int __init shmobile_clk_init(void) { diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h new file mode 100644 index 000000000000..76ac61292e48 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/clock.h @@ -0,0 +1,39 @@ +#ifndef CLOCK_H +#define CLOCK_H + +unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk); +extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops; + +/* clock ratio */ +struct clk_ratio { + int mul; + int div; +}; + +#define SH_CLK_RATIO(name, m, d) \ +static struct clk_ratio name ##_ratio = { \ + .mul = m, \ + .div = d, \ +} + +#define SH_FIXED_RATIO_CLKg(name, p, r) \ +struct clk name = { \ + .parent = &p, \ + .ops = &shmobile_fixed_ratio_clk_ops,\ + .priv = &r ## _ratio, \ +} + +#define SH_FIXED_RATIO_CLK(name, p, r) \ +static SH_FIXED_RATIO_CLKg(name, p, r); + +#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ + SH_CLK_RATIO(name, m, d); \ + SH_FIXED_RATIO_CLK(name, p, name); + +#define SH_CLK_SET_RATIO(p, m, d) \ +{ \ + (p)->mul = m; \ + (p)->div = d; \ +} + +#endif From 99fb32b88be4e9b12c44f61b613a0936a62454b7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:54 -0700 Subject: [PATCH 254/307] ARM: shmobile: sh7372: use fixed ratio clock Current clock-sh7372 is using own implement for each divX clocks. This patch switches to use fixed ratio clock, and was tesed on mackerel board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh7372.c | 44 +++++---------------------- 1 file changed, 7 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 6c23e3f22d62..7e105932c09d 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -21,6 +21,7 @@ #include #include #include +#include #include /* SH7372 registers */ @@ -83,39 +84,12 @@ struct clk sh7372_extal2_clk = { .rate = 48000000, }; -/* A fixed divide-by-2 block */ -static unsigned long div2_recalc(struct clk *clk) -{ - return clk->parent->rate / 2; -} +SH_CLK_RATIO(div2, 1, 2); -static struct sh_clk_ops div2_clk_ops = { - .recalc = div2_recalc, -}; - -/* Divide dv_clki by two */ -struct clk sh7372_dv_clki_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh7372_dv_clki_clk, -}; - -/* Divide extal1 by two */ -static struct clk extal1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh7372_extal1_clk, -}; - -/* Divide extal2 by two */ -static struct clk extal2_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh7372_extal2_clk, -}; - -/* Divide extal2 by four */ -static struct clk extal2_div4_clk = { - .ops = &div2_clk_ops, - .parent = &extal2_div2_clk, -}; +SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2); +SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2); /* PLLC0 and PLLC1 */ static unsigned long pllc01_recalc(struct clk *clk) @@ -147,10 +121,7 @@ static struct clk pllc1_clk = { }; /* Divide PLLC1 by two */ -static struct clk pllc1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &pllc1_clk, -}; +SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); /* PLLC2 */ @@ -650,5 +621,4 @@ void __init sh7372_clock_init(void) shmobile_clk_init(); else panic("failed to setup sh7372 clocks\n"); - } From 891cab3e7a71365eb8c79098e487b8f2056a1a73 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:56:14 -0700 Subject: [PATCH 255/307] ARM: shmobile: sh73a0: use fixed ratio clock Current clock-sh73a0 is using own implement for each divX clocks. This patch switches to use fixed ratio clock, and was tesed on kzm9g board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 72 +++++---------------------- 1 file changed, 12 insertions(+), 60 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 26a580324105..784fbaa4cc55 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #define FRQCRA IOMEM(0xe6150000) @@ -83,61 +84,16 @@ struct clk sh73a0_extal2_clk = { .rate = 48000000, }; -/* A fixed divide-by-2 block */ -static unsigned long div2_recalc(struct clk *clk) -{ - return clk->parent->rate / 2; -} - -static struct sh_clk_ops div2_clk_ops = { - .recalc = div2_recalc, -}; - -static unsigned long div7_recalc(struct clk *clk) -{ - return clk->parent->rate / 7; -} - -static struct sh_clk_ops div7_clk_ops = { - .recalc = div7_recalc, -}; - -static unsigned long div13_recalc(struct clk *clk) -{ - return clk->parent->rate / 13; -} - -static struct sh_clk_ops div13_clk_ops = { - .recalc = div13_recalc, -}; - -/* Divide extal1 by two */ -static struct clk extal1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh73a0_extal1_clk, -}; - -/* Divide extal2 by two */ -static struct clk extal2_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh73a0_extal2_clk, -}; - static struct sh_clk_ops main_clk_ops = { .recalc = followparent_recalc, }; /* Main clock */ static struct clk main_clk = { + /* .parent wll be set on sh73a0_clock_init() */ .ops = &main_clk_ops, }; -/* Divide Main clock by two */ -static struct clk main_div2_clk = { - .ops = &div2_clk_ops, - .parent = &main_clk, -}; - /* PLL0, PLL1, PLL2, PLL3 */ static unsigned long pll_recalc(struct clk *clk) { @@ -193,21 +149,17 @@ static struct clk pll3_clk = { .enable_bit = 3, }; -/* Divide PLL */ -static struct clk pll1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &pll1_clk, -}; +/* A fixed divide block */ +SH_CLK_RATIO(div2, 1, 2); +SH_CLK_RATIO(div7, 1, 7); +SH_CLK_RATIO(div13, 1, 13); -static struct clk pll1_div7_clk = { - .ops = &div7_clk_ops, - .parent = &pll1_clk, -}; - -static struct clk pll1_div13_clk = { - .ops = &div13_clk_ops, - .parent = &pll1_clk, -}; +SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2); +SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); +SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); +SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7); +SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13); /* External input clock */ struct clk sh73a0_extcki_clk = { From 5d14ff082badf94c5f5eaf9bc3f53075792c4f44 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:56:40 -0700 Subject: [PATCH 256/307] ARM: shmobile: r8a7740: tidyup comment/implementation mismatch Current clock-r8a7740's DIV4/DIV6/MSTP implemented area and its comment are mismatching. This patch tidyup its comment/implementation area. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 60 +++++++++++++------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 1feb9a2286a8..161e128e2157 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -323,6 +323,7 @@ struct clk *main_clks[] = { &fsibck_clk, }; +/* DIV4 clocks */ static void div4_kick(struct clk *clk) { unsigned long value; @@ -346,6 +347,26 @@ static struct clk_div4_table div4_table = { .kick = div4_kick, }; +enum { + DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, + DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, + DIV4_NR +}; + +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), + [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), + [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), + [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), + [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), + [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), + [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), +}; + /* DIV6 reparent */ enum { DIV6_HDMI, @@ -391,6 +412,16 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), }; +/* DIV6 clocks */ +enum { + DIV6_SUB, + DIV6_NR +}; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), +}; + /* HDMI1/2 clock */ static unsigned long hdmi12_recalc(struct clk *clk) { @@ -455,35 +486,6 @@ static struct clk fsidivs[] = { }; /* MSTP */ -enum { - DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, - DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, - DIV4_NR -}; - -struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), - [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), - [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), - [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), - [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), - [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), - [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), -}; - -enum { - DIV6_SUB, - DIV6_NR -}; - -static struct clk div6_clks[DIV6_NR] = { - [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), -}; - enum { MSTP128, MSTP127, MSTP125, MSTP116, MSTP111, MSTP100, MSTP117, From 10d6db2ba2a68fd7d5639ce4f422ec9dff2af0e7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:56:57 -0700 Subject: [PATCH 257/307] ARM: shmobile: r8a7740: use fixed ratio clock Current clock-r8a7740 is using own implement for each divX clocks. This patch switches to use fixed ratio clock, and was tesed on armadillo board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 54 +++++--------------------- 1 file changed, 9 insertions(+), 45 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 161e128e2157..c0d39aa6de50 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -97,42 +98,13 @@ static struct clk dv_clk = { .rate = 27000000, }; -static unsigned long div_recalc(struct clk *clk) -{ - return clk->parent->rate / (int)(clk->priv); -} +SH_CLK_RATIO(div2, 1, 2); +SH_CLK_RATIO(div1k, 1, 1024); -static struct sh_clk_ops div_clk_ops = { - .recalc = div_recalc, -}; - -/* extal1 / 2 */ -static struct clk extal1_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &extal1_clk, -}; - -/* extal1 / 1024 */ -static struct clk extal1_div1024_clk = { - .ops = &div_clk_ops, - .priv = (void *)1024, - .parent = &extal1_clk, -}; - -/* extal1 / 2 / 1024 */ -static struct clk extal1_div2048_clk = { - .ops = &div_clk_ops, - .priv = (void *)1024, - .parent = &extal1_div2_clk, -}; - -/* extal2 / 2 */ -static struct clk extal2_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &extal2_clk, -}; +SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k); +SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k); +SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); static struct sh_clk_ops followparent_clk_ops = { .recalc = followparent_recalc, @@ -143,11 +115,7 @@ static struct clk system_clk = { .ops = &followparent_clk_ops, }; -static struct clk system_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &system_clk, -}; +SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2); /* r_clk */ static struct clk r_clk = { @@ -184,11 +152,7 @@ static struct clk pllc1_clk = { }; /* PLLC1 / 2 */ -static struct clk pllc1_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &pllc1_clk, -}; +SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); /* USB clock */ /* From ec0728d67985690f329592e68f0f1fe1f2388e70 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:57:38 -0700 Subject: [PATCH 258/307] ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock R-Car H1 has many clocks, and it is possible to read/use clock ratio of these clocks from FRQMRx as DIV4 clocks. But, these ratio are fixed value and these are decided by MD pin status. This means that we can use fixed ratio clock via MD pin status, instead of DIV4 clocks. This patch reads MD pin status, and sets PLLA clock (= root clock), and used fixed ratio clock for other clocks. It was tesed on marzen board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7779.c | 196 ++++++++++++++----------- 1 file changed, 109 insertions(+), 87 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index d9edeaf66007..7d86bfbb5b06 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -17,13 +17,17 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include #include #include #include #include #include +#include #include +#define MD(nr) BIT(nr) + #define FRQMR IOMEM(0xffc80014) #define MSTPCR0 IOMEM(0xffc80030) #define MSTPCR1 IOMEM(0xffc80034) @@ -36,6 +40,9 @@ #define MSTPCR6 IOMEM(0xffc80058) #define MSTPCR7 IOMEM(0xffc80040) +#define MODEMR 0xffcc0020 + + /* ioremap() through clock mapping mandatory to avoid * collision with ARM coherent DMA virtual memory range. */ @@ -50,40 +57,39 @@ static struct clk_mapping cpg_mapping = { * from the platform code. */ static struct clk plla_clk = { - .rate = 1500000000, + /* .rate will be updated on r8a7779_clock_init() */ .mapping = &cpg_mapping, }; +/* + * clock ratio of these clock will be updated + * on r8a7779_clock_init() + */ +SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1); + static struct clk *main_clks[] = { &plla_clk, -}; - -static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; - -static struct clk_div_mult_table div4_div_mult_table = { - .divisors = divisors, - .nr_divisors = ARRAY_SIZE(divisors), -}; - -static struct clk_div4_table div4_table = { - .div_mult_table = &div4_div_mult_table, -}; - -enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR }; - -static struct clk div4_clks[DIV4_NR] = { - [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20, - 0x0018, CLK_ENABLE_ON_INIT), - [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16, - 0x0700, CLK_ENABLE_ON_INIT), - [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12, - 0x0040, CLK_ENABLE_ON_INIT), - [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8, - 0x0010, CLK_ENABLE_ON_INIT), - [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4, - 0x0060, CLK_ENABLE_ON_INIT), - [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0, - 0x0300, CLK_ENABLE_ON_INIT), + &clkz_clk, + &clkzs_clk, + &clki_clk, + &clks_clk, + &clks1_clk, + &clks3_clk, + &clks4_clk, + &clkb_clk, + &clkout_clk, + &clkp_clk, + &clkg_clk, }; enum { MSTP323, MSTP322, MSTP321, MSTP320, @@ -96,52 +102,28 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ - [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ - [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ - [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ - [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ - [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ - [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ - [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ - [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ - [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */ - [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */ - [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */ - [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ - [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ - [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ - [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ - [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ - [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ - [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ - [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ - [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ - [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */ -}; - -static unsigned long mul4_recalc(struct clk *clk) -{ - return clk->parent->rate * 4; -} - -static struct sh_clk_ops mul4_clk_ops = { - .recalc = mul4_recalc, -}; - -struct clk clkz_clk = { - .ops = &mul4_clk_ops, - .parent = &div4_clks[DIV4_S], -}; - -struct clk clkzs_clk = { - /* clks x 4 / 4 = clks */ - .parent = &div4_clks[DIV4_S], -}; - -static struct clk *late_main_clks[] = { - &clkz_clk, - &clkzs_clk, + [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */ + [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ + [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ + [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */ + [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */ + [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */ + [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */ + [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */ + [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */ + [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */ + [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */ + [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */ + [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */ }; static struct clk_lookup lookups[] = { @@ -151,12 +133,12 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), /* DIV4 clocks */ - CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), - CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), - CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), - CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), - CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), - CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("shyway_clk", &clks_clk), + CLKDEV_CON_ID("bus_clk", &clkout_clk), + CLKDEV_CON_ID("shyway4_clk", &clks4_clk), + CLKDEV_CON_ID("shyway3_clk", &clks3_clk), + CLKDEV_CON_ID("shyway1_clk", &clks1_clk), + CLKDEV_CON_ID("peripheral_clk", &clkp_clk), /* MSTP32 clocks */ CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ @@ -190,20 +172,60 @@ static struct clk_lookup lookups[] = { void __init r8a7779_clock_init(void) { + void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); + u32 mode; int k, ret = 0; + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + if (mode & MD(1)) { + plla_clk.rate = 1500000000; + + SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3); + SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6); + SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); + SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6); + SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24); + SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36); + } else { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); + } + } else { + plla_clk.rate = 1600000000; + + SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2); + SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); + SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32); + SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32); + } else { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); + } + } + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); - if (!ret) - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); - if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) - ret = clk_register(late_main_clks[k]); - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) From daf9aa98293528abcf24b015ae8aa6e075d37298 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:48:19 -0700 Subject: [PATCH 259/307] ARM: shmobile: sh7372: move global functions to sh7372.h There is no reason each CPU's own function has to exist in common.h. sh7372_xxx() go to sh7372.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 15 --------------- arch/arm/mach-shmobile/include/mach/sh7372.h | 12 ++++++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 03f73def2fc6..d01a5511a5ac 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,21 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void sh7372_init_irq(void); -extern void sh7372_map_io(void); -extern void sh7372_earlytimer_init(void); -extern void sh7372_add_early_devices(void); -extern void sh7372_add_standard_devices(void); -extern void sh7372_add_early_devices_dt(void); -extern void sh7372_add_standard_devices_dt(void); -extern void sh7372_clock_init(void); -extern void sh7372_pinmux_init(void); -extern void sh7372_pm_init(void); -extern void sh7372_resume_core_standby_sysc(void); -extern int sh7372_do_idle_sysc(unsigned long sleep_mode); -extern struct clk sh7372_extal1_clk; -extern struct clk sh7372_extal2_clk; - extern void sh73a0_init_delay(void); extern void sh73a0_init_irq(void); extern void sh73a0_init_irq_dt(void); diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index b582facc1cf6..f0ea60d6648a 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -478,6 +478,18 @@ extern struct clk sh7372_dv_clki_clk; extern struct clk sh7372_dv_clki_div2_clk; extern struct clk sh7372_pllc2_clk; +extern void sh7372_init_irq(void); +extern void sh7372_map_io(void); +extern void sh7372_earlytimer_init(void); +extern void sh7372_add_early_devices(void); +extern void sh7372_add_standard_devices(void); +extern void sh7372_add_early_devices_dt(void); +extern void sh7372_add_standard_devices_dt(void); +extern void sh7372_clock_init(void); +extern void sh7372_pinmux_init(void); +extern void sh7372_pm_init(void); +extern void sh7372_resume_core_standby_sysc(void); +extern int sh7372_do_idle_sysc(unsigned long sleep_mode); extern void sh7372_intcs_suspend(void); extern void sh7372_intcs_resume(void); extern void sh7372_intca_suspend(void); From 014f93a08361282a0af0dd155c3b434431ea36df Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:48:30 -0700 Subject: [PATCH 260/307] ARM: shmobile: sh73a0: move global functions to sh73a0.h There is no reason each CPU's own function has to exist in common.h. sh73a0_xxx() go to sh73a0.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 16 ---------------- arch/arm/mach-shmobile/include/mach/sh73a0.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d01a5511a5ac..48eeca9d25a3 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,22 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void sh73a0_init_delay(void); -extern void sh73a0_init_irq(void); -extern void sh73a0_init_irq_dt(void); -extern void sh73a0_map_io(void); -extern void sh73a0_earlytimer_init(void); -extern void sh73a0_add_early_devices(void); -extern void sh73a0_add_standard_devices(void); -extern void sh73a0_add_standard_devices_dt(void); -extern void sh73a0_clock_init(void); -extern void sh73a0_pinmux_init(void); -extern void sh73a0_pm_init(void); -extern struct clk sh73a0_extal1_clk; -extern struct clk sh73a0_extal2_clk; -extern struct clk sh73a0_extcki_clk; -extern struct clk sh73a0_extalr_clk; - extern void r8a7740_meram_workaround(void); extern void r8a7740_init_irq(void); extern void r8a7740_map_io(void); diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 606d31d02a4e..936da1b4a9c5 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -557,6 +557,21 @@ enum { #define SH73A0_PINT0_IRQ(irq) ((irq) + 700) #define SH73A0_PINT1_IRQ(irq) ((irq) + 732) +extern void sh73a0_init_delay(void); +extern void sh73a0_init_irq(void); +extern void sh73a0_init_irq_dt(void); +extern void sh73a0_map_io(void); +extern void sh73a0_earlytimer_init(void); +extern void sh73a0_add_early_devices(void); +extern void sh73a0_add_standard_devices(void); +extern void sh73a0_add_standard_devices_dt(void); +extern void sh73a0_clock_init(void); +extern void sh73a0_pinmux_init(void); +extern void sh73a0_pm_init(void); +extern struct clk sh73a0_extal1_clk; +extern struct clk sh73a0_extal2_clk; +extern struct clk sh73a0_extcki_clk; +extern struct clk sh73a0_extalr_clk; extern struct smp_operations sh73a0_smp_ops; #endif /* __ASM_SH73A0_H__ */ From f96c764dac2c2761fc05164255c0ed689b8ac496 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:49:15 -0700 Subject: [PATCH 261/307] ARM: shmobile: r8a7740: move global functions to r8a7740.h There is no reason each CPU's own function has to exist in common.h. r8a7740_xxx() go to r8a7740.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 9 --------- arch/arm/mach-shmobile/include/mach/r8a7740.h | 9 +++++++++ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 48eeca9d25a3..4d5410de00d6 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,15 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void r8a7740_meram_workaround(void); -extern void r8a7740_init_irq(void); -extern void r8a7740_map_io(void); -extern void r8a7740_add_early_devices(void); -extern void r8a7740_add_standard_devices(void); -extern void r8a7740_clock_init(u8 md_ck); -extern void r8a7740_pinmux_init(void); -extern void r8a7740_pm_init(void); - extern void r8a7779_init_delay(void); extern void r8a7779_init_irq(void); extern void r8a7779_init_irq_extpin(int irlm); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index 59d252f4cf97..5a879bbe145f 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -606,6 +606,15 @@ enum { SHDMA_SLAVE_USBHS_RX, }; +extern void r8a7740_meram_workaround(void); +extern void r8a7740_init_irq(void); +extern void r8a7740_map_io(void); +extern void r8a7740_add_early_devices(void); +extern void r8a7740_add_standard_devices(void); +extern void r8a7740_clock_init(u8 md_ck); +extern void r8a7740_pinmux_init(void); +extern void r8a7740_pm_init(void); + #ifdef CONFIG_PM extern void __init r8a7740_init_pm_domains(void); #else From 60e3a566897dcdd8621464ff46f4537903c2255a Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:49:27 -0700 Subject: [PATCH 262/307] ARM: shmobile: r8a7779: move global functions to r8a7779.h There is no reason each CPU's own function has to exist in common.h. r8a7779_xxx() go to r8a7779.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 14 -------------- arch/arm/mach-shmobile/include/mach/r8a7779.h | 13 +++++++++++++ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 4d5410de00d6..e002cfd9d2df 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,20 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void r8a7779_init_delay(void); -extern void r8a7779_init_irq(void); -extern void r8a7779_init_irq_extpin(int irlm); -extern void r8a7779_init_irq_dt(void); -extern void r8a7779_map_io(void); -extern void r8a7779_earlytimer_init(void); -extern void r8a7779_add_early_devices(void); -extern void r8a7779_add_standard_devices(void); -extern void r8a7779_add_standard_devices_dt(void); -extern void r8a7779_clock_init(void); -extern void r8a7779_pinmux_init(void); -extern void r8a7779_pm_init(void); -extern void r8a7779_register_twd(void); - #ifdef CONFIG_SUSPEND int shmobile_suspend_init(void); #else diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 8ab0cd6ad6b0..af38750f38f7 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -343,6 +343,19 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; } +extern void r8a7779_init_delay(void); +extern void r8a7779_init_irq(void); +extern void r8a7779_init_irq_extpin(int irlm); +extern void r8a7779_init_irq_dt(void); +extern void r8a7779_map_io(void); +extern void r8a7779_earlytimer_init(void); +extern void r8a7779_add_early_devices(void); +extern void r8a7779_add_standard_devices(void); +extern void r8a7779_add_standard_devices_dt(void); +extern void r8a7779_clock_init(void); +extern void r8a7779_pinmux_init(void); +extern void r8a7779_pm_init(void); +extern void r8a7779_register_twd(void); extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); From 0468b2d6b6ae71699c22e67701e23d6ca8ff3046 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:49:34 +0900 Subject: [PATCH 263/307] ARM: shmobile: Initial r8a7790 SoC support Add initial support for the r8a7790 SoC including: - Single Cortex-A15 CPU Core - GIC - Architecture timer No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 54 ++++++++++++++++ arch/arm/mach-shmobile/Kconfig | 7 +++ arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/clock-r8a7790.c | 61 +++++++++++++++++++ arch/arm/mach-shmobile/include/mach/r8a7790.h | 7 +++ arch/arm/mach-shmobile/setup-r8a7790.c | 51 ++++++++++++++++ 6 files changed, 181 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7790.dtsi create mode 100644 arch/arm/mach-shmobile/clock-r8a7790.c create mode 100644 arch/arm/mach-shmobile/include/mach/r8a7790.h create mode 100644 arch/arm/mach-shmobile/setup-r8a7790.c diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi new file mode 100644 index 000000000000..1c58ffb6cccf --- /dev/null +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -0,0 +1,54 @@ +/* + * Device Tree Source for the r8a7790 SoC + * + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a7790"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1300000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xf1001000 0x1000>, + <0xf1002000 0x1000>, + <0xf1004000 0x2000>, + <0xf1006000 0x2000>; + interrupts = <1 9 0xf04>; + + gic-cpuif@4 { + compatible = "arm,gic-cpuif"; + cpuif-id = <4>; + cpu = <&cpu0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index d569c34b1c86..749dfb4c63c0 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -51,6 +51,13 @@ config ARCH_R8A7779 select USB_ARCH_HAS_OHCI select RENESAS_INTC_IRQPIN +config ARCH_R8A7790 + bool "R-Car H2 (R8A77900)" + select ARM_GIC + select CPU_V7 + select ARM_ARCH_TIMER + select SH_CLK_CPG + config ARCH_EMEV2 bool "Emma Mobile EV2" select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 2d42de46db8d..709b9b421f93 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o +obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o # SMP objects diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c new file mode 100644 index 000000000000..6869798effa3 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -0,0 +1,61 @@ +/* + * r8a7790 clock framework support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include + +#define CPG_BASE 0xe6150000 +#define CPG_LEN 0x1000 + +static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, + .len = CPG_LEN, +}; + +static struct clk *main_clks[] = { +}; + +enum { MSTP_NR }; +static struct clk mstp_clks[MSTP_NR] = { +}; + +static struct clk_lookup lookups[] = { +}; + +void __init r8a7790_clock_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + shmobile_clk_init(); + else + panic("failed to setup r8a7790 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h new file mode 100644 index 000000000000..f38ded61285f --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -0,0 +1,7 @@ +#ifndef __ASM_R8A7790_H__ +#define __ASM_R8A7790_H__ + +void r8a7790_add_standard_devices(void); +void r8a7790_clock_init(void); + +#endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c new file mode 100644 index 000000000000..af432ba11020 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -0,0 +1,51 @@ +/* + * r8a7790 processor support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void __init r8a7790_add_standard_devices(void) +{ +} + +#ifdef CONFIG_USE_OF +void __init r8a7790_add_standard_devices_dt(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *r8a7790_boards_compat_dt[] __initdata = { + "renesas,r8a7790", + NULL, +}; + +DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") + .init_irq = irqchip_init, + .init_machine = r8a7790_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7790_boards_compat_dt, +MACHINE_END +#endif /* CONFIG_USE_OF */ From 55d9fab280e6e587d634d2ec2effe94eabe90e9c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:49:44 +0900 Subject: [PATCH 264/307] ARM: shmobile: r8a7790 SCIF support Add SCIF serial port support to the r8a7790 SoC by adding platform devices for SCIFA0 -> SCIFA2 as well as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF1 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7790.c | 36 ++++++++++++++++- arch/arm/mach-shmobile/setup-r8a7790.c | 55 ++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 6869798effa3..bad9bf2e34d6 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -27,19 +27,51 @@ #define CPG_BASE 0xe6150000 #define CPG_LEN 0x1000 +#define SMSTPCR2 0xe6150138 +#define SMSTPCR7 0xe615014c + static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, .len = CPG_LEN, }; -static struct clk *main_clks[] = { +static struct clk p_clk = { + .rate = 65000000, /* shortcut for now */ + .mapping = &cpg_mapping, }; -enum { MSTP_NR }; +static struct clk mp_clk = { + .rate = 52000000, /* shortcut for now */ + .mapping = &cpg_mapping, +}; + +static struct clk *main_clks[] = { + &p_clk, + &mp_clk, +}; + +enum { MSTP721, MSTP720, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ + [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ + [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ }; static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), }; void __init r8a7790_clock_init(void) diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index af432ba11020..3bb5bf16000c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -22,13 +22,68 @@ #include #include #include +#include #include #include #include #include +#define SCIF_COMMON(scif_type, baseaddr, irq) \ + .type = scif_type, \ + .mapbase = baseaddr, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .irqs = SCIx_IRQ_MUXED(irq) + +#define SCIFA_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ + .scbrr_algo_id = SCBRR_ALGO_4, \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ +} + +#define SCIFB_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ + .scbrr_algo_id = SCBRR_ALGO_4, \ + .scscr = SCSCR_RE | SCSCR_TE, \ +} + +#define SCIF_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ + .scbrr_algo_id = SCBRR_ALGO_2, \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ +} + +enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 }; + +static const struct plat_sci_port scif[] = { + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ + SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ + SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ + SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ + SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ + SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ + SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ + SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ +}; + +static inline void r8a7790_register_scif(int idx) +{ + platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], + sizeof(struct plat_sci_port)); +} + void __init r8a7790_add_standard_devices(void) { + r8a7790_register_scif(SCIFA0); + r8a7790_register_scif(SCIFA1); + r8a7790_register_scif(SCIFB0); + r8a7790_register_scif(SCIFB1); + r8a7790_register_scif(SCIFB2); + r8a7790_register_scif(SCIFA2); + r8a7790_register_scif(SCIF0); + r8a7790_register_scif(SCIF1); } #ifdef CONFIG_USE_OF From 8f5ec0a57ef503e7609d763cadba55f12b9486ce Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:49:54 +0900 Subject: [PATCH 265/307] ARM: shmobile: r8a7790 IRQC support Add IRQC interrupt controller support to r8a7790 by hooking up a single IRQC instances to handle 4 external IRQ signals. The IRQC controller is tied to SPIs of the GIC. On r8a7790 the external IRQ pins routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 9 +++++++++ arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 1c58ffb6cccf..a1e0e0c64c3c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -51,4 +51,13 @@ timer { <1 11 0xf08>, <1 10 0xf08>; }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; + }; }; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 749dfb4c63c0..ccaea6aecea0 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -57,6 +57,7 @@ config ARCH_R8A7790 select CPU_V7 select ARM_ARCH_TIMER select SH_CLK_CPG + select RENESAS_IRQC config ARCH_EMEV2 bool "Emma Mobile EV2" diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 3bb5bf16000c..9b4ccd7b5031 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -74,6 +75,25 @@ static inline void r8a7790_register_scif(int idx) sizeof(struct plat_sci_port)); } +static struct renesas_irqc_config irqc0_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ +}; + +static struct resource irqc0_resources[] = { + DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ + DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ +}; + +#define r8a7790_register_irqc(idx) \ + platform_device_register_resndata(&platform_bus, "renesas_irqc", \ + idx, irqc##idx##_resources, \ + ARRAY_SIZE(irqc##idx##_resources), \ + &irqc##idx##_data, \ + sizeof(struct renesas_irqc_config)) + void __init r8a7790_add_standard_devices(void) { r8a7790_register_scif(SCIFA0); @@ -84,6 +104,7 @@ void __init r8a7790_add_standard_devices(void) r8a7790_register_scif(SCIFA2); r8a7790_register_scif(SCIF0); r8a7790_register_scif(SCIF1); + r8a7790_register_irqc(0); } #ifdef CONFIG_USE_OF From 69e351d029985a31abd41b2b8729788a01e8588d Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:50:03 +0900 Subject: [PATCH 266/307] ARM: shmobile: r8a7790 PFC support Add a platform device for the r8a7790 PFC. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/include/mach/r8a7790.h | 1 + arch/arm/mach-shmobile/setup-r8a7790.c | 10 ++++++++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index ccaea6aecea0..ff674c5f2d03 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -53,6 +53,7 @@ config ARCH_R8A7779 config ARCH_R8A7790 bool "R-Car H2 (R8A77900)" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 select ARM_ARCH_TIMER diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h index f38ded61285f..9bd6f5c894bb 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -3,5 +3,6 @@ void r8a7790_add_standard_devices(void); void r8a7790_clock_init(void); +void r8a7790_pinmux_init(void); #endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 9b4ccd7b5031..481201a4f3f5 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -29,6 +29,16 @@ #include #include +static const struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xe6060000, 0x250), +}; + +void __init r8a7790_pinmux_init(void) +{ + platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, + ARRAY_SIZE(pfc_resources)); +} + #define SCIF_COMMON(scif_type, baseaddr, irq) \ .type = scif_type, \ .mapbase = baseaddr, \ From 26a0d2d47f5bfb75cd14d961f9d825338d471317 Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Fri, 29 Mar 2013 16:45:56 +0900 Subject: [PATCH 267/307] ARM: shmobile: r8a73a4 SoC 64-bit DT support The r8a73a4 SoC supports LPAE and has memory window up to 0x2ffffffff. Convert to 64-bit addresses by enlarging #addr-cells and #size-cells to 2. Signed-off-by: Takashi Yoshii Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 7db5b504e64c..fde2a337d1ff 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -9,11 +9,11 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - / { compatible = "renesas,r8a73a4"; interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; cpus { #address-cells = <1>; @@ -32,10 +32,10 @@ gic: interrupt-controller@f1001000 { #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0xf1001000 0x1000>, - <0xf1002000 0x1000>, - <0xf1004000 0x2000>, - <0xf1006000 0x2000>; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; gic-cpuif@4 { @@ -57,7 +57,7 @@ irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; - reg = <0xe61c0000 0x200>; + reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, @@ -73,7 +73,7 @@ irqc1: interrupt-controller@e61c0200 { compatible = "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; - reg = <0xe61c0200 0x200>; + reg = <0 0xe61c0200 0 0x200>; interrupt-parent = <&gic>; interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, @@ -86,8 +86,8 @@ irqc1: interrupt-controller@e61c0200 { thermal@e61f0000 { compatible = "renesas,rcar-thermal"; - reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>, - <0xe61f0200 0x38>, <0xe61f0300 0x38>; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, + <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupt-parent = <&gic>; interrupts = <0 69 4>; }; From 8585deb18580d04209a2986430aa0959ef38fce2 Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Fri, 29 Mar 2013 16:49:17 +0900 Subject: [PATCH 268/307] ARM: shmobile: r8a7790 SoC 64-bit DT support The r8a7790 SoC supports LPAE and has memory window up to 0x2ffffffff. Convert to 64-bit addresses by enlarging #addr-cells and #size-cells to 2. Signed-off-by: Takashi Yoshii Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index a1e0e0c64c3c..7a1711027e41 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -8,11 +8,11 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - / { compatible = "renesas,r8a7790"; interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; cpus { #address-cells = <1>; @@ -31,10 +31,10 @@ gic: interrupt-controller@f1001000 { #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0xf1001000 0x1000>, - <0xf1002000 0x1000>, - <0xf1004000 0x2000>, - <0xf1006000 0x2000>; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; gic-cpuif@4 { @@ -56,7 +56,7 @@ irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; - reg = <0xe61c0000 0x200>; + reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; }; From 1960d58003b735555bb2dc56699530d606698574 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 26 Mar 2013 01:44:52 +0100 Subject: [PATCH 269/307] sh-pfc: Fix compiler warning when BUG() The sh_pfc_phys_to_virt() function ends with a BUG() statement without a return. When CONFIG_BUG isn't set the function will thus have no return value. Fix it. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index feef89792568..97e6ea3147e0 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -72,6 +72,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, } BUG(); + return NULL; } int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) From 6299e571b2d90dffcee7b58a9252f3ef29241922 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 26 Mar 2013 02:07:51 +0100 Subject: [PATCH 270/307] sh: sh7269: Fix compilation by adding missing includes struct resource is defined in linux/ioport.h. Include it. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c index 1825b0bd523d..4c17fb6970b1 100644 --- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c @@ -9,7 +9,9 @@ * for more details. */ +#include #include +#include #include #include From c09b51d5de108acbf9ae176cc81325afd79648dd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 14:33:32 +0100 Subject: [PATCH 271/307] sh-pfc: r8a7779: Remove function GPIOs All r8a7779 platforms use the pinctrl API to control functions. Function GPIOs are unused and unneeded, remove them. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 271 --------------------------- 1 file changed, 271 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 1d7b0dfbbb21..4db99445acc2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2670,274 +2670,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb2), }; -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) - -static const struct pinmux_func pinmux_func_gpios[] = { - GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), - GPIO_FN(A19), - - /* IPSR0 */ - GPIO_FN(PWM1), GPIO_FN(PWMFSW0), - GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), - GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), - GPIO_FN(HCTS1), GPIO_FN(A0), - GPIO_FN(FD3), GPIO_FN(A20), - GPIO_FN(A21), - GPIO_FN(A22), - GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), - GPIO_FN(VI1_R1), GPIO_FN(A24), - GPIO_FN(FD4), GPIO_FN(VI1_R2), - GPIO_FN(SSI_WS78_B), GPIO_FN(A25), - GPIO_FN(FD5), GPIO_FN(VI1_R3), - GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT), - GPIO_FN(PWM0_B), - GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), - GPIO_FN(VI1_R7), GPIO_FN(HRTS1), - - /* IPSR1 */ - GPIO_FN(FD6), GPIO_FN(FD7), - GPIO_FN(FALE), - GPIO_FN(ATACS00), - GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), - GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), - GPIO_FN(SSI_SDATA9), - GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), - GPIO_FN(HTX1), - GPIO_FN(SSI_SCK9), - GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), - GPIO_FN(HRX1), GPIO_FN(SSI_WS9), - GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG), - GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), - GPIO_FN(HTX0), GPIO_FN(SDATA), - GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2), - GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26), - GPIO_FN(CC5_STATE34), - - /* IPSR2 */ - GPIO_FN(HRX0), GPIO_FN(SCKZ), - GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11), - GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35), - GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5), - GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), - GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16), - GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0), - GPIO_FN(STM), GPIO_FN(PWM0_D), - GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B), - GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), - GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), - GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), - GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0), - GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), - GPIO_FN(LCDOUT1), GPIO_FN(DACK0), - GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), - GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3), - GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5), - GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7), - GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), - GPIO_FN(AUDATA2), - - /* IPSR3 */ - GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), - GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10), - GPIO_FN(LCDOUT11), - GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13), - GPIO_FN(LCDOUT14), - GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16), - GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), - GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), - GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), - GPIO_FN(LCDOUT18), - GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20), - GPIO_FN(LCDOUT21), - GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23), - GPIO_FN(QSTVA_QVS), - GPIO_FN(SCL3_B), GPIO_FN(QCLK), - GPIO_FN(QSTVB_QVE), - GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B), - GPIO_FN(QSTH_QHS), - GPIO_FN(QSTB_QHE), - GPIO_FN(QCPV_QDE), - GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), - - /* IPSR4 */ - GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), - GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), - GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), - GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), - GPIO_FN(AUDCK), - GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1), - GPIO_FN(PWM0), - GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0), - GPIO_FN(VI2_G1), GPIO_FN(VI2_G2), - GPIO_FN(VI2_G3), GPIO_FN(VI2_G4), - GPIO_FN(VI2_G5), - GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), - GPIO_FN(AUDATA6), - GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), - GPIO_FN(AUDATA7), - GPIO_FN(VI2_G6), GPIO_FN(VI2_G7), - GPIO_FN(VI2_R0), GPIO_FN(VI2_R1), - GPIO_FN(VI2_R2), GPIO_FN(VI2_R3), - GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), - - /* IPSR5 */ - GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), - GPIO_FN(VI2_R4), GPIO_FN(VI2_R5), - GPIO_FN(VI2_R6), GPIO_FN(VI2_R7), - GPIO_FN(SCL2_D), GPIO_FN(SDA2_D), - GPIO_FN(VI2_CLKENB), - GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD), - GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC), - GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC), - GPIO_FN(VI3_VSYNC), - GPIO_FN(VI2_CLK), - GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), - GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN), - GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6), - GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), - GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), - GPIO_FN(VI2_DATA7_VI2_B7), - GPIO_FN(VI1_FIELD), - GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), - GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), - GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), - GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0), - - /* IPSR6 */ - GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1), - GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2), - GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5), - GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6), - GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34), - GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX), - GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7), - GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C), - GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8), - GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B), - GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9), - GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK), - GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D), - GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11), - GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA), - GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), - GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B), - - /* IPSR7 */ - GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), - GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), - GPIO_FN(SSI_SCK9_B), - GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), - GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7), - GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C), - GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), - GPIO_FN(ATACS01), GPIO_FN(ATACS11), - GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1), - GPIO_FN(CC5_TRST), GPIO_FN(ATAG1), - GPIO_FN(CC5_TMS), GPIO_FN(ATARD1), - GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1), - GPIO_FN(CC5_TDI), GPIO_FN(DREQ2), - GPIO_FN(DACK2), - - /* IPSR8 */ - GPIO_FN(AD_CLK), - GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), - GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), - GPIO_FN(AD_DI), - GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), - GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), - GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), - GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), - GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), - GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), - GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), - GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), - GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA), - GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB), - GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), - GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B), - GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), - GPIO_FN(HSCK1_B), - GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B), - GPIO_FN(PWMFSW0_C), - - /* IPSR9 */ - GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), - GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM), - GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3), - GPIO_FN(VI0_DATA4_VI0_B4), - GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6), - GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), - GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), - GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2), - GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), - GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1), - GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), - GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), - GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4), - GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6), - GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), - GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0), - GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7), - GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9), - - /* IPSR10 */ - GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), - GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), - GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), - GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), - GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), - GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), - GPIO_FN(ARM_TRACEDATA_13), - GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), - GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), - GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), - GPIO_FN(ARM_TRACEDATA_15), - GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC), - GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK), - GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7), - GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), - GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN), - GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC), - GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C), - GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C), - GPIO_FN(SPV_TRST), GPIO_FN(SCL3), - - /* IPSR11 */ - GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST), - GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1), - GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), - GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), - GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B), - GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN), - GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4), - GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), - GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), - GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), - GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), - GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), - GPIO_FN(VI1_DATA7_VI1_B7), - GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), - GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), - GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO), - GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), - GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), - GPIO_FN(HRTS0_B), - - /* IPSR12 */ - GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1), - GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), - GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1), - GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4), - GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B), - GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5), - GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B), - GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB), - GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), - GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), -}; - static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { GP_0_31_FN, FN_IP3_31_29, @@ -3831,9 +3563,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, From 7417dae5214a19885220597562ea16f238d2c6fc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 23:47:18 +0100 Subject: [PATCH 272/307] sh-pfc: r8a7779: Don't use GPIO enum entries Refactor the GPIO macro magic to use GPIO numbers directly instead of the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum entries from the mach/r8a7779.h header. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 94 ++++++++++++++++++++-------- 1 file changed, 69 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 4db99445acc2..41d8bda45163 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -19,39 +19,83 @@ */ #include -#include #include "sh_pfc.h" -#define CPU_32_PORT6(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ - PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ - PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ - PORT_1(fn, pfx##8, sfx) +#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) -#define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_32(fn, pfx##_0_, sfx), \ - PORT_32(fn, pfx##_1_, sfx), \ - PORT_32(fn, pfx##_2_, sfx), \ - PORT_32(fn, pfx##_3_, sfx), \ - PORT_32(fn, pfx##_4_, sfx), \ - PORT_32(fn, pfx##_5_, sfx), \ - CPU_32_PORT6(fn, pfx##_6_, sfx) +#define PORT_GP_32(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ + PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) +#define PORT_GP_32_9(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx) -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA +#define PORT_GP_32_REV(bank, fn, sfx) \ + PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ + PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ + PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ + PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ + PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ + PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ + PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ + PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ + PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ + PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ + PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ + PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ + PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ + PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ + PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ + PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx), \ + PORT_GP_32_9(6, fn, sfx) -#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused) +#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx + +#define _GP_GPIO(bank, pin, _name, sfx) \ + [(bank * 32) + pin] = { \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } + +#define _GP_DATA(bank, pin, name, sfx) \ + PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT) + +#define _GP_INOUTSEL(bank, pin, name, sfx) name##_IN, name##_OUT +#define _GP_INDT(bank, pin, name, sfx) name##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) + +#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused) +#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused) #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ From 87bd63bfcf177daa272432482c17195f3c0ebb21 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 14:44:27 +0100 Subject: [PATCH 273/307] ARM: shmobile: r8a7779: Remove all GPIOs Function GPIOs are not used anymore, and all code use the GPIO numbers directly. Remove the GPIOs enumeration. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 317 ------------------ 1 file changed, 317 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 68c3b2dfb018..945299ed1638 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -4,323 +4,6 @@ #include #include -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, - GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, - GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, - GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, - GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, - GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, - GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, - GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, - GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, - GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, - GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, - GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, - GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, - GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, - GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, - - GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18, - GPIO_FN_A19, - - /* IPSR0 */ - GPIO_FN_PWM1, GPIO_FN_PWMFSW0, - GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, - GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, - GPIO_FN_HCTS1, GPIO_FN_A0, - GPIO_FN_FD3, GPIO_FN_A20, - GPIO_FN_A21, - GPIO_FN_A22, GPIO_FN_VI1_R0, - GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1, - GPIO_FN_A24, GPIO_FN_FD4, - GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, - GPIO_FN_FD5, - GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B, - GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, - GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0, - GPIO_FN_VI1_R7, GPIO_FN_HRTS1, - - /* IPSR1 */ - GPIO_FN_FD6, GPIO_FN_FD7, - GPIO_FN_FALE, - GPIO_FN_ATACS00, - GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, - GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, - GPIO_FN_SSI_SDATA9, - GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, - GPIO_FN_HTX1, GPIO_FN_SSI_SCK9, - GPIO_FN_FD1, - GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, - GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2, - GPIO_FN_MLB_SIG, GPIO_FN_PWM3, - GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0, - GPIO_FN_SDATA, GPIO_FN_SUB_TCK, - GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18, - GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34, - - /* IPSR2 */ - GPIO_FN_HRX0, GPIO_FN_SCKZ, - GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11, - GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35, - GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5, - GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO, - GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16, - GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, - GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C, - GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0, - GPIO_FN_MDATA, GPIO_FN_SUB_TMS, - GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17, - GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, - GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0, - GPIO_FN_LCDOUT1, GPIO_FN_DACK0, - GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, - GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3, - GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5, - GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7, - GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2, - GPIO_FN_AUDATA2, - - /* IPSR3 */ - GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2, - GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10, - GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12, - GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14, - GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1, - GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, - GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B, - GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18, - GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20, - GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22, - GPIO_FN_LCDOUT23, - GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B, - GPIO_FN_QCLK, - GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B, - GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B, - GPIO_FN_QSTH_QHS, - GPIO_FN_QSTB_QHE, - GPIO_FN_QCPV_QDE, - GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON, - - /* IPSR4 */ - GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, - GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, - GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, - GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, - GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B, - GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0, - GPIO_FN_AUDSYNC, - GPIO_FN_VI2_G0, - GPIO_FN_VI2_G1, GPIO_FN_VI2_G2, - GPIO_FN_VI2_G3, GPIO_FN_VI2_G4, - GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2, - GPIO_FN_SCL1_B, GPIO_FN_AUDATA6, - GPIO_FN_VI2_DATA3_VI2_B3, - GPIO_FN_SDA1_B, GPIO_FN_AUDATA7, - GPIO_FN_VI2_G6, - GPIO_FN_VI2_G7, GPIO_FN_VI2_R0, - GPIO_FN_VI2_R1, GPIO_FN_VI2_R2, - GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4, - GPIO_FN_SCL2_B, - - /* IPSR5 */ - GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B, - GPIO_FN_VI2_R4, GPIO_FN_VI2_R5, - GPIO_FN_VI2_R6, GPIO_FN_VI2_R7, - GPIO_FN_SCL2_D, GPIO_FN_SDA2_D, - GPIO_FN_VI2_CLKENB, - GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD, - GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC, - GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC, - GPIO_FN_VI3_VSYNC, - GPIO_FN_VI2_CLK, - GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, - GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN, - GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6, - GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, - GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, - GPIO_FN_VI2_DATA7_VI2_B7, - GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, - GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C, - GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, - GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0, - GPIO_FN_MOUT0, - - /* IPSR6 */ - GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1, - GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2, - GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5, - GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6, - GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34, - GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX, - GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7, - GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C, - GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8, - GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B, - GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C, - GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10, - GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP, - GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5, - GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, - GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B, - - /* IPSR7 */ - GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B, - GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B, - GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, - GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78, - GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B, - GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, - GPIO_FN_TCLK1_C, - GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, - GPIO_FN_ATACS01, - GPIO_FN_ATACS11, GPIO_FN_CC5_TDO, - GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST, - GPIO_FN_ATAG1, GPIO_FN_CC5_TMS, - GPIO_FN_ATARD1, GPIO_FN_CC5_TCK, - GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI, - GPIO_FN_DREQ2, GPIO_FN_DACK2, - - /* IPSR8 */ - GPIO_FN_AD_CLK, - GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20, - GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, - GPIO_FN_AD_DI, - GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21, - GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, - GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO, - GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22, - GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, - GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7, - GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31, - GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE, - GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA, - GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, - GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, - GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B, - GPIO_FN_HSCK1_B, - GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B, - GPIO_FN_PWMFSW0_C, - - /* IPSR9 */ - GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO, - GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM, - GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3, - GPIO_FN_VI0_DATA4_VI0_B4, - GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6, - GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7, - GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0, - GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2, - GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, - GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1, - GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0, - GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, - GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4, - GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6, - GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, - GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0, - GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7, - GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9, - - /* IPSR10 */ - GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B, - GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1, - GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11, - GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK, - GPIO_FN_ARM_TRACEDATA_12, - GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, - GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK, - GPIO_FN_ARM_TRACEDATA_14, - GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0, - GPIO_FN_ARM_TRACEDATA_15, - GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC, - GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK, - GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO, - GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D, - GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D, - GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4, - GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC, - GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK, - GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3, - - /* IPSR11 */ - GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST, - GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1, - GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS, - GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, - GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B, - GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN, - GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4, - GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST, - GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5, - GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK, - GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6, - GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, - GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM, - GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, - GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, - GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1, - GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, - GPIO_FN_HRTS0_B, - - /* IPSR12 */ - GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1, - GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3, - GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B, - GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C, - GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5, - GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B, - GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB, - GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7, - GPIO_FN_GPS_MAG, GPIO_FN_FCE, -}; - struct platform_device; struct r8a7779_pm_ch { From 119f5e448d32c11faf22fe81f6f2d78467a47149 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Mar 2013 20:32:13 +0900 Subject: [PATCH 274/307] gpio: Renesas R-Car GPIO driver V3 This patch is V3 of a GPIO driver for the R-Car series of SoCs from Renesas. This driver is designed to be reusable between multiple SoCs that share the same basic building block, but so far it has only been used on R-Car H1 (r8a7779). Each driver instance handles 32 GPIOs with individually maskable IRQs. The driver operates on a single I/O memory range and the 32 GPIOs are hooked up a single interrupt. In the case of R-Car H1 either external IRQ pins or GPIOs with interrupts can be used for on-board interupts. For external IRQs 4 pins are supported, and in the case of GPIO there are 202 GPIOS as 202 interrupts hooked up via 6 driver instances and to the GIC and the Cortex-A9 Quad. At this point this driver is interfacing as a regular platform device driver. In the future DT support will be submitted as an incremental feature patch. Signed-off-by: Magnus Damm Reviewed-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rcar.c | 373 ++++++++++++++++++++++++ include/linux/platform_data/gpio-rcar.h | 25 ++ 4 files changed, 405 insertions(+) create mode 100644 drivers/gpio/gpio-rcar.c create mode 100644 include/linux/platform_data/gpio-rcar.h diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 93aaadf99f28..d766e3cbef18 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -204,6 +204,12 @@ config GPIO_PXA help Say yes here to support the PXA GPIO device +config GPIO_RCAR + tristate "Renesas R-Car GPIO" + depends on ARM + help + Say yes here to support GPIO on Renesas R-Car SoCs. + config GPIO_SPEAR_SPICS bool "ST SPEAr13xx SPI Chip Select as GPIO support" depends on PLAT_SPEAR diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 22e07bc9fcb5..b41c74d45287 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o +obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SCH) += gpio-sch.o diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c new file mode 100644 index 000000000000..581ba56131a7 --- /dev/null +++ b/drivers/gpio/gpio-rcar.c @@ -0,0 +1,373 @@ +/* + * Renesas R-Car GPIO Support + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct gpio_rcar_priv { + void __iomem *base; + spinlock_t lock; + struct gpio_rcar_config config; + struct platform_device *pdev; + struct gpio_chip gpio_chip; + struct irq_chip irq_chip; + struct irq_domain *irq_domain; +}; + +#define IOINTSEL 0x00 +#define INOUTSEL 0x04 +#define OUTDT 0x08 +#define INDT 0x0c +#define INTDT 0x10 +#define INTCLR 0x14 +#define INTMSK 0x18 +#define MSKCLR 0x1c +#define POSNEG 0x20 +#define EDGLEVEL 0x24 +#define FILONOFF 0x28 + +static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) +{ + return ioread32(p->base + offs); +} + +static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, + u32 value) +{ + iowrite32(value, p->base + offs); +} + +static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, + int bit, bool value) +{ + u32 tmp = gpio_rcar_read(p, offs); + + if (value) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + + gpio_rcar_write(p, offs, tmp); +} + +static void gpio_rcar_irq_disable(struct irq_data *d) +{ + struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); + + gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); +} + +static void gpio_rcar_irq_enable(struct irq_data *d) +{ + struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); + + gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); +} + +static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, + unsigned int hwirq, + bool active_high_rising_edge, + bool level_trigger) +{ + unsigned long flags; + + /* follow steps in the GPIO documentation for + * "Setting Edge-Sensitive Interrupt Input Mode" and + * "Setting Level-Sensitive Interrupt Input Mode" + */ + + spin_lock_irqsave(&p->lock, flags); + + /* Configure postive or negative logic in POSNEG */ + gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); + + /* Configure edge or level trigger in EDGLEVEL */ + gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); + + /* Select "Interrupt Input Mode" in IOINTSEL */ + gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); + + /* Write INTCLR in case of edge trigger */ + if (!level_trigger) + gpio_rcar_write(p, INTCLR, BIT(hwirq)); + + spin_unlock_irqrestore(&p->lock, flags); +} + +static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); + unsigned int hwirq = irqd_to_hwirq(d); + + dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_HIGH: + gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true); + break; + case IRQ_TYPE_LEVEL_LOW: + gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true); + break; + case IRQ_TYPE_EDGE_RISING: + gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false); + break; + case IRQ_TYPE_EDGE_FALLING: + gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false); + break; + default: + return -EINVAL; + } + return 0; +} + +static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) +{ + struct gpio_rcar_priv *p = dev_id; + u32 pending; + unsigned int offset, irqs_handled = 0; + + while ((pending = gpio_rcar_read(p, INTDT))) { + offset = __ffs(pending); + gpio_rcar_write(p, INTCLR, BIT(offset)); + generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); + irqs_handled++; + } + + return irqs_handled ? IRQ_HANDLED : IRQ_NONE; +} + +static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip) +{ + return container_of(chip, struct gpio_rcar_priv, gpio_chip); +} + +static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, + unsigned int gpio, + bool output) +{ + struct gpio_rcar_priv *p = gpio_to_priv(chip); + unsigned long flags; + + /* follow steps in the GPIO documentation for + * "Setting General Output Mode" and + * "Setting General Input Mode" + */ + + spin_lock_irqsave(&p->lock, flags); + + /* Configure postive logic in POSNEG */ + gpio_rcar_modify_bit(p, POSNEG, gpio, false); + + /* Select "General Input/Output Mode" in IOINTSEL */ + gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); + + /* Select Input Mode or Output Mode in INOUTSEL */ + gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); + + spin_unlock_irqrestore(&p->lock, flags); +} + +static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) +{ + gpio_rcar_config_general_input_output_mode(chip, offset, false); + return 0; +} + +static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) +{ + return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset)); +} + +static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct gpio_rcar_priv *p = gpio_to_priv(chip); + unsigned long flags; + + spin_lock_irqsave(&p->lock, flags); + gpio_rcar_modify_bit(p, OUTDT, offset, value); + spin_unlock_irqrestore(&p->lock, flags); +} + +static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + /* write GPIO value to output before selecting output mode of pin */ + gpio_rcar_set(chip, offset, value); + gpio_rcar_config_general_input_output_mode(chip, offset, true); + return 0; +} + +static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); +} + +static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct gpio_rcar_priv *p = h->host_data; + + dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq); + + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; +} + +static struct irq_domain_ops gpio_rcar_irq_domain_ops = { + .map = gpio_rcar_irq_domain_map, +}; + +static int gpio_rcar_probe(struct platform_device *pdev) +{ + struct gpio_rcar_config *pdata = pdev->dev.platform_data; + struct gpio_rcar_priv *p; + struct resource *io, *irq; + struct gpio_chip *gpio_chip; + struct irq_chip *irq_chip; + const char *name = dev_name(&pdev->dev); + int ret; + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + ret = -ENOMEM; + goto err0; + } + + /* deal with driver instance configuration */ + if (pdata) + p->config = *pdata; + + p->pdev = pdev; + platform_set_drvdata(pdev, p); + spin_lock_init(&p->lock); + + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + + if (!io || !irq) { + dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); + ret = -EINVAL; + goto err0; + } + + p->base = devm_ioremap_nocache(&pdev->dev, io->start, + resource_size(io)); + if (!p->base) { + dev_err(&pdev->dev, "failed to remap I/O memory\n"); + ret = -ENXIO; + goto err0; + } + + gpio_chip = &p->gpio_chip; + gpio_chip->direction_input = gpio_rcar_direction_input; + gpio_chip->get = gpio_rcar_get; + gpio_chip->direction_output = gpio_rcar_direction_output; + gpio_chip->set = gpio_rcar_set; + gpio_chip->to_irq = gpio_rcar_to_irq; + gpio_chip->label = name; + gpio_chip->owner = THIS_MODULE; + gpio_chip->base = p->config.gpio_base; + gpio_chip->ngpio = p->config.number_of_pins; + + irq_chip = &p->irq_chip; + irq_chip->name = name; + irq_chip->irq_mask = gpio_rcar_irq_disable; + irq_chip->irq_unmask = gpio_rcar_irq_enable; + irq_chip->irq_enable = gpio_rcar_irq_enable; + irq_chip->irq_disable = gpio_rcar_irq_disable; + irq_chip->irq_set_type = gpio_rcar_irq_set_type; + irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED; + + p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, + p->config.number_of_pins, + p->config.irq_base, + &gpio_rcar_irq_domain_ops, p); + if (!p->irq_domain) { + ret = -ENXIO; + dev_err(&pdev->dev, "cannot initialize irq domain\n"); + goto err1; + } + + if (devm_request_irq(&pdev->dev, irq->start, + gpio_rcar_irq_handler, 0, name, p)) { + dev_err(&pdev->dev, "failed to request IRQ\n"); + ret = -ENOENT; + goto err1; + } + + ret = gpiochip_add(gpio_chip); + if (ret) { + dev_err(&pdev->dev, "failed to add GPIO controller\n"); + goto err1; + } + + dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins); + + /* warn in case of mismatch if irq base is specified */ + if (p->config.irq_base) { + ret = irq_find_mapping(p->irq_domain, 0); + if (p->config.irq_base != ret) + dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n", + p->config.irq_base, ret); + } + + return 0; + +err1: + irq_domain_remove(p->irq_domain); +err0: + return ret; +} + +static int gpio_rcar_remove(struct platform_device *pdev) +{ + struct gpio_rcar_priv *p = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&p->gpio_chip); + if (ret) + return ret; + + irq_domain_remove(p->irq_domain); + return 0; +} + +static struct platform_driver gpio_rcar_device_driver = { + .probe = gpio_rcar_probe, + .remove = gpio_rcar_remove, + .driver = { + .name = "gpio_rcar", + } +}; + +module_platform_driver(gpio_rcar_device_driver); + +MODULE_AUTHOR("Magnus Damm"); +MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h new file mode 100644 index 000000000000..bebfcd86fb80 --- /dev/null +++ b/include/linux/platform_data/gpio-rcar.h @@ -0,0 +1,25 @@ +/* + * Renesas R-Car GPIO Support + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_RCAR_H__ +#define __GPIO_RCAR_H__ + +struct gpio_rcar_config { + unsigned int gpio_base; + unsigned int irq_base; + unsigned int number_of_pins; +}; + +#endif /* __GPIO_RCAR_H__ */ From dc3465a943ed2dd5de37d3d60df5c4e11c49efcb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 03:27:00 +0100 Subject: [PATCH 275/307] gpio-rcar: Add pinctrl support Register the GPIO pin range, and request and free GPIO pins using the pinctrl API. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/gpio/gpio-rcar.c | 23 +++++++++++++++++++++++ include/linux/platform_data/gpio-rcar.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 581ba56131a7..b4ca450947b8 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -190,6 +191,21 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, spin_unlock_irqrestore(&p->lock, flags); } +static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); + + /* Set the GPIO as an input to ensure that the next GPIO request won't + * drive the GPIO pin as an output. + */ + gpio_rcar_config_general_input_output_mode(chip, offset, false); +} + static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) { gpio_rcar_config_general_input_output_mode(chip, offset, false); @@ -285,6 +301,8 @@ static int gpio_rcar_probe(struct platform_device *pdev) } gpio_chip = &p->gpio_chip; + gpio_chip->request = gpio_rcar_request; + gpio_chip->free = gpio_rcar_free; gpio_chip->direction_input = gpio_rcar_direction_input; gpio_chip->get = gpio_rcar_get; gpio_chip->direction_output = gpio_rcar_direction_output; @@ -337,6 +355,11 @@ static int gpio_rcar_probe(struct platform_device *pdev) p->config.irq_base, ret); } + ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, + gpio_chip->base, gpio_chip->ngpio); + if (ret < 0) + dev_warn(&pdev->dev, "failed to add pin range\n"); + return 0; err1: diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h index bebfcd86fb80..b253f77a7ddf 100644 --- a/include/linux/platform_data/gpio-rcar.h +++ b/include/linux/platform_data/gpio-rcar.h @@ -20,6 +20,7 @@ struct gpio_rcar_config { unsigned int gpio_base; unsigned int irq_base; unsigned int number_of_pins; + const char *pctl_name; }; #endif /* __GPIO_RCAR_H__ */ From 48b1e3e80f742bff0f469245f2d05007af9af92e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 03:43:32 +0100 Subject: [PATCH 276/307] ARM: shmobile: marzen: Add GPIO LEDs The board has 3 LEDs connected to GPIOs. Add a led-gpio device to support them. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-marzen.c | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 5852331743e7..a88f7f3594c7 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = { .num_resources = ARRAY_SIZE(usb_phy_resources), }; +/* LEDS */ +static struct gpio_led marzen_leds[] = { + { + .name = "led2", + .gpio = 157, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led3", + .gpio = 158, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led4", + .gpio = 159, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, +}; + +static struct gpio_led_platform_data marzen_leds_pdata = { + .leds = marzen_leds, + .num_leds = ARRAY_SIZE(marzen_leds), +}; + +static struct platform_device leds_device = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &marzen_leds_pdata, + }, +}; + static struct platform_device *marzen_devices[] __initdata = { ð_device, &sdhi0_device, &thermal_device, &hspi_device, &usb_phy_device, + &leds_device, }; /* USB */ From 542a564d2ddbd2c37536b4dff8e45fa0fc239bcc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 7 Mar 2013 14:31:57 +0100 Subject: [PATCH 277/307] sh-pfc: Make function GPIOs support optional The target is to get rid of function GPIOs completely. To reach this, make function GPIOs support optional by skipping the function GPIO chip registration if no function GPIOS are defined in SoC data. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/gpio.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index d7acb06d888c..7a54ec79518b 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -384,6 +384,9 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) } /* Register the function GPIOs chip. */ + if (pfc->info->nr_func_gpios == 0) + return 0; + chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); if (IS_ERR(chip)) return PTR_ERR(chip); From 1a4fd58f76cf331c93daaa1667daa25db297d0d4 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 03:19:44 +0100 Subject: [PATCH 278/307] sh-pfc: Make GPIO support optional When implemented as a separate IP block, GPIOs should be handled by a separate driver. To make this possible GPIO support needs to be optional in the sh-pfc driver. If no GPIO data registers are supplied in the SoC information structure skip registration of the gpiochip. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/gpio.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 7a54ec79518b..317cebb0ee4d 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -354,6 +354,9 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) unsigned int i; int ret; + if (pfc->info->data_regs == NULL) + return 0; + /* Register the real GPIOs chip. */ chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); if (IS_ERR(chip)) From ceef91dcc0bca0a39c54d2f0071848b6d5c66b88 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 03:19:44 +0100 Subject: [PATCH 279/307] sh-pfc: Skip gpiochip registration when no GPIO resource is found Boards/platforms that register dedicated GPIO devices will not supply a memory resource for GPIOs. Try to locate the GPIO memory resource at initialization time, and skip registration of the gpiochip if the resource can't be found. This is a temporary modification to ease the transition to separate GPIO drivers. It should be reverted when all boards and platforms will have been moved. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/gpio.c | 39 +++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 317cebb0ee4d..d37efa7dcf90 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -101,24 +101,9 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio) static int gpio_setup_data_regs(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; - unsigned long addr = pfc->info->data_regs[0].reg; const struct pinmux_data_reg *dreg; unsigned int i; - /* Find the window that contain the GPIO registers. */ - for (i = 0; i < pfc->num_windows; ++i) { - struct sh_pfc_window *window = &pfc->window[i]; - - if (addr >= window->phys && addr < window->phys + window->size) - break; - } - - if (i == pfc->num_windows) - return -EINVAL; - - /* GPIO data registers must be in the first memory resource. */ - chip->mem = &pfc->window[i]; - /* Count the number of data registers, allocate memory and initialize * them. */ @@ -319,7 +304,8 @@ static int gpio_function_setup(struct sh_pfc_chip *chip) */ static struct sh_pfc_chip * -sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *)) +sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), + struct sh_pfc_window *mem) { struct sh_pfc_chip *chip; int ret; @@ -328,6 +314,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *)) if (unlikely(!chip)) return ERR_PTR(-ENOMEM); + chip->mem = mem; chip->pfc = pfc; ret = setup(chip); @@ -357,8 +344,24 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) if (pfc->info->data_regs == NULL) return 0; + /* Find the memory window that contain the GPIO registers. Boards that + * register a separate GPIO device will not supply a memory resource + * that covers the data registers. In that case don't try to handle + * GPIOs. + */ + for (i = 0; i < pfc->num_windows; ++i) { + struct sh_pfc_window *window = &pfc->window[i]; + + if (pfc->info->data_regs[0].reg >= window->phys && + pfc->info->data_regs[0].reg < window->phys + window->size) + break; + } + + if (i == pfc->num_windows) + return 0; + /* Register the real GPIOs chip. */ - chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); + chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]); if (IS_ERR(chip)) return PTR_ERR(chip); @@ -390,7 +393,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) if (pfc->info->nr_func_gpios == 0) return 0; - chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); + chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); if (IS_ERR(chip)) return PTR_ERR(chip); From e3c470510babd8ed385f1e09ec616787022b77b1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 17:30:25 +0100 Subject: [PATCH 280/307] sh-pfc: Configure pins as GPIOs at request time when handled externally When a GPIO is handled by a separate driver the pinmux gpio_set_direction() handler won't be called. The pin mux type then need to be configured to GPIO at request time. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/core.c | 37 ++++++++++++++------------------ drivers/pinctrl/sh-pfc/pinctrl.c | 11 ++++++++++ 2 files changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 97e6ea3147e0..ced9a95aa1fc 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -268,7 +268,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) int ret; switch (pinmux_type) { - + case PINMUX_TYPE_GPIO: case PINMUX_TYPE_FUNCTION: range = NULL; break; @@ -297,6 +297,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) enum_id = 0; field = 0; value = 0; + + /* Iterate over all the configuration fields we need to update. */ while (1) { pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); if (pos < 0) @@ -305,18 +307,20 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) if (!enum_id) break; - /* first check if this is a function enum */ + /* Check if the configuration field selects a function. If it + * doesn't, skip the field if it's not applicable to the + * requested pinmux type. + */ in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); if (!in_range) { - /* not a function enum */ - if (range) { - /* - * other range exists, so this pin is - * a regular GPIO pin that now is being - * bound to a specific direction. - * - * for this case we only allow function enums - * and the enums that match the other range. + if (pinmux_type == PINMUX_TYPE_FUNCTION) { + /* Functions are allowed to modify all + * fields. + */ + in_range = 1; + } else if (pinmux_type != PINMUX_TYPE_GPIO) { + /* Input/output types can only modify fields + * that correspond to their respective ranges. */ in_range = sh_pfc_enum_in_range(enum_id, range); @@ -327,17 +331,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) */ if (in_range && enum_id == range->force) continue; - } else { - /* - * no other range exists, so this pin - * must then be of the function type. - * - * allow function type pins to select - * any combination of function/in/out - * in their MARK lists. - */ - in_range = 1; } + /* GPIOs are only allowed to modify function fields. */ } if (!in_range) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index aef268bc17ba..3492ec9a33b7 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -182,6 +182,17 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, goto done; } + if (!pfc->gpio) { + /* If GPIOs are handled externally the pin mux type need to be + * set to GPIO here. + */ + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + + ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); + if (ret < 0) + goto done; + } + cfg->type = PINMUX_TYPE_GPIO; ret = 0; From 37a72d074d9658172dfef69c56ea7c0e9a9f6d1e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 03:31:51 +0100 Subject: [PATCH 281/307] ARM: shmobile: r8a7779: Register GPIO devices Move GPIOs handling from the PFC device to separate GPIO devices. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 58 +++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 042df35e71a0..a460ba3dedcb 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -68,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = { .end = 0xfffc023b, .flags = IORESOURCE_MEM, }, - [1] = { - .start = 0xffc40000, - .end = 0xffc46fff, - .flags = IORESOURCE_MEM, - } }; static struct platform_device r8a7779_pfc_device = { @@ -82,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = { .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), }; +#define R8A7779_GPIO(idx, npins) \ +static struct resource r8a7779_gpio##idx##_resources[] = { \ + [0] = { \ + .start = 0xffc40000 + 0x1000 * (idx), \ + .end = 0xffc4002b + 0x1000 * (idx), \ + .flags = IORESOURCE_MEM, \ + }, \ + [1] = { \ + .start = gic_iid(0xad + (idx)), \ + .flags = IORESOURCE_IRQ, \ + } \ +}; \ + \ +static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ + .gpio_base = 32 * (idx), \ + .irq_base = 0, \ + .number_of_pins = npins, \ + .pctl_name = "pfc-r8a7779", \ +}; \ + \ +static struct platform_device r8a7779_gpio##idx##_device = { \ + .name = "gpio_rcar", \ + .id = idx, \ + .resource = r8a7779_gpio##idx##_resources, \ + .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ + .dev = { \ + .platform_data = &r8a7779_gpio##idx##_platform_data, \ + }, \ +} + +R8A7779_GPIO(0, 32); +R8A7779_GPIO(1, 32); +R8A7779_GPIO(2, 32); +R8A7779_GPIO(3, 32); +R8A7779_GPIO(4, 32); +R8A7779_GPIO(5, 32); +R8A7779_GPIO(6, 9); + +static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { + &r8a7779_pfc_device, + &r8a7779_gpio0_device, + &r8a7779_gpio1_device, + &r8a7779_gpio2_device, + &r8a7779_gpio3_device, + &r8a7779_gpio4_device, + &r8a7779_gpio5_device, + &r8a7779_gpio6_device, +}; + void __init r8a7779_pinmux_init(void) { - platform_device_register(&r8a7779_pfc_device); + platform_add_devices(r8a7779_pinctrl_devices, + ARRAY_SIZE(r8a7779_pinctrl_devices)); } static struct plat_sci_port scif0_platform_data = { From 2b4b588299fa3c8672e1049ab33acc7b600a8990 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 10 Mar 2013 04:02:15 +0100 Subject: [PATCH 282/307] sh-pfc: r8a7779: Remove GPIO data GPIOs are now handled by a separate driver, remove GPIO data from the SoC information structure. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 58 +--------------------------- 1 file changed, 1 insertion(+), 57 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 41d8bda45163..e448ff1f408f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -85,18 +85,12 @@ } #define _GP_DATA(bank, pin, name, sfx) \ - PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT) - -#define _GP_INOUTSEL(bank, pin, name, sfx) name##_IN, name##_OUT -#define _GP_INDT(bank, pin, name, sfx) name##_DATA + PINMUX_DATA(name##_DATA, name##_FN) #define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) -#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused) -#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused) - #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ FN_##ipsr, FN_##fn) @@ -108,14 +102,6 @@ enum { GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ PINMUX_DATA_END, - PINMUX_INPUT_BEGIN, - GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */ - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */ - PINMUX_OUTPUT_END, - PINMUX_FUNCTION_BEGIN, GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ @@ -3549,45 +3535,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C1 [2] */ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 } }, - { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } }, - { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } }, - { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } }, - { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } }, - { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } }, - { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } }, - { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_8_IN, GP_6_8_OUT, - GP_6_7_IN, GP_6_7_OUT, - GP_6_6_IN, GP_6_6_OUT, - GP_6_5_IN, GP_6_5_OUT, - GP_6_4_IN, GP_6_4_OUT, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, } - }, - { }, -}; - -static const struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } }, - { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } }, - { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } }, - { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } }, - { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } }, - { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } }, - { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA, - GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, - GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } - }, { }, }; @@ -3596,8 +3543,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = { .unlock_reg = 0xfffc0000, /* PMMR */ - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .pins = pinmux_pins, @@ -3608,7 +3553,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, .gpio_data = pinmux_data, .gpio_data_size = ARRAY_SIZE(pinmux_data), From ba774cc7380e83f942c08564d3c142af2fbd05be Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 27 Mar 2013 11:06:37 +0100 Subject: [PATCH 283/307] sh-pfc: r8a7779: Split DU input and output pixel clocks The output pixel clocks can be used without the input pixel clocks. Split them in different groups. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 60 ++++++++++++++++++---------- 1 file changed, 39 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index e448ff1f408f..62dcdcdec940 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1498,19 +1498,26 @@ static const unsigned int du0_rgb888_mux[] = { DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, }; -static const unsigned int du0_clk_0_pins[] = { - /* CLKIN, CLKOUT */ - 29, 180, +static const unsigned int du0_clk_in_pins[] = { + /* CLKIN */ + 29, }; -static const unsigned int du0_clk_0_mux[] = { - DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK, +static const unsigned int du0_clk_in_mux[] = { + DU0_DOTCLKIN_MARK, }; -static const unsigned int du0_clk_1_pins[] = { - /* CLKIN, CLKOUT */ - 29, 30, +static const unsigned int du0_clk_out_0_pins[] = { + /* CLKOUT */ + 180, }; -static const unsigned int du0_clk_1_mux[] = { - DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK, +static const unsigned int du0_clk_out_0_mux[] = { + DU0_DOTCLKOUT0_MARK, +}; +static const unsigned int du0_clk_out_1_pins[] = { + /* CLKOUT */ + 30, +}; +static const unsigned int du0_clk_out_1_mux[] = { + DU0_DOTCLKOUT1_MARK, }; static const unsigned int du0_sync_0_pins[] = { /* VSYNC, HSYNC, DISP */ @@ -1571,12 +1578,19 @@ static const unsigned int du1_rgb888_mux[] = { DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, }; -static const unsigned int du1_clk_pins[] = { - /* CLKIN, CLKOUT */ - 58, 59, +static const unsigned int du1_clk_in_pins[] = { + /* CLKIN */ + 58, }; -static const unsigned int du1_clk_mux[] = { - DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK, +static const unsigned int du1_clk_in_mux[] = { + DU1_DOTCLKIN_MARK, +}; +static const unsigned int du1_clk_out_pins[] = { + /* CLKOUT */ + 59, +}; +static const unsigned int du1_clk_out_mux[] = { + DU1_DOTCLKOUT_MARK, }; static const unsigned int du1_sync_0_pins[] = { /* VSYNC, HSYNC, DISP */ @@ -2369,15 +2383,17 @@ static const unsigned int usb2_mux[] = { static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_rgb666), SH_PFC_PIN_GROUP(du0_rgb888), - SH_PFC_PIN_GROUP(du0_clk_0), - SH_PFC_PIN_GROUP(du0_clk_1), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du0_clk_out_0), + SH_PFC_PIN_GROUP(du0_clk_out_1), SH_PFC_PIN_GROUP(du0_sync_0), SH_PFC_PIN_GROUP(du0_sync_1), SH_PFC_PIN_GROUP(du0_oddf), SH_PFC_PIN_GROUP(du0_cde), SH_PFC_PIN_GROUP(du1_rgb666), SH_PFC_PIN_GROUP(du1_rgb888), - SH_PFC_PIN_GROUP(du1_clk), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_clk_out), SH_PFC_PIN_GROUP(du1_sync_0), SH_PFC_PIN_GROUP(du1_sync_1), SH_PFC_PIN_GROUP(du1_oddf), @@ -2492,8 +2508,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { static const char * const du0_groups[] = { "du0_rgb666", "du0_rgb888", - "du0_clk_0", - "du0_clk_1", + "du0_clk_in", + "du0_clk_out_0", + "du0_clk_out_1", "du0_sync_0", "du0_sync_1", "du0_oddf", @@ -2503,7 +2520,8 @@ static const char * const du0_groups[] = { static const char * const du1_groups[] = { "du1_rgb666", "du1_rgb888", - "du1_clk", + "du1_clk_in", + "du1_clk_out", "du1_sync_0", "du1_sync_1", "du1_oddf", From c98f6c21afaf4692886cea0f5b63ead9945d85cc Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:49:49 +0900 Subject: [PATCH 284/307] sh-pfc: Add r8a73a4 pinmux support Add initial PFC support for the r8a73a4 SoC. At this point only GPIO interface is supported, move to newer interfaces planned as incremental changes. Original authors are Morimoto-san with help from Yoshii-san, thanks to them for the heavy lifting. Adjusted by Magnus to work together with updated code in drivers/pinctrl. Signed-off-by: Kuninori Morimoto Signed-off-by: Takashi Yoshii Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/r8a73a4.h | 918 ++++++ drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 3 + drivers/pinctrl/sh-pfc/core.h | 1 + drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 2826 +++++++++++++++++ 6 files changed, 3754 insertions(+) create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index f043103e32c9..f0b1b4a962b3 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -1,6 +1,924 @@ #ifndef __ASM_R8A73A4_H__ #define __ASM_R8A73A4_H__ +/* + * Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + + /* PORT */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, + GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, + + GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, GPIO_PORT283, + GPIO_PORT288, GPIO_PORT289, + + GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, + GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, + + GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, + GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, + + GPIO_PORT320, GPIO_PORT321, GPIO_PORT322, GPIO_PORT323, GPIO_PORT324, + GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329, + + /* Port0 */ + GPIO_FN_LCDD0, + GPIO_FN_PDM2_CLK_0, + GPIO_FN_DU0_DR0, + GPIO_FN_IRQ0, + + /* Port1 */ + GPIO_FN_LCDD1, + GPIO_FN_PDM2_DATA_1, + GPIO_FN_DU0_DR19, + GPIO_FN_IRQ1, + + /* Port2 */ + GPIO_FN_LCDD2, + GPIO_FN_PDM3_CLK_2, + GPIO_FN_DU0_DR2, + GPIO_FN_IRQ2, + + /* Port3 */ + GPIO_FN_LCDD3, + GPIO_FN_PDM3_DATA_3, + GPIO_FN_DU0_DR3, + GPIO_FN_IRQ3, + + /* Port4 */ + GPIO_FN_LCDD4, + GPIO_FN_PDM4_CLK_4, + GPIO_FN_DU0_DR4, + GPIO_FN_IRQ4, + + /* Port5 */ + GPIO_FN_LCDD5, + GPIO_FN_PDM4_DATA_5, + GPIO_FN_DU0_DR5, + GPIO_FN_IRQ5, + + /* Port6 */ + GPIO_FN_LCDD6, + GPIO_FN_PDM0_OUTCLK_6, + GPIO_FN_DU0_DR6, + GPIO_FN_IRQ6, + + /* Port7 */ + GPIO_FN_LCDD7, + GPIO_FN_PDM0_OUTDATA_7, + GPIO_FN_DU0_DR7, + GPIO_FN_IRQ7, + + /* Port8 */ + GPIO_FN_LCDD8, + GPIO_FN_PDM1_OUTCLK_8, + GPIO_FN_DU0_DG0, + GPIO_FN_IRQ8, + + /* Port9 */ + GPIO_FN_LCDD9, + GPIO_FN_PDM1_OUTDATA_9, + GPIO_FN_DU0_DG1, + GPIO_FN_IRQ9, + + /* Port10 */ + GPIO_FN_LCDD10, + GPIO_FN_FSICCK, + GPIO_FN_DU0_DG2, + GPIO_FN_IRQ10, + + /* Port11 */ + GPIO_FN_LCDD11, + GPIO_FN_FSICISLD, + GPIO_FN_DU0_DG3, + GPIO_FN_IRQ11, + + /* Port12 */ + GPIO_FN_LCDD12, + GPIO_FN_FSICOMC, + GPIO_FN_DU0_DG4, + GPIO_FN_IRQ12, + + /* Port13 */ + GPIO_FN_LCDD13, + GPIO_FN_FSICOLR, + GPIO_FN_FSICILR, + GPIO_FN_DU0_DG5, + GPIO_FN_IRQ13, + + /* Port14 */ + GPIO_FN_LCDD14, + GPIO_FN_FSICOBT, + GPIO_FN_FSICIBT, + GPIO_FN_DU0_DG6, + GPIO_FN_IRQ14, + + /* Port15 */ + GPIO_FN_LCDD15, + GPIO_FN_FSICOSLD, + GPIO_FN_DU0_DG7, + GPIO_FN_IRQ15, + + /* Port16 */ + GPIO_FN_LCDD16, + GPIO_FN_TPU1TO1, + GPIO_FN_DU0_DB0, + + /* Port17 */ + GPIO_FN_LCDD17, + GPIO_FN_SF_IRQ_00, + GPIO_FN_DU0_DB1, + + /* Port18 */ + GPIO_FN_LCDD18, + GPIO_FN_SF_IRQ_01, + GPIO_FN_DU0_DB2, + + /* Port19 */ + GPIO_FN_LCDD19, + GPIO_FN_SCIFB3_RTS_19, + GPIO_FN_DU0_DB3, + + /* Port20 */ + GPIO_FN_LCDD20, + GPIO_FN_SCIFB3_CTS_20, + GPIO_FN_DU0_DB4, + + /* Port21 */ + GPIO_FN_LCDD21, + GPIO_FN_SCIFB3_TXD_21, + GPIO_FN_DU0_DB5, + + /* Port22 */ + GPIO_FN_LCDD22, + GPIO_FN_SCIFB3_RXD_22, + GPIO_FN_DU0_DB6, + + /* Port23 */ + GPIO_FN_LCDD23, + GPIO_FN_SCIFB3_SCK_23, + GPIO_FN_DU0_DB7, + + /* Port24 */ + GPIO_FN_LCDHSYN, + GPIO_FN_LCDCS, + GPIO_FN_SCIFB1_RTS_24, + GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N, + + /* Port25 */ + GPIO_FN_LCDVSYN, + GPIO_FN_SCIFB1_CTS_25, + GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N, + + /* Port26 */ + GPIO_FN_LCDDCK, + GPIO_FN_LCDWR, + GPIO_FN_SCIFB1_TXD_26, + GPIO_FN_DU0_DOTCLKIN, + + /* Port27 */ + GPIO_FN_LCDDISP, + GPIO_FN_LCDRS, + GPIO_FN_SCIFB1_RXD_27, + GPIO_FN_DU0_DOTCLKOUT, + + /* Port28 */ + GPIO_FN_LCDRD_N, + GPIO_FN_SCIFB1_SCK_28, + GPIO_FN_DU0_DOTCLKOUTB, + + /* Port29 */ + GPIO_FN_LCDLCLK, + GPIO_FN_SF_IRQ_02, + GPIO_FN_DU0_DISP_CSYNC_N_DE, + + /* Port30 */ + GPIO_FN_LCDDON, + GPIO_FN_SF_IRQ_03, + GPIO_FN_DU0_ODDF_N_CLAMP, + + /* Port32 */ + GPIO_FN_SCIFA0_RTS, + GPIO_FN_SIM0_DET, + GPIO_FN_CSCIF0_RTS, + + /* Port33 */ + GPIO_FN_SCIFA0_CTS, + GPIO_FN_SIM1_DET, + GPIO_FN_CSCIF0_CTS, + + /* Port34 */ + GPIO_FN_SCIFA0_SCK, + GPIO_FN_SIM0_PWRON, + GPIO_FN_CSCIF0_SCK, + + /* Port35 */ + GPIO_FN_SCIFA1_RTS, + GPIO_FN_CSCIF1_RTS, + + /* Port36 */ + GPIO_FN_SCIFA1_CTS, + GPIO_FN_CSCIF1_CTS, + + /* Port37 */ + GPIO_FN_SCIFA1_SCK, + GPIO_FN_CSCIF1_SCK, + + /* Port38 */ + GPIO_FN_SCIFB0_RTS, + GPIO_FN_TPU0TO1, + GPIO_FN_SCIFB3_RTS_38, + GPIO_FN_CHSCIF0_HRTS, + + /* Port39 */ + GPIO_FN_SCIFB0_CTS, + GPIO_FN_TPU0TO2, + GPIO_FN_SCIFB3_CTS_39, + GPIO_FN_CHSCIF0_HCTS, + + /* Port40 */ + GPIO_FN_SCIFB0_SCK, + GPIO_FN_TPU0TO3, + GPIO_FN_SCIFB3_SCK_40, + GPIO_FN_CHSCIF0_HSCK, + + /* Port64 */ + GPIO_FN_PDM0_DATA, + + /* Port65 */ + GPIO_FN_PDM1_DATA, + + /* Port66 */ + GPIO_FN_HSI_RX_WAKE, + GPIO_FN_SCIFB2_CTS_66, + GPIO_FN_MSIOF3_SYNC, + GPIO_FN_GenIO4, + GPIO_FN_IRQ40, + + /* Port67 */ + GPIO_FN_HSI_RX_READY, + GPIO_FN_SCIFB1_TXD_67, + GPIO_FN_GIO_OUT3_67, + GPIO_FN_CHSCIF1_HTX, + + /* Port68 */ + GPIO_FN_HSI_RX_FLAG, + GPIO_FN_SCIFB2_TXD_68, + GPIO_FN_MSIOF3_TXD, + GPIO_FN_GIO_OUT4_68, + + /* Port69 */ + GPIO_FN_HSI_RX_DATA, + GPIO_FN_SCIFB2_RXD_69, + GPIO_FN_MSIOF3_RXD, + GPIO_FN_GIO_OUT5_69, + + /* Port70 */ + GPIO_FN_HSI_TX_FLAG, + GPIO_FN_SCIFB1_RTS_70, + GPIO_FN_GIO_OUT1_70, + GPIO_FN_HSIC_TSTCLK0, + GPIO_FN_CHSCIF1_HRTS, + + /* Port71 */ + GPIO_FN_HSI_TX_DATA, + GPIO_FN_SCIFB1_CTS_71, + GPIO_FN_GIO_OUT2_71, + GPIO_FN_HSIC_TSTCLK1, + GPIO_FN_CHSCIF1_HCTS, + + /* Port72 */ + GPIO_FN_HSI_TX_WAKE, + GPIO_FN_SCIFB1_RXD_72, + GPIO_FN_GenIO8, + GPIO_FN_CHSCIF1_HRX, + + /* Port73 */ + GPIO_FN_HSI_TX_READY, + GPIO_FN_SCIFB2_RTS_73, + GPIO_FN_MSIOF3_SCK, + GPIO_FN_GIO_OUT0_73, + + /* Port74 - Port85 */ + GPIO_FN_IRDA_OUT, + GPIO_FN_IRDA_IN, + GPIO_FN_IRDA_FIRSEL, + GPIO_FN_TPU0TO0, + GPIO_FN_DIGRFEN, + GPIO_FN_GPS_TIMESTAMP, + GPIO_FN_TXP, + GPIO_FN_TXP2, + GPIO_FN_COEX_0, + GPIO_FN_COEX_1, + GPIO_FN_IRQ19, + GPIO_FN_IRQ18, + + /* Port96 - Port101 */ + GPIO_FN_KEYIN0, + GPIO_FN_KEYIN1, + GPIO_FN_KEYIN2, + GPIO_FN_KEYIN3, + GPIO_FN_KEYIN4, + GPIO_FN_KEYIN5, + + /* Port102 */ + GPIO_FN_KEYIN6, + GPIO_FN_IRQ41, + + /* Port103 */ + GPIO_FN_KEYIN7, + GPIO_FN_IRQ42, + + /* Port104 - Port108 */ + GPIO_FN_KEYOUT0, + GPIO_FN_KEYOUT1, + GPIO_FN_KEYOUT2, + GPIO_FN_KEYOUT3, + GPIO_FN_KEYOUT4, + + /* Port109 */ + GPIO_FN_KEYOUT5, + GPIO_FN_IRQ43, + + /* Port110 */ + GPIO_FN_KEYOUT6, + GPIO_FN_IRQ44, + + /* Port111 */ + GPIO_FN_KEYOUT7, + GPIO_FN_RFANAEN, + GPIO_FN_IRQ45, + + /* Port112 */ + GPIO_FN_KEYIN8, + GPIO_FN_KEYOUT8, + GPIO_FN_SF_IRQ_04, + GPIO_FN_IRQ46, + + /* Port113 */ + GPIO_FN_KEYIN9, + GPIO_FN_KEYOUT9, + GPIO_FN_SF_IRQ_05, + GPIO_FN_IRQ47, + + /* Port114 */ + GPIO_FN_KEYIN10, + GPIO_FN_KEYOUT10, + GPIO_FN_SF_IRQ_06, + GPIO_FN_IRQ48, + + /* Port115 */ + GPIO_FN_KEYIN11, + GPIO_FN_KEYOUT11, + GPIO_FN_SF_IRQ_07, + GPIO_FN_IRQ49, + + /* Port116 */ + GPIO_FN_SCIFA0_TXD, + GPIO_FN_CSCIF0_TX, + + /* Port117 */ + GPIO_FN_SCIFA0_RXD, + GPIO_FN_CSCIF0_RX, + + /* Port118 */ + GPIO_FN_SCIFA1_TXD, + GPIO_FN_CSCIF1_TX, + + /* Port119 */ + GPIO_FN_SCIFA1_RXD, + GPIO_FN_CSCIF1_RX, + + /* Port120 */ + GPIO_FN_SF_PORT_1_120, + GPIO_FN_SCIFB3_RXD_120, + GPIO_FN_DU0_CDE, + + /* Port121 */ + GPIO_FN_SF_PORT_0_121, + GPIO_FN_SCIFB3_TXD_121, + + /* Port122 */ + GPIO_FN_SCIFB0_TXD, + GPIO_FN_CHSCIF0_HTX, + + /* Port123 */ + GPIO_FN_SCIFB0_RXD, + GPIO_FN_CHSCIF0_HRX, + + /* Port124 */ + GPIO_FN_ISP_STROBE_124, + + /* Port125 */ + GPIO_FN_STP_ISD_0, + GPIO_FN_PDM4_CLK_125, + GPIO_FN_MSIOF2_TXD, + GPIO_FN_SIM0_VOLTSEL0, + + /* Port126 */ + GPIO_FN_TS_SDEN, + GPIO_FN_MSIOF7_SYNC, + GPIO_FN_STP_ISEN_1, + + /* Port128 */ + GPIO_FN_STP_ISEN_0, + GPIO_FN_PDM1_OUTDATA_128, + GPIO_FN_MSIOF2_SYNC, + GPIO_FN_SIM1_VOLTSEL1, + + /* Port129 */ + GPIO_FN_TS_SPSYNC, + GPIO_FN_MSIOF7_RXD, + GPIO_FN_STP_ISSYNC_1, + + /* Port130 */ + GPIO_FN_STP_ISSYNC_0, + GPIO_FN_PDM4_DATA_130, + GPIO_FN_MSIOF2_RXD, + GPIO_FN_SIM0_VOLTSEL1, + + /* Port131 */ + GPIO_FN_STP_OPWM_0, + GPIO_FN_SIM1_PWRON, + + /* Port132 */ + GPIO_FN_TS_SCK, + GPIO_FN_MSIOF7_SCK, + GPIO_FN_STP_ISCLK_1, + + /* Port133 */ + GPIO_FN_STP_ISCLK_0, + GPIO_FN_PDM1_OUTCLK_133, + GPIO_FN_MSIOF2_SCK, + GPIO_FN_SIM1_VOLTSEL0, + + /* Port134 */ + GPIO_FN_TS_SDAT, + GPIO_FN_MSIOF7_TXD, + GPIO_FN_STP_ISD_1, + + /* Port160 - Port178 */ + GPIO_FN_IRQ20, + GPIO_FN_IRQ21, + GPIO_FN_IRQ22, + GPIO_FN_IRQ23, + GPIO_FN_MMCD0_0, + GPIO_FN_MMCD0_1, + GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, + GPIO_FN_MMCD0_4, + GPIO_FN_MMCD0_5, + GPIO_FN_MMCD0_6, + GPIO_FN_MMCD0_7, + GPIO_FN_MMCCMD0, + GPIO_FN_MMCCLK0, + GPIO_FN_MMCRST, + GPIO_FN_IRQ24, + GPIO_FN_IRQ25, + GPIO_FN_IRQ26, + GPIO_FN_IRQ27, + + /* Port192 - Port200 FN1 */ + GPIO_FN_A10, + GPIO_FN_A9, + GPIO_FN_A8, + GPIO_FN_A7, + GPIO_FN_A6, + GPIO_FN_A5, + GPIO_FN_A4, + GPIO_FN_A3, + GPIO_FN_A2, + + /* Port192 - Port200 FN2 */ + GPIO_FN_MMCD1_7, + GPIO_FN_MMCD1_6, + GPIO_FN_MMCD1_5, + GPIO_FN_MMCD1_4, + GPIO_FN_MMCD1_3, + GPIO_FN_MMCD1_2, + GPIO_FN_MMCD1_1, + GPIO_FN_MMCD1_0, + GPIO_FN_MMCCMD1, + + /* Port192 - Port200 IRQ */ + GPIO_FN_IRQ31, + GPIO_FN_IRQ32, + GPIO_FN_IRQ33, + GPIO_FN_IRQ34, + GPIO_FN_IRQ35, + GPIO_FN_IRQ36, + GPIO_FN_IRQ37, + GPIO_FN_IRQ38, + GPIO_FN_IRQ39, + + /* Port201 */ + GPIO_FN_A1, + + /* Port202 */ + GPIO_FN_A0, + GPIO_FN_BS, + + /* Port203 */ + GPIO_FN_CKO, + GPIO_FN_MMCCLK1, + + /* Port204 */ + GPIO_FN_CS0_N, + GPIO_FN_SIM0_GPO1, + + /* Port205 */ + GPIO_FN_CS2_N, + GPIO_FN_SIM0_GPO2, + + /* Port206 */ + GPIO_FN_CS4_N, + GPIO_FN_VIO_VD, + GPIO_FN_SIM1_GPO0, + + /* Port207 - Port212 FN1 */ + GPIO_FN_D15, + GPIO_FN_D14, + GPIO_FN_D13, + GPIO_FN_D12, + GPIO_FN_D11, + GPIO_FN_D10, + + /* Port207 - Port212 FN5 */ + GPIO_FN_GIO_OUT15, + GPIO_FN_GIO_OUT14, + GPIO_FN_GIO_OUT13, + GPIO_FN_GIO_OUT12, + GPIO_FN_WGM_TXP2, + GPIO_FN_WGM_GPS_TIMEM_ASK_RFCLK, + + /* Port213 - Port222 FN1 */ + GPIO_FN_D9, + GPIO_FN_D8, + GPIO_FN_D7, + GPIO_FN_D6, + GPIO_FN_D5, + GPIO_FN_D4, + GPIO_FN_D3, + GPIO_FN_D2, + GPIO_FN_D1, + GPIO_FN_D0, + + /* Port213 - Port222 FN2 */ + GPIO_FN_VIO_D9, + GPIO_FN_VIO_D8, + GPIO_FN_VIO_D7, + GPIO_FN_VIO_D6, + GPIO_FN_VIO_D5, + GPIO_FN_VIO_D4, + GPIO_FN_VIO_D3, + GPIO_FN_VIO_D2, + GPIO_FN_VIO_D1, + GPIO_FN_VIO_D0, + + /* Port213 - Port222 FN5 */ + GPIO_FN_GIO_OUT9, + GPIO_FN_GIO_OUT8, + GPIO_FN_GIO_OUT7, + GPIO_FN_GIO_OUT6, + GPIO_FN_GIO_OUT5_217, + GPIO_FN_GIO_OUT4_218, + GPIO_FN_GIO_OUT3_219, + GPIO_FN_GIO_OUT2_220, + GPIO_FN_GIO_OUT1_221, + GPIO_FN_GIO_OUT0_222, + + /* Port224 */ + GPIO_FN_RDWR_224, + GPIO_FN_VIO_HD, + GPIO_FN_SIM1_GPO2, + + /* Port225 */ + GPIO_FN_RD_N, + + /* Port226 */ + GPIO_FN_WAIT_N, + GPIO_FN_VIO_CLK, + GPIO_FN_SIM1_GPO1, + + /* Port227 */ + GPIO_FN_WE0_N, + GPIO_FN_RDWR_227, + + /* Port228 */ + GPIO_FN_WE1_N, + GPIO_FN_SIM0_GPO0, + + /* Port229 */ + GPIO_FN_PWMO, + GPIO_FN_VIO_CKO1_229, + + /* Port230 */ + GPIO_FN_SLIM_CLK, + GPIO_FN_VIO_CKO4_230, + + /* Port231 */ + GPIO_FN_SLIM_DATA, + GPIO_FN_VIO_CKO5_231, + + /* Port232 */ + GPIO_FN_VIO_CKO2_232, + GPIO_FN_SF_PORT_0_232, + + /* Port233 */ + GPIO_FN_VIO_CKO3_233, + GPIO_FN_SF_PORT_1_233, + + /* Port234 */ + GPIO_FN_FSIACK, + GPIO_FN_PDM3_CLK_234, + GPIO_FN_ISP_IRIS1_234, + + /* Port235 */ + GPIO_FN_FSIAISLD, + GPIO_FN_PDM3_DATA_235, + + /* Port236 */ + GPIO_FN_FSIAOMC, + GPIO_FN_PDM0_OUTCLK_236, + GPIO_FN_ISP_IRIS0_236, + + /* Port237 */ + GPIO_FN_FSIAOLR, + GPIO_FN_FSIAILR, + + /* Port238 */ + GPIO_FN_FSIAOBT, + GPIO_FN_FSIAIBT, + + /* Port239 */ + GPIO_FN_FSIAOSLD, + GPIO_FN_PDM0_OUTDATA_239, + + /* Port240 */ + GPIO_FN_FSIBISLD, + + /* Port241 */ + GPIO_FN_FSIBOLR, + GPIO_FN_FSIBILR, + + /* Port242 */ + GPIO_FN_FSIBOMC, + GPIO_FN_ISP_SHUTTER1_242, + + /* Port243 */ + GPIO_FN_FSIBOBT, + GPIO_FN_FSIBIBT, + + /* Port244 */ + GPIO_FN_FSIBOSLD, + GPIO_FN_FSIASPDIF, + + /* Port245 */ + GPIO_FN_FSIBCK, + GPIO_FN_ISP_SHUTTER0_245, + + /* Port246 - Port250 FN1 */ + GPIO_FN_ISP_IRIS1_246, + GPIO_FN_ISP_IRIS0_247, + GPIO_FN_ISP_SHUTTER1_248, + GPIO_FN_ISP_SHUTTER0_249, + GPIO_FN_ISP_STROBE_250, + + /* Port256 - Port258 */ + GPIO_FN_MSIOF0_SYNC, + GPIO_FN_MSIOF0_RXD, + GPIO_FN_MSIOF0_SCK, + + /* Port259 */ + GPIO_FN_MSIOF0_SS2, + GPIO_FN_VIO_CKO3_259, + + /* Port260 */ + GPIO_FN_MSIOF0_TXD, + + /* Port261 */ + GPIO_FN_SCIFB1_SCK_261, + GPIO_FN_CHSCIF1_HSCK, + + /* Port262 */ + GPIO_FN_SCIFB2_SCK_262, + + /* Port263 - Port266 FN1 */ + GPIO_FN_MSIOF1_SS2, + GPIO_FN_MSIOF1_TXD, + GPIO_FN_MSIOF1_RXD, + GPIO_FN_MSIOF1_SS1, + + /* Port263 - Port266 FN4 */ + GPIO_FN_MSIOF5_SS2, + GPIO_FN_MSIOF5_TXD, + GPIO_FN_MSIOF5_RXD, + GPIO_FN_MSIOF5_SS1, + + /* Port267 */ + GPIO_FN_MSIOF0_SS1, + + /* Port268 */ + GPIO_FN_MSIOF1_SCK, + GPIO_FN_MSIOF5_SCK, + + /* Port269 */ + GPIO_FN_MSIOF1_SYNC, + GPIO_FN_MSIOF5_SYNC, + + /* Port270 - Port273 FN1 */ + GPIO_FN_MSIOF2_SS1, + GPIO_FN_MSIOF2_SS2, + GPIO_FN_MSIOF3_SS2, + GPIO_FN_MSIOF3_SS1, + + /* Port270 - Port273 FN3 */ + GPIO_FN_VIO_CKO5_270, + GPIO_FN_VIO_CKO2_271, + GPIO_FN_VIO_CKO1_272, + GPIO_FN_VIO_CKO4_273, + + /* Port274 */ + GPIO_FN_MSIOF4_SS2, + GPIO_FN_TPU1TO0, + + /* Port275 - Port280 */ + GPIO_FN_IC_DP, + GPIO_FN_SIM0_RST, + GPIO_FN_IC_DM, + GPIO_FN_SIM0_BSICOMP, + GPIO_FN_SIM0_CLK, + GPIO_FN_SIM0_IO, + + /* Port281 */ + GPIO_FN_SIM1_IO, + GPIO_FN_PDM2_DATA_281, + + /* Port282 */ + GPIO_FN_SIM1_CLK, + GPIO_FN_PDM2_CLK_282, + + /* Port283 */ + GPIO_FN_SIM1_RST, + + /* Port289 */ + GPIO_FN_SDHID1_0, + GPIO_FN_STMDATA0_2, + + /* Port290 */ + GPIO_FN_SDHID1_1, + GPIO_FN_STMDATA1_2, + GPIO_FN_IRQ51, + + /* Port291 - Port294 FN1 */ + GPIO_FN_SDHID1_2, + GPIO_FN_SDHID1_3, + GPIO_FN_SDHICLK1, + GPIO_FN_SDHICMD1, + + /* Port291 - Port294 FN3 */ + GPIO_FN_STMDATA2_2, + GPIO_FN_STMDATA3_2, + GPIO_FN_STMCLK_2, + GPIO_FN_STMSIDI_2, + + /* Port295 */ + GPIO_FN_SDHID2_0, + GPIO_FN_MSIOF4_TXD, + GPIO_FN_SCIFB2_TXD_295, + GPIO_FN_MSIOF6_TXD, + + /* Port296 */ + GPIO_FN_SDHID2_1, + GPIO_FN_MSIOF6_SS2, + GPIO_FN_IRQ52, + + /* Port297 - Port300 FN1 */ + GPIO_FN_SDHID2_2, + GPIO_FN_SDHID2_3, + GPIO_FN_SDHICLK2, + GPIO_FN_SDHICMD2, + + /* Port297 - Port300 FN2 */ + GPIO_FN_MSIOF4_RXD, + GPIO_FN_MSIOF4_SYNC, + GPIO_FN_MSIOF4_SCK, + GPIO_FN_MSIOF4_SS1, + + /* Port297 - Port300 FN3 */ + GPIO_FN_SCIFB2_RXD_297, + GPIO_FN_SCIFB2_CTS_298, + GPIO_FN_SCIFB2_SCK_299, + GPIO_FN_SCIFB2_RTS_300, + + /* Port297 - Port300 FN4 */ + GPIO_FN_MSIOF6_RXD, + GPIO_FN_MSIOF6_SYNC, + GPIO_FN_MSIOF6_SCK, + GPIO_FN_MSIOF6_SS1, + + /* Port301 */ + GPIO_FN_SDHICD0, + GPIO_FN_IRQ50, + + /* Port302 - Port306 FN1 */ + GPIO_FN_SDHID0_0, + GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, + GPIO_FN_SDHID0_3, + GPIO_FN_SDHICMD0, + + /* Port302 - Port306 FN3 */ + GPIO_FN_STMDATA0_1, + GPIO_FN_STMDATA1_1, + GPIO_FN_STMDATA2_1, + GPIO_FN_STMDATA3_1, + GPIO_FN_STMSIDI_1, + + /* Port307 */ + GPIO_FN_SDHIWP0, + + /* Port308 */ + GPIO_FN_SDHICLK0, + GPIO_FN_STMCLK_1, + + /* Port320 - Port329 */ + GPIO_FN_IRQ16, + GPIO_FN_IRQ17, + GPIO_FN_IRQ28, + GPIO_FN_IRQ29, + GPIO_FN_IRQ30, + GPIO_FN_IRQ53, + GPIO_FN_IRQ54, + GPIO_FN_IRQ55, + GPIO_FN_IRQ56, + GPIO_FN_IRQ57, +}; + void r8a73a4_add_standard_devices(void); void r8a73a4_clock_init(void); void r8a73a4_pinmux_init(void); diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index af16f8f6ab6c..0e1f99c33d47 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -22,6 +22,11 @@ config GPIO_SH_PFC This enables support for GPIOs within the SoC's pin function controller. +config PINCTRL_PFC_R8A73A4 + def_bool y + depends on ARCH_R8A73A4 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7740 def_bool y depends on ARCH_R8A7740 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index e8b9562c47e1..211cd8e98a8a 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y) sh-pfc-objs += gpio.o endif obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o +obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index ced9a95aa1fc..b551336924a5 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -418,6 +418,9 @@ static int sh_pfc_remove(struct platform_device *pdev) } static const struct platform_device_id sh_pfc_id_table[] = { +#ifdef CONFIG_PINCTRL_PFC_R8A73A4 + { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7740 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, #endif diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 763d717ca979..89cb4289d761 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -54,6 +54,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); +extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c new file mode 100644 index 000000000000..47d75d5548eb --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -0,0 +1,2826 @@ +/* + * Copyright (C) 2012-2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Kuninori Morimoto + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include + +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + /* Port0 - Port30 */ \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##30, sfx), \ + /* Port32 - Port40 */ \ + PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \ + PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \ + PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \ + PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \ + PORT_1(fn, pfx##40, sfx), \ + /* Port64 - Port85 */ \ + PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \ + PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \ + PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \ + PORT_10(fn, pfx##7, sfx), \ + PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \ + PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \ + PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \ + /* Port96 - Port126 */ \ + PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \ + PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \ + PORT_10(fn, pfx##10, sfx), \ + PORT_10(fn, pfx##11, sfx), \ + PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \ + PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \ + PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \ + PORT_1(fn, pfx##126, sfx), \ + /* Port128 - Port134 */ \ + PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ + PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \ + PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \ + PORT_1(fn, pfx##134, sfx), \ + /* Port160 - Port178 */ \ + PORT_10(fn, pfx##16, sfx), \ + PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \ + PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \ + PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \ + PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \ + PORT_1(fn, pfx##178, sfx), \ + /* Port192 - Port222 */ \ + PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ + PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ + PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ + PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ + PORT_10(fn, pfx##20, sfx), \ + PORT_10(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \ + PORT_1(fn, pfx##222, sfx), \ + /* Port224 - Port250 */ \ + PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \ + PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \ + PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \ + PORT_10(fn, pfx##23, sfx), \ + PORT_10(fn, pfx##24, sfx), \ + PORT_1(fn, pfx##250, sfx), \ + /* Port256 - Port283 */ \ + PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \ + PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \ + PORT_10(fn, pfx##26, sfx), \ + PORT_10(fn, pfx##27, sfx), \ + PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ + PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \ + /* Port288 - Port308 */ \ + PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ + PORT_10(fn, pfx##29, sfx), \ + PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \ + PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \ + PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \ + PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \ + PORT_1(fn, pfx##308, sfx), \ + /* Port320 - Port329 */ \ + PORT_10(fn, pfx##32, sfx) + + +enum { + PINMUX_RESERVED = 0, + + /* PORT0_DATA -> PORT329_DATA */ + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), + PINMUX_DATA_END, + + /* PORT0_IN -> PORT329_IN */ + PINMUX_INPUT_BEGIN, + PORT_ALL(IN), + PINMUX_INPUT_END, + + /* PORT0_IN_PU -> PORT329_IN_PU */ + PINMUX_INPUT_PULLUP_BEGIN, + PORT_ALL(IN_PU), + PINMUX_INPUT_PULLUP_END, + + /* PORT0_IN_PD -> PORT329_IN_PD */ + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_ALL(IN_PD), + PINMUX_INPUT_PULLDOWN_END, + + /* PORT0_OUT -> PORT329_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */ + PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */ + PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */ + PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */ + PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */ + PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */ + PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */ + PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */ + PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */ + PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */ + + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_25_0, MSEL1CR_25_1, + MSEL1CR_24_0, MSEL1CR_24_1, + MSEL1CR_22_0, MSEL1CR_22_1, + MSEL1CR_21_0, MSEL1CR_21_1, + MSEL1CR_20_0, MSEL1CR_20_1, + MSEL1CR_19_0, MSEL1CR_19_1, + MSEL1CR_18_0, MSEL1CR_18_1, + MSEL1CR_17_0, MSEL1CR_17_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_11_0, MSEL1CR_11_1, + MSEL1CR_10_0, MSEL1CR_10_1, + MSEL1CR_09_0, MSEL1CR_09_1, + MSEL1CR_08_0, MSEL1CR_08_1, + MSEL1CR_07_0, MSEL1CR_07_1, + MSEL1CR_06_0, MSEL1CR_06_1, + MSEL1CR_05_0, MSEL1CR_05_1, + MSEL1CR_04_0, MSEL1CR_04_1, + MSEL1CR_03_0, MSEL1CR_03_1, + MSEL1CR_02_0, MSEL1CR_02_1, + MSEL1CR_01_0, MSEL1CR_01_1, + MSEL1CR_00_0, MSEL1CR_00_1, + + MSEL3CR_31_0, MSEL3CR_31_1, + MSEL3CR_28_0, MSEL3CR_28_1, + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + MSEL3CR_23_0, MSEL3CR_23_1, + MSEL3CR_22_0, MSEL3CR_22_1, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + MSEL3CR_19_0, MSEL3CR_19_1, + MSEL3CR_18_0, MSEL3CR_18_1, + MSEL3CR_17_0, MSEL3CR_17_1, + MSEL3CR_16_0, MSEL3CR_16_1, + MSEL3CR_15_0, MSEL3CR_15_1, + MSEL3CR_12_0, MSEL3CR_12_1, + MSEL3CR_11_0, MSEL3CR_11_1, + MSEL3CR_10_0, MSEL3CR_10_1, + MSEL3CR_09_0, MSEL3CR_09_1, + MSEL3CR_06_0, MSEL3CR_06_1, + MSEL3CR_03_0, MSEL3CR_03_1, + MSEL3CR_01_0, MSEL3CR_01_1, + MSEL3CR_00_0, MSEL3CR_00_1, + + MSEL4CR_30_0, MSEL4CR_30_1, + MSEL4CR_29_0, MSEL4CR_29_1, + MSEL4CR_28_0, MSEL4CR_28_1, + MSEL4CR_27_0, MSEL4CR_27_1, + MSEL4CR_26_0, MSEL4CR_26_1, + MSEL4CR_25_0, MSEL4CR_25_1, + MSEL4CR_24_0, MSEL4CR_24_1, + MSEL4CR_23_0, MSEL4CR_23_1, + MSEL4CR_22_0, MSEL4CR_22_1, + MSEL4CR_21_0, MSEL4CR_21_1, + MSEL4CR_20_0, MSEL4CR_20_1, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + MSEL4CR_13_0, MSEL4CR_13_1, + MSEL4CR_12_0, MSEL4CR_12_1, + MSEL4CR_11_0, MSEL4CR_11_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_09_0, MSEL4CR_09_1, + MSEL4CR_07_0, MSEL4CR_07_1, + MSEL4CR_04_0, MSEL4CR_04_1, + MSEL4CR_01_0, MSEL4CR_01_1, + + MSEL5CR_31_0, MSEL5CR_31_1, + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + MSEL5CR_28_0, MSEL5CR_28_1, + MSEL5CR_27_0, MSEL5CR_27_1, + MSEL5CR_26_0, MSEL5CR_26_1, + MSEL5CR_25_0, MSEL5CR_25_1, + MSEL5CR_24_0, MSEL5CR_24_1, + MSEL5CR_23_0, MSEL5CR_23_1, + MSEL5CR_22_0, MSEL5CR_22_1, + MSEL5CR_21_0, MSEL5CR_21_1, + MSEL5CR_20_0, MSEL5CR_20_1, + MSEL5CR_19_0, MSEL5CR_19_1, + MSEL5CR_18_0, MSEL5CR_18_1, + MSEL5CR_17_0, MSEL5CR_17_1, + MSEL5CR_16_0, MSEL5CR_16_1, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + MSEL5CR_09_0, MSEL5CR_09_1, + MSEL5CR_08_0, MSEL5CR_08_1, + MSEL5CR_07_0, MSEL5CR_07_1, + MSEL5CR_06_0, MSEL5CR_06_1, + + MSEL8CR_16_0, MSEL8CR_16_1, + MSEL8CR_01_0, MSEL8CR_01_1, + MSEL8CR_00_0, MSEL8CR_00_1, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + +#define F1(a) a##_MARK +#define F2(a) a##_MARK +#define F3(a) a##_MARK +#define F4(a) a##_MARK +#define F5(a) a##_MARK +#define F6(a) a##_MARK +#define F7(a) a##_MARK +#define IRQ(a) IRQ##a##_MARK + + F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */ + F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1), + F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2), + F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3), + F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4), + F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5), + F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6), + F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7), + F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8), + F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9), + F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */ + F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11), + F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12), + F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13), + F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14), + F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15), + F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0), + F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1), + F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2), + F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3), + F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */ + F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5), + F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6), + F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7), + F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24), + F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N), + F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N), + F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN), + F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT), + F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB), + F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE), + F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */ + + F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */ + F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS), + F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK), + F1(SCIFA1_RTS), F7(CSCIF1_RTS), + F1(SCIFA1_CTS), F7(CSCIF1_CTS), + F1(SCIFA1_SCK), F7(CSCIF1_SCK), + F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS), + F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS), + F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40), + F7(CHSCIF0_HSCK), /* Port40 */ + + F1(PDM0_DATA), /* Port64 */ + F1(PDM1_DATA), + F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4), + IRQ(40), + F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX), + F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68), + F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69), + F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0), + F7(CHSCIF1_HRTS), /* Port70 */ + F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1), + F7(CHSCIF1_HCTS), + F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX), + F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73), + F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0), + F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */ + F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */ + + F1(KEYIN0), /* Port96 */ + F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */ + F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42), + F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3), + F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */ + F2(KEYOUT7), F5(RFANAEN), IRQ(45), + F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46), + F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47), + F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48), + F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49), + F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX), + F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX), + F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */ + F3(SF_PORT_0_121), F4(SCIFB3_TXD_121), + F1(SCIFB0_TXD), F7(CHSCIF0_HTX), + F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124), + F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0), + F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1), + F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC), + F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1), + F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD), + F5(SIM0_VOLTSEL1), /* Port130 */ + F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK), + F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK), + F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1), + IRQ(20), /* Port160 */ + IRQ(21), IRQ(22), IRQ(23), + F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3), + F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */ + F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST), + IRQ(24), IRQ(25), IRQ(26), IRQ(27), + F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */ + F1(A9), F2(MMCD1_6), IRQ(32), + F1(A8), F2(MMCD1_5), IRQ(33), + F1(A7), F2(MMCD1_4), IRQ(34), + F1(A6), F2(MMCD1_3), IRQ(35), + F1(A5), F2(MMCD1_2), IRQ(36), + F1(A4), F2(MMCD1_1), IRQ(37), + F1(A3), F2(MMCD1_0), IRQ(38), + F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */ + F1(A1), + F1(A0), F2(BS), + F1(CKO), F2(MMCCLK1), + F1(CS0_N), F5(SIM0_GPO1), + F1(CS2_N), F5(SIM0_GPO2), + F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0), + F1(D15), F5(GIO_OUT15), + F1(D14), F5(GIO_OUT14), + F1(D13), F5(GIO_OUT13), + F1(D12), F5(GIO_OUT12), /* Port210 */ + F1(D11), F5(WGM_TXP2), + F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK), + F1(D9), F2(VIO_D9), F5(GIO_OUT9), + F1(D8), F2(VIO_D8), F5(GIO_OUT8), + F1(D7), F2(VIO_D7), F5(GIO_OUT7), + F1(D6), F2(VIO_D6), F5(GIO_OUT6), + F1(D5), F2(VIO_D5), F5(GIO_OUT5_217), + F1(D4), F2(VIO_D4), F5(GIO_OUT4_218), + F1(D3), F2(VIO_D3), F5(GIO_OUT3_219), + F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */ + F1(D1), F2(VIO_D1), F5(GIO_OUT1_221), + F1(D0), F2(VIO_D0), F5(GIO_OUT0_222), + F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2), + F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1), + F1(WE0_N), F2(RDWR_227), + F1(WE1_N), F5(SIM0_GPO0), + F1(PWMO), F2(VIO_CKO1_229), + F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */ + F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232), + F2(VIO_CKO3_233), F4(SF_PORT_1_233), + F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234), + F1(FSIAISLD), F2(PDM3_DATA_235), + F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236), + F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT), + F1(FSIAOSLD), F2(PDM0_OUTDATA_239), + F1(FSIBISLD), /* Port240 */ + F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242), + F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF), + F1(FSIBCK), F3(ISP_SHUTTER0_245), + F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248), + F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */ + F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2), + F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */ + F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262), + F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD), + F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1), + F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK), + F1(MSIOF1_SYNC), F4(MSIOF5_SYNC), + F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */ + F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272), + F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0), + F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP), + F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */ + F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282), + F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2), + F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */ + F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2), + F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2), + F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD), + F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52), + F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD), + F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC), + F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK), + F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300), + F4(MSIOF6_SS1), /* Port300 */ + F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1), + F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1), + F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1), + F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */ + IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54), + IRQ(55), IRQ(56), IRQ(57), + PINMUX_MARK_END, +}; + +static const pinmux_enum_t pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + + PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1), + PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3), + PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5), + PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7), + PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9), + + PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11), + PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13), + PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15), + PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17), + PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19), + + PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21), + PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23), + PORT_DATA_IO_PU_PD(24), PORT_DATA_IO_PU_PD(25), + PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27), + PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29), + + PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32), + PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34), + PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36), + PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38), + PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40), + + PORT_DATA_IO_PU_PD(64), PORT_DATA_IO_PU_PD(65), + PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), + + PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), + PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75), + PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), + PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), + + PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), + PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83), + PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85), + + PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), + PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), + + PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101), + PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103), + PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105), + PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107), + PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109), + + PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111), + PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113), + PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115), + PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117), + PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119), + + PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121), + PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123), + PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125), + PORT_DATA_IO_PU_PD(126), + PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129), + + PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131), + PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133), + PORT_DATA_IO_PU_PD(134), + + PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161), + PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163), + PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165), + PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167), + PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169), + + PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171), + PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173), + PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175), + PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177), + PORT_DATA_IO_PU_PD(178), + + PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193), + PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195), + PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197), + PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), + + PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201), + PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203), + PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), + PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209), + + PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211), + PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213), + PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215), + PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217), + PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219), + + PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221), + PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224), + PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226), + PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228), + PORT_DATA_IO_PU_PD(229), + + PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231), + PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233), + PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235), + PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237), + PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239), + + PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241), + PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243), + PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245), + PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247), + PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249), + + PORT_DATA_IO_PU_PD(250), + PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257), + PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259), + + PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261), + PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263), + PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265), + PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267), + PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269), + + PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271), + PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273), + PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275), + PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277), + PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279), + + PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281), + PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283), + PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289), + + PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291), + PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293), + PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295), + PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297), + PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299), + + PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301), + PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303), + PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305), + PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307), + PORT_DATA_IO_PU_PD(308), + + PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321), + PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323), + PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325), + PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327), + PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329), + + /* Port0 */ + PINMUX_DATA(LCDD0_MARK, PORT0_FN1), + PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3), + PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7), + PINMUX_DATA(IRQ0_MARK, PORT0_FN0), + + /* Port1 */ + PINMUX_DATA(LCDD1_MARK, PORT1_FN1), + PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0), + PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7), + PINMUX_DATA(IRQ1_MARK, PORT1_FN0), + + /* Port2 */ + PINMUX_DATA(LCDD2_MARK, PORT2_FN1), + PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3), + PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7), + PINMUX_DATA(IRQ2_MARK, PORT2_FN0), + + /* Port3 */ + PINMUX_DATA(LCDD3_MARK, PORT3_FN1), + PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0), + PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7), + PINMUX_DATA(IRQ3_MARK, PORT3_FN0), + + /* Port4 */ + PINMUX_DATA(LCDD4_MARK, PORT4_FN1), + PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3), + PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7), + PINMUX_DATA(IRQ4_MARK, PORT4_FN0), + + /* Port5 */ + PINMUX_DATA(LCDD5_MARK, PORT5_FN1), + PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0), + PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7), + PINMUX_DATA(IRQ5_MARK, PORT5_FN0), + + /* Port6 */ + PINMUX_DATA(LCDD6_MARK, PORT6_FN1), + PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3), + PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7), + PINMUX_DATA(IRQ6_MARK, PORT6_FN0), + + /* Port7 */ + PINMUX_DATA(LCDD7_MARK, PORT7_FN1), + PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3), + PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7), + PINMUX_DATA(IRQ7_MARK, PORT7_FN0), + + /* Port8 */ + PINMUX_DATA(LCDD8_MARK, PORT8_FN1), + PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3), + PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7), + PINMUX_DATA(IRQ8_MARK, PORT8_FN0), + + /* Port9 */ + PINMUX_DATA(LCDD9_MARK, PORT9_FN1), + PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3), + PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7), + PINMUX_DATA(IRQ9_MARK, PORT9_FN0), + + /* Port10 */ + PINMUX_DATA(LCDD10_MARK, PORT10_FN1), + PINMUX_DATA(FSICCK_MARK, PORT10_FN3), + PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7), + PINMUX_DATA(IRQ10_MARK, PORT10_FN0), + + /* Port11 */ + PINMUX_DATA(LCDD11_MARK, PORT11_FN1), + PINMUX_DATA(FSICISLD_MARK, PORT11_FN3), + PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7), + PINMUX_DATA(IRQ11_MARK, PORT11_FN0), + + /* Port12 */ + PINMUX_DATA(LCDD12_MARK, PORT12_FN1), + PINMUX_DATA(FSICOMC_MARK, PORT12_FN3), + PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7), + PINMUX_DATA(IRQ12_MARK, PORT12_FN0), + + /* Port13 */ + PINMUX_DATA(LCDD13_MARK, PORT13_FN1), + PINMUX_DATA(FSICOLR_MARK, PORT13_FN3), + PINMUX_DATA(FSICILR_MARK, PORT13_FN4), + PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7), + PINMUX_DATA(IRQ13_MARK, PORT13_FN0), + + /* Port14 */ + PINMUX_DATA(LCDD14_MARK, PORT14_FN1), + PINMUX_DATA(FSICOBT_MARK, PORT14_FN3), + PINMUX_DATA(FSICIBT_MARK, PORT14_FN4), + PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7), + PINMUX_DATA(IRQ14_MARK, PORT14_FN0), + + /* Port15 */ + PINMUX_DATA(LCDD15_MARK, PORT15_FN1), + PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3), + PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7), + PINMUX_DATA(IRQ15_MARK, PORT15_FN0), + + /* Port16 */ + PINMUX_DATA(LCDD16_MARK, PORT16_FN1), + PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4), + PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7), + + /* Port17 */ + PINMUX_DATA(LCDD17_MARK, PORT17_FN1), + PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4), + PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7), + + /* Port18 */ + PINMUX_DATA(LCDD18_MARK, PORT18_FN1), + PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4), + PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7), + + /* Port19 */ + PINMUX_DATA(LCDD19_MARK, PORT19_FN1), + PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3), + PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7), + + /* Port20 */ + PINMUX_DATA(LCDD20_MARK, PORT20_FN1), + PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0), + PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7), + + /* Port21 */ + PINMUX_DATA(LCDD21_MARK, PORT21_FN1), + PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0), + PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7), + + /* Port22 */ + PINMUX_DATA(LCDD22_MARK, PORT22_FN1), + PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0), + PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7), + + /* Port23 */ + PINMUX_DATA(LCDD23_MARK, PORT23_FN1), + PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3), + PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7), + + /* Port24 */ + PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1), + PINMUX_DATA(LCDCS_MARK, PORT24_FN2), + PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3), + PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7), + + /* Port25 */ + PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1), + PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0), + PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7), + + /* Port26 */ + PINMUX_DATA(LCDDCK_MARK, PORT26_FN1), + PINMUX_DATA(LCDWR_MARK, PORT26_FN2), + PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0), + PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7), + + /* Port27 */ + PINMUX_DATA(LCDDISP_MARK, PORT27_FN1), + PINMUX_DATA(LCDRS_MARK, PORT27_FN2), + PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0), + PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7), + + /* Port28 */ + PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1), + PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3), + PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7), + + /* Port29 */ + PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1), + PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4), + PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7), + + /* Port30 */ + PINMUX_DATA(LCDDON_MARK, PORT30_FN1), + PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4), + PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7), + + /* Port32 */ + PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1), + PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5), + PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7), + + /* Port33 */ + PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1), + PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5), + PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7), + + /* Port34 */ + PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1), + PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5), + PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7), + + /* Port35 */ + PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1), + PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7), + + /* Port36 */ + PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1), + PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7), + + /* Port37 */ + PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1), + PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7), + + /* Port38 */ + PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1), + PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3), + PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4), + PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7), + + /* Port39 */ + PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1), + PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3), + PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1), + PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7), + + /* Port40 */ + PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1), + PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3), + PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4), + PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7), + + /* Port64 */ + PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1), + + /* Port65 */ + PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1), + + /* Port66 */ + PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1), + PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0), + PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3), + PINMUX_DATA(GenIO4_MARK, PORT66_FN5), + PINMUX_DATA(IRQ40_MARK, PORT66_FN0), + + /* Port67 */ + PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1), + PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1), + PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5), + PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7), + + /* Port68 */ + PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1), + PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0), + PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3), + PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5), + + /* Port69 */ + PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1), + PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0), + PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3), + PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5), + + /* Port70 */ + PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1), + PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2), + PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5), + PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6), + PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7), + + /* Port71 */ + PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1), + PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1), + PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5), + PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6), + PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7), + + /* Port72 */ + PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1), + PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1), + PINMUX_DATA(GenIO8_MARK, PORT72_FN5), + PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7), + + /* Port73 */ + PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1), + PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2), + PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3), + PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5), + + /* Port74 - Port85 */ + PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1), + PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1), + PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1), + PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1), + PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1), + PINMUX_DATA(TXP_MARK, PORT80_FN1), + PINMUX_DATA(TXP2_MARK, PORT81_FN1), + PINMUX_DATA(COEX_0_MARK, PORT82_FN1), + PINMUX_DATA(COEX_1_MARK, PORT83_FN1), + PINMUX_DATA(IRQ19_MARK, PORT84_FN0), + PINMUX_DATA(IRQ18_MARK, PORT85_FN0), + + /* Port96 - Port101 */ + PINMUX_DATA(KEYIN0_MARK, PORT96_FN1), + PINMUX_DATA(KEYIN1_MARK, PORT97_FN1), + PINMUX_DATA(KEYIN2_MARK, PORT98_FN1), + PINMUX_DATA(KEYIN3_MARK, PORT99_FN1), + PINMUX_DATA(KEYIN4_MARK, PORT100_FN1), + PINMUX_DATA(KEYIN5_MARK, PORT101_FN1), + + /* Port102 */ + PINMUX_DATA(KEYIN6_MARK, PORT102_FN1), + PINMUX_DATA(IRQ41_MARK, PORT102_FN0), + + /* Port103 */ + PINMUX_DATA(KEYIN7_MARK, PORT103_FN1), + PINMUX_DATA(IRQ42_MARK, PORT103_FN0), + + /* Port104 - Port108 */ + PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2), + PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2), + PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2), + PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2), + PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2), + + /* Port109 */ + PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2), + PINMUX_DATA(IRQ43_MARK, PORT109_FN0), + + /* Port110 */ + PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2), + PINMUX_DATA(IRQ44_MARK, PORT110_FN0), + + /* Port111 */ + PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2), + PINMUX_DATA(RFANAEN_MARK, PORT111_FN5), + PINMUX_DATA(IRQ45_MARK, PORT111_FN0), + + /* Port112 */ + PINMUX_DATA(KEYIN8_MARK, PORT112_FN1), + PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2), + PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4), + PINMUX_DATA(IRQ46_MARK, PORT112_FN0), + + /* Port113 */ + PINMUX_DATA(KEYIN9_MARK, PORT113_FN1), + PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2), + PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4), + PINMUX_DATA(IRQ47_MARK, PORT113_FN0), + + /* Port114 */ + PINMUX_DATA(KEYIN10_MARK, PORT114_FN1), + PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2), + PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4), + PINMUX_DATA(IRQ48_MARK, PORT114_FN0), + + /* Port115 */ + PINMUX_DATA(KEYIN11_MARK, PORT115_FN1), + PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2), + PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4), + PINMUX_DATA(IRQ49_MARK, PORT115_FN0), + + /* Port116 */ + PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1), + PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7), + + /* Port117 */ + PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1), + PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7), + + /* Port118 */ + PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1), + PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7), + + /* Port119 */ + PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1), + PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7), + + /* Port120 */ + PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3), + PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1), + PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7), + + /* Port121 */ + PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3), + PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1), + + /* Port122 */ + PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1), + PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7), + + /* Port123 */ + PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1), + PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7), + + /* Port124 */ + PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3), + + /* Port125 */ + PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1), + PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2), + PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3), + PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5), + + /* Port126 */ + PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1), + PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2), + PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3), + + /* Port128 */ + PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1), + PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2), + PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3), + PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5), + + /* Port129 */ + PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1), + PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2), + PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3), + + /* Port130 */ + PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1), + PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1), + PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3), + PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5), + + /* Port131 */ + PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1), + PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5), + + /* Port132 */ + PINMUX_DATA(TS_SCK_MARK, PORT132_FN1), + PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2), + PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3), + + /* Port133 */ + PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1), + PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2), + PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3), + PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5), + + /* Port134 */ + PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1), + PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2), + PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3), + + /* Port160 - Port178 */ + PINMUX_DATA(IRQ20_MARK, PORT160_FN0), + PINMUX_DATA(IRQ21_MARK, PORT161_FN0), + PINMUX_DATA(IRQ22_MARK, PORT162_FN0), + PINMUX_DATA(IRQ23_MARK, PORT163_FN0), + PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1), + PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1), + PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1), + PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1), + PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1), + PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1), + PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1), + PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1), + PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1), + PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1), + PINMUX_DATA(MMCRST_MARK, PORT174_FN1), + PINMUX_DATA(IRQ24_MARK, PORT175_FN0), + PINMUX_DATA(IRQ25_MARK, PORT176_FN0), + PINMUX_DATA(IRQ26_MARK, PORT177_FN0), + PINMUX_DATA(IRQ27_MARK, PORT178_FN0), + + /* Port192 - Port200 FN1 */ + PINMUX_DATA(A10_MARK, PORT192_FN1), + PINMUX_DATA(A9_MARK, PORT193_FN1), + PINMUX_DATA(A8_MARK, PORT194_FN1), + PINMUX_DATA(A7_MARK, PORT195_FN1), + PINMUX_DATA(A6_MARK, PORT196_FN1), + PINMUX_DATA(A5_MARK, PORT197_FN1), + PINMUX_DATA(A4_MARK, PORT198_FN1), + PINMUX_DATA(A3_MARK, PORT199_FN1), + PINMUX_DATA(A2_MARK, PORT200_FN1), + + /* Port192 - Port200 FN2 */ + PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2), + PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2), + PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2), + PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2), + PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2), + PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2), + PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2), + PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2), + PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2), + + /* Port192 - Port200 IRQ */ + PINMUX_DATA(IRQ31_MARK, PORT192_FN0), + PINMUX_DATA(IRQ32_MARK, PORT193_FN0), + PINMUX_DATA(IRQ33_MARK, PORT194_FN0), + PINMUX_DATA(IRQ34_MARK, PORT195_FN0), + PINMUX_DATA(IRQ35_MARK, PORT196_FN0), + PINMUX_DATA(IRQ36_MARK, PORT197_FN0), + PINMUX_DATA(IRQ37_MARK, PORT198_FN0), + PINMUX_DATA(IRQ38_MARK, PORT199_FN0), + PINMUX_DATA(IRQ39_MARK, PORT200_FN0), + + /* Port201 */ + PINMUX_DATA(A1_MARK, PORT201_FN1), + + /* Port202 */ + PINMUX_DATA(A0_MARK, PORT202_FN1), + PINMUX_DATA(BS_MARK, PORT202_FN2), + + /* Port203 */ + PINMUX_DATA(CKO_MARK, PORT203_FN1), + PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2), + + /* Port204 */ + PINMUX_DATA(CS0_N_MARK, PORT204_FN1), + PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5), + + /* Port205 */ + PINMUX_DATA(CS2_N_MARK, PORT205_FN1), + PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5), + + /* Port206 */ + PINMUX_DATA(CS4_N_MARK, PORT206_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT206_FN2), + PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5), + + /* Port207 - Port212 FN1 */ + PINMUX_DATA(D15_MARK, PORT207_FN1), + PINMUX_DATA(D14_MARK, PORT208_FN1), + PINMUX_DATA(D13_MARK, PORT209_FN1), + PINMUX_DATA(D12_MARK, PORT210_FN1), + PINMUX_DATA(D11_MARK, PORT211_FN1), + PINMUX_DATA(D10_MARK, PORT212_FN1), + + /* Port207 - Port212 FN5 */ + PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5), + PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5), + PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5), + PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5), + PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5), + PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5), + + /* Port213 - Port222 FN1 */ + PINMUX_DATA(D9_MARK, PORT213_FN1), + PINMUX_DATA(D8_MARK, PORT214_FN1), + PINMUX_DATA(D7_MARK, PORT215_FN1), + PINMUX_DATA(D6_MARK, PORT216_FN1), + PINMUX_DATA(D5_MARK, PORT217_FN1), + PINMUX_DATA(D4_MARK, PORT218_FN1), + PINMUX_DATA(D3_MARK, PORT219_FN1), + PINMUX_DATA(D2_MARK, PORT220_FN1), + PINMUX_DATA(D1_MARK, PORT221_FN1), + PINMUX_DATA(D0_MARK, PORT222_FN1), + + /* Port213 - Port222 FN2 */ + PINMUX_DATA(VIO_D9_MARK, PORT213_FN2), + PINMUX_DATA(VIO_D8_MARK, PORT214_FN2), + PINMUX_DATA(VIO_D7_MARK, PORT215_FN2), + PINMUX_DATA(VIO_D6_MARK, PORT216_FN2), + PINMUX_DATA(VIO_D5_MARK, PORT217_FN2), + PINMUX_DATA(VIO_D4_MARK, PORT218_FN2), + PINMUX_DATA(VIO_D3_MARK, PORT219_FN2), + PINMUX_DATA(VIO_D2_MARK, PORT220_FN2), + PINMUX_DATA(VIO_D1_MARK, PORT221_FN2), + PINMUX_DATA(VIO_D0_MARK, PORT222_FN2), + + /* Port213 - Port222 FN5 */ + PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5), + PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5), + PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5), + PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5), + PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5), + PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5), + PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5), + PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5), + PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5), + PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5), + + /* Port224 */ + PINMUX_DATA(RDWR_224_MARK, PORT224_FN1), + PINMUX_DATA(VIO_HD_MARK, PORT224_FN2), + PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5), + + /* Port225 */ + PINMUX_DATA(RD_N_MARK, PORT225_FN1), + + /* Port226 */ + PINMUX_DATA(WAIT_N_MARK, PORT226_FN1), + PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2), + PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5), + + /* Port227 */ + PINMUX_DATA(WE0_N_MARK, PORT227_FN1), + PINMUX_DATA(RDWR_227_MARK, PORT227_FN2), + + /* Port228 */ + PINMUX_DATA(WE1_N_MARK, PORT228_FN1), + PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5), + + /* Port229 */ + PINMUX_DATA(PWMO_MARK, PORT229_FN1), + PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2), + + /* Port230 */ + PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1), + PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2), + + /* Port231 */ + PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1), + PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2), + + /* Port232 */ + PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2), + PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4), + + /* Port233 */ + PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2), + PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4), + + /* Port234 */ + PINMUX_DATA(FSIACK_MARK, PORT234_FN1), + PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2), + PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3), + + /* Port235 */ + PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1), + PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1), + + /* Port236 */ + PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1), + PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2), + PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3), + + /* Port237 */ + PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1), + PINMUX_DATA(FSIAILR_MARK, PORT237_FN2), + + /* Port238 */ + PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1), + PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2), + + /* Port239 */ + PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1), + PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2), + + /* Port240 */ + PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1), + + /* Port241 */ + PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1), + PINMUX_DATA(FSIBILR_MARK, PORT241_FN2), + + /* Port242 */ + PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1), + PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3), + + /* Port243 */ + PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1), + PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2), + + /* Port244 */ + PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1), + PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2), + + /* Port245 */ + PINMUX_DATA(FSIBCK_MARK, PORT245_FN1), + PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3), + + /* Port246 - Port250 FN1 */ + PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1), + PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1), + PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1), + PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1), + PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1), + + /* Port256 - Port258 */ + PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1), + PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1), + + /* Port259 */ + PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1), + PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3), + + /* Port260 */ + PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1), + + /* Port261 */ + PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2), + PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7), + + /* Port262 */ + PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2), + + /* Port263 - Port266 FN1 */ + PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1), + + /* Port263 - Port266 FN4 */ + PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4), + PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4), + PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4), + PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4), + + /* Port267 */ + PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1), + + /* Port268 */ + PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1), + PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4), + + /* Port269 */ + PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1), + PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4), + + /* Port270 - Port273 FN1 */ + PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1), + PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1), + PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1), + PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1), + + /* Port270 - Port273 FN3 */ + PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3), + PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3), + PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3), + PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3), + + /* Port274 */ + PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1), + PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4), + + /* Port275 - Port280 */ + PINMUX_DATA(IC_DP_MARK, PORT275_FN1), + PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1), + PINMUX_DATA(IC_DM_MARK, PORT277_FN1), + PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1), + PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1), + PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1), + + /* Port281 */ + PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1), + PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1), + + /* Port282 */ + PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1), + PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2), + + /* Port283 */ + PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1), + + /* Port289 */ + PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1), + PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3), + + /* Port290 */ + PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1), + PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3), + PINMUX_DATA(IRQ51_MARK, PORT290_FN0), + + /* Port291 - Port294 FN1 */ + PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1), + PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1), + PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1), + PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1), + + /* Port291 - Port294 FN3 */ + PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3), + PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3), + PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3), + PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3), + + /* Port295 */ + PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1), + PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2), + PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1), + PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4), + + /* Port296 */ + PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1), + PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4), + PINMUX_DATA(IRQ52_MARK, PORT296_FN0), + + /* Port297 - Port300 FN1 */ + PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1), + PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1), + PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1), + PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1), + + /* Port297 - Port300 FN2 */ + PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2), + PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2), + PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2), + PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2), + + /* Port297 - Port300 FN3 */ + PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1), + PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1), + PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3), + PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3), + + /* Port297 - Port300 FN4 */ + PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4), + PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4), + PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4), + PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4), + + /* Port301 */ + PINMUX_DATA(SDHICD0_MARK, PORT301_FN1), + PINMUX_DATA(IRQ50_MARK, PORT301_FN0), + + /* Port302 - Port306 FN1 */ + PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1), + PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1), + PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1), + PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1), + PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1), + + /* Port302 - Port306 FN3 */ + PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3), + PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3), + PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3), + PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3), + PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3), + + /* Port307 */ + PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1), + + /* Port308 */ + PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1), + PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3), + + /* Port320 - Port329 */ + PINMUX_DATA(IRQ16_MARK, PORT320_FN0), + PINMUX_DATA(IRQ17_MARK, PORT321_FN0), + PINMUX_DATA(IRQ28_MARK, PORT322_FN0), + PINMUX_DATA(IRQ29_MARK, PORT323_FN0), + PINMUX_DATA(IRQ30_MARK, PORT324_FN0), + PINMUX_DATA(IRQ53_MARK, PORT325_FN0), + PINMUX_DATA(IRQ54_MARK, PORT326_FN0), + PINMUX_DATA(IRQ55_MARK, PORT327_FN0), + PINMUX_DATA(IRQ56_MARK, PORT328_FN0), + PINMUX_DATA(IRQ57_MARK, PORT329_FN0), +}; + +static struct sh_pfc_pin pinmux_pins[] = { + GPIO_PORT_ALL(), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + +static const struct pinmux_func pinmux_func_gpios[] = { + /* Port0 */ + GPIO_FN(LCDD0), + GPIO_FN(PDM2_CLK_0), + GPIO_FN(DU0_DR0), + GPIO_FN(IRQ0), + + /* Port1 */ + GPIO_FN(LCDD1), + GPIO_FN(PDM2_DATA_1), + GPIO_FN(DU0_DR19), + GPIO_FN(IRQ1), + + /* Port2 */ + GPIO_FN(LCDD2), + GPIO_FN(PDM3_CLK_2), + GPIO_FN(DU0_DR2), + GPIO_FN(IRQ2), + + /* Port3 */ + GPIO_FN(LCDD3), + GPIO_FN(PDM3_DATA_3), + GPIO_FN(DU0_DR3), + GPIO_FN(IRQ3), + + /* Port4 */ + GPIO_FN(LCDD4), + GPIO_FN(PDM4_CLK_4), + GPIO_FN(DU0_DR4), + GPIO_FN(IRQ4), + + /* Port5 */ + GPIO_FN(LCDD5), + GPIO_FN(PDM4_DATA_5), + GPIO_FN(DU0_DR5), + GPIO_FN(IRQ5), + + /* Port6 */ + GPIO_FN(LCDD6), + GPIO_FN(PDM0_OUTCLK_6), + GPIO_FN(DU0_DR6), + GPIO_FN(IRQ6), + + /* Port7 */ + GPIO_FN(LCDD7), + GPIO_FN(PDM0_OUTDATA_7), + GPIO_FN(DU0_DR7), + GPIO_FN(IRQ7), + + /* Port8 */ + GPIO_FN(LCDD8), + GPIO_FN(PDM1_OUTCLK_8), + GPIO_FN(DU0_DG0), + GPIO_FN(IRQ8), + + /* Port9 */ + GPIO_FN(LCDD9), + GPIO_FN(PDM1_OUTDATA_9), + GPIO_FN(DU0_DG1), + GPIO_FN(IRQ9), + + /* Port10 */ + GPIO_FN(LCDD10), + GPIO_FN(FSICCK), + GPIO_FN(DU0_DG2), + GPIO_FN(IRQ10), + + /* Port11 */ + GPIO_FN(LCDD11), + GPIO_FN(FSICISLD), + GPIO_FN(DU0_DG3), + GPIO_FN(IRQ11), + + /* Port12 */ + GPIO_FN(LCDD12), + GPIO_FN(FSICOMC), + GPIO_FN(DU0_DG4), + GPIO_FN(IRQ12), + + /* Port13 */ + GPIO_FN(LCDD13), + GPIO_FN(FSICOLR), + GPIO_FN(FSICILR), + GPIO_FN(DU0_DG5), + GPIO_FN(IRQ13), + + /* Port14 */ + GPIO_FN(LCDD14), + GPIO_FN(FSICOBT), + GPIO_FN(FSICIBT), + GPIO_FN(DU0_DG6), + GPIO_FN(IRQ14), + + /* Port15 */ + GPIO_FN(LCDD15), + GPIO_FN(FSICOSLD), + GPIO_FN(DU0_DG7), + GPIO_FN(IRQ15), + + /* Port16 */ + GPIO_FN(LCDD16), + GPIO_FN(TPU1TO1), + GPIO_FN(DU0_DB0), + + /* Port17 */ + GPIO_FN(LCDD17), + GPIO_FN(SF_IRQ_00), + GPIO_FN(DU0_DB1), + + /* Port18 */ + GPIO_FN(LCDD18), + GPIO_FN(SF_IRQ_01), + GPIO_FN(DU0_DB2), + + /* Port19 */ + GPIO_FN(LCDD19), + GPIO_FN(SCIFB3_RTS_19), + GPIO_FN(DU0_DB3), + + /* Port20 */ + GPIO_FN(LCDD20), + GPIO_FN(SCIFB3_CTS_20), + GPIO_FN(DU0_DB4), + + /* Port21 */ + GPIO_FN(LCDD21), + GPIO_FN(SCIFB3_TXD_21), + GPIO_FN(DU0_DB5), + + /* Port22 */ + GPIO_FN(LCDD22), + GPIO_FN(SCIFB3_RXD_22), + GPIO_FN(DU0_DB6), + + /* Port23 */ + GPIO_FN(LCDD23), + GPIO_FN(SCIFB3_SCK_23), + GPIO_FN(DU0_DB7), + + /* Port24 */ + GPIO_FN(LCDHSYN), + GPIO_FN(LCDCS), + GPIO_FN(SCIFB1_RTS_24), + GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N), + + /* Port25 */ + GPIO_FN(LCDVSYN), + GPIO_FN(SCIFB1_CTS_25), + GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N), + + /* Port26 */ + GPIO_FN(LCDDCK), + GPIO_FN(LCDWR), + GPIO_FN(SCIFB1_TXD_26), + GPIO_FN(DU0_DOTCLKIN), + + /* Port27 */ + GPIO_FN(LCDDISP), + GPIO_FN(LCDRS), + GPIO_FN(SCIFB1_RXD_27), + GPIO_FN(DU0_DOTCLKOUT), + + /* Port28 */ + GPIO_FN(LCDRD_N), + GPIO_FN(SCIFB1_SCK_28), + GPIO_FN(DU0_DOTCLKOUTB), + + /* Port29 */ + GPIO_FN(LCDLCLK), + GPIO_FN(SF_IRQ_02), + GPIO_FN(DU0_DISP_CSYNC_N_DE), + + /* Port30 */ + GPIO_FN(LCDDON), + GPIO_FN(SF_IRQ_03), + GPIO_FN(DU0_ODDF_N_CLAMP), + + /* Port32 */ + GPIO_FN(SCIFA0_RTS), + GPIO_FN(SIM0_DET), + GPIO_FN(CSCIF0_RTS), + + /* Port33 */ + GPIO_FN(SCIFA0_CTS), + GPIO_FN(SIM1_DET), + GPIO_FN(CSCIF0_CTS), + + /* Port34 */ + GPIO_FN(SCIFA0_SCK), + GPIO_FN(SIM0_PWRON), + GPIO_FN(CSCIF0_SCK), + + /* Port35 */ + GPIO_FN(SCIFA1_RTS), + GPIO_FN(CSCIF1_RTS), + + /* Port36 */ + GPIO_FN(SCIFA1_CTS), + GPIO_FN(CSCIF1_CTS), + + /* Port37 */ + GPIO_FN(SCIFA1_SCK), + GPIO_FN(CSCIF1_SCK), + + /* Port38 */ + GPIO_FN(SCIFB0_RTS), + GPIO_FN(TPU0TO1), + GPIO_FN(SCIFB3_RTS_38), + GPIO_FN(CHSCIF0_HRTS), + + /* Port39 */ + GPIO_FN(SCIFB0_CTS), + GPIO_FN(TPU0TO2), + GPIO_FN(SCIFB3_CTS_39), + GPIO_FN(CHSCIF0_HCTS), + + /* Port40 */ + GPIO_FN(SCIFB0_SCK), + GPIO_FN(TPU0TO3), + GPIO_FN(SCIFB3_SCK_40), + GPIO_FN(CHSCIF0_HSCK), + + /* Port64 */ + GPIO_FN(PDM0_DATA), + + /* Port65 */ + GPIO_FN(PDM1_DATA), + + /* Port66 */ + GPIO_FN(HSI_RX_WAKE), + GPIO_FN(SCIFB2_CTS_66), + GPIO_FN(MSIOF3_SYNC), + GPIO_FN(GenIO4), + GPIO_FN(IRQ40), + + /* Port67 */ + GPIO_FN(HSI_RX_READY), + GPIO_FN(SCIFB1_TXD_67), + GPIO_FN(GIO_OUT3_67), + GPIO_FN(CHSCIF1_HTX), + + /* Port68 */ + GPIO_FN(HSI_RX_FLAG), + GPIO_FN(SCIFB2_TXD_68), + GPIO_FN(MSIOF3_TXD), + GPIO_FN(GIO_OUT4_68), + + /* Port69 */ + GPIO_FN(HSI_RX_DATA), + GPIO_FN(SCIFB2_RXD_69), + GPIO_FN(MSIOF3_RXD), + GPIO_FN(GIO_OUT5_69), + + /* Port70 */ + GPIO_FN(HSI_TX_FLAG), + GPIO_FN(SCIFB1_RTS_70), + GPIO_FN(GIO_OUT1_70), + GPIO_FN(HSIC_TSTCLK0), + GPIO_FN(CHSCIF1_HRTS), + + /* Port71 */ + GPIO_FN(HSI_TX_DATA), + GPIO_FN(SCIFB1_CTS_71), + GPIO_FN(GIO_OUT2_71), + GPIO_FN(HSIC_TSTCLK1), + GPIO_FN(CHSCIF1_HCTS), + + /* Port72 */ + GPIO_FN(HSI_TX_WAKE), + GPIO_FN(SCIFB1_RXD_72), + GPIO_FN(GenIO8), + GPIO_FN(CHSCIF1_HRX), + + /* Port73 */ + GPIO_FN(HSI_TX_READY), + GPIO_FN(SCIFB2_RTS_73), + GPIO_FN(MSIOF3_SCK), + GPIO_FN(GIO_OUT0_73), + + /* Port74 - Port85 */ + GPIO_FN(IRDA_OUT), + GPIO_FN(IRDA_IN), + GPIO_FN(IRDA_FIRSEL), + GPIO_FN(TPU0TO0), + GPIO_FN(DIGRFEN), + GPIO_FN(GPS_TIMESTAMP), + GPIO_FN(TXP), + GPIO_FN(TXP2), + GPIO_FN(COEX_0), + GPIO_FN(COEX_1), + GPIO_FN(IRQ19), + GPIO_FN(IRQ18), + + /* Port96 - Port101 */ + GPIO_FN(KEYIN0), + GPIO_FN(KEYIN1), + GPIO_FN(KEYIN2), + GPIO_FN(KEYIN3), + GPIO_FN(KEYIN4), + GPIO_FN(KEYIN5), + + /* Port102 */ + GPIO_FN(KEYIN6), + GPIO_FN(IRQ41), + + /* Port103 */ + GPIO_FN(KEYIN7), + GPIO_FN(IRQ42), + + /* Port104 - Port108 */ + GPIO_FN(KEYOUT0), + GPIO_FN(KEYOUT1), + GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT3), + GPIO_FN(KEYOUT4), + + /* Port109 */ + GPIO_FN(KEYOUT5), + GPIO_FN(IRQ43), + + /* Port110 */ + GPIO_FN(KEYOUT6), + GPIO_FN(IRQ44), + + /* Port111 */ + GPIO_FN(KEYOUT7), + GPIO_FN(RFANAEN), + GPIO_FN(IRQ45), + + /* Port112 */ + GPIO_FN(KEYIN8), + GPIO_FN(KEYOUT8), + GPIO_FN(SF_IRQ_04), + GPIO_FN(IRQ46), + + /* Port113 */ + GPIO_FN(KEYIN9), + GPIO_FN(KEYOUT9), + GPIO_FN(SF_IRQ_05), + GPIO_FN(IRQ47), + + /* Port114 */ + GPIO_FN(KEYIN10), + GPIO_FN(KEYOUT10), + GPIO_FN(SF_IRQ_06), + GPIO_FN(IRQ48), + + /* Port115 */ + GPIO_FN(KEYIN11), + GPIO_FN(KEYOUT11), + GPIO_FN(SF_IRQ_07), + GPIO_FN(IRQ49), + + /* Port116 */ + GPIO_FN(SCIFA0_TXD), + GPIO_FN(CSCIF0_TX), + + /* Port117 */ + GPIO_FN(SCIFA0_RXD), + GPIO_FN(CSCIF0_RX), + + /* Port118 */ + GPIO_FN(SCIFA1_TXD), + GPIO_FN(CSCIF1_TX), + + /* Port119 */ + GPIO_FN(SCIFA1_RXD), + GPIO_FN(CSCIF1_RX), + + /* Port120 */ + GPIO_FN(SF_PORT_1_120), + GPIO_FN(SCIFB3_RXD_120), + GPIO_FN(DU0_CDE), + + /* Port121 */ + GPIO_FN(SF_PORT_0_121), + GPIO_FN(SCIFB3_TXD_121), + + /* Port122 */ + GPIO_FN(SCIFB0_TXD), + GPIO_FN(CHSCIF0_HTX), + + /* Port123 */ + GPIO_FN(SCIFB0_RXD), + GPIO_FN(CHSCIF0_HRX), + + /* Port124 */ + GPIO_FN(ISP_STROBE_124), + + /* Port125 */ + GPIO_FN(STP_ISD_0), + GPIO_FN(PDM4_CLK_125), + GPIO_FN(MSIOF2_TXD), + GPIO_FN(SIM0_VOLTSEL0), + + /* Port126 */ + GPIO_FN(TS_SDEN), + GPIO_FN(MSIOF7_SYNC), + GPIO_FN(STP_ISEN_1), + + /* Port128 */ + GPIO_FN(STP_ISEN_0), + GPIO_FN(PDM1_OUTDATA_128), + GPIO_FN(MSIOF2_SYNC), + GPIO_FN(SIM1_VOLTSEL1), + + /* Port129 */ + GPIO_FN(TS_SPSYNC), + GPIO_FN(MSIOF7_RXD), + GPIO_FN(STP_ISSYNC_1), + + /* Port130 */ + GPIO_FN(STP_ISSYNC_0), + GPIO_FN(PDM4_DATA_130), + GPIO_FN(MSIOF2_RXD), + GPIO_FN(SIM0_VOLTSEL1), + + /* Port131 */ + GPIO_FN(STP_OPWM_0), + GPIO_FN(SIM1_PWRON), + + /* Port132 */ + GPIO_FN(TS_SCK), + GPIO_FN(MSIOF7_SCK), + GPIO_FN(STP_ISCLK_1), + + /* Port133 */ + GPIO_FN(STP_ISCLK_0), + GPIO_FN(PDM1_OUTCLK_133), + GPIO_FN(MSIOF2_SCK), + GPIO_FN(SIM1_VOLTSEL0), + + /* Port134 */ + GPIO_FN(TS_SDAT), + GPIO_FN(MSIOF7_TXD), + GPIO_FN(STP_ISD_1), + + /* Port160 - Port178 */ + GPIO_FN(IRQ20), + GPIO_FN(IRQ21), + GPIO_FN(IRQ22), + GPIO_FN(IRQ23), + GPIO_FN(MMCD0_0), + GPIO_FN(MMCD0_1), + GPIO_FN(MMCD0_2), + GPIO_FN(MMCD0_3), + GPIO_FN(MMCD0_4), + GPIO_FN(MMCD0_5), + GPIO_FN(MMCD0_6), + GPIO_FN(MMCD0_7), + GPIO_FN(MMCCMD0), + GPIO_FN(MMCCLK0), + GPIO_FN(MMCRST), + GPIO_FN(IRQ24), + GPIO_FN(IRQ25), + GPIO_FN(IRQ26), + GPIO_FN(IRQ27), + + /* Port192 - Port200 FN1 */ + GPIO_FN(A10), + GPIO_FN(A9), + GPIO_FN(A8), + GPIO_FN(A7), + GPIO_FN(A6), + GPIO_FN(A5), + GPIO_FN(A4), + GPIO_FN(A3), + GPIO_FN(A2), + + /* Port192 - Port200 FN2 */ + GPIO_FN(MMCD1_7), + GPIO_FN(MMCD1_6), + GPIO_FN(MMCD1_5), + GPIO_FN(MMCD1_4), + GPIO_FN(MMCD1_3), + GPIO_FN(MMCD1_2), + GPIO_FN(MMCD1_1), + GPIO_FN(MMCD1_0), + GPIO_FN(MMCCMD1), + + /* Port192 - Port200 IRQ */ + GPIO_FN(IRQ31), + GPIO_FN(IRQ32), + GPIO_FN(IRQ33), + GPIO_FN(IRQ34), + GPIO_FN(IRQ35), + GPIO_FN(IRQ36), + GPIO_FN(IRQ37), + GPIO_FN(IRQ38), + GPIO_FN(IRQ39), + + /* Port201 */ + GPIO_FN(A1), + + /* Port202 */ + GPIO_FN(A0), + GPIO_FN(BS), + + /* Port203 */ + GPIO_FN(CKO), + GPIO_FN(MMCCLK1), + + /* Port204 */ + GPIO_FN(CS0_N), + GPIO_FN(SIM0_GPO1), + + /* Port205 */ + GPIO_FN(CS2_N), + GPIO_FN(SIM0_GPO2), + + /* Port206 */ + GPIO_FN(CS4_N), + GPIO_FN(VIO_VD), + GPIO_FN(SIM1_GPO0), + + /* Port207 - Port212 FN1 */ + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + + /* Port207 - Port212 FN5 */ + GPIO_FN(GIO_OUT15), + GPIO_FN(GIO_OUT14), + GPIO_FN(GIO_OUT13), + GPIO_FN(GIO_OUT12), + GPIO_FN(WGM_TXP2), + GPIO_FN(WGM_GPS_TIMEM_ASK_RFCLK), + + /* Port213 - Port222 FN1 */ + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), + + /* Port213 - Port222 FN2 */ + GPIO_FN(VIO_D9), + GPIO_FN(VIO_D8), + GPIO_FN(VIO_D7), + GPIO_FN(VIO_D6), + GPIO_FN(VIO_D5), + GPIO_FN(VIO_D4), + GPIO_FN(VIO_D3), + GPIO_FN(VIO_D2), + GPIO_FN(VIO_D1), + GPIO_FN(VIO_D0), + + /* Port213 - Port222 FN5 */ + GPIO_FN(GIO_OUT9), + GPIO_FN(GIO_OUT8), + GPIO_FN(GIO_OUT7), + GPIO_FN(GIO_OUT6), + GPIO_FN(GIO_OUT5_217), + GPIO_FN(GIO_OUT4_218), + GPIO_FN(GIO_OUT3_219), + GPIO_FN(GIO_OUT2_220), + GPIO_FN(GIO_OUT1_221), + GPIO_FN(GIO_OUT0_222), + + /* Port224 */ + GPIO_FN(RDWR_224), + GPIO_FN(VIO_HD), + GPIO_FN(SIM1_GPO2), + + /* Port225 */ + GPIO_FN(RD_N), + + /* Port226 */ + GPIO_FN(WAIT_N), + GPIO_FN(VIO_CLK), + GPIO_FN(SIM1_GPO1), + + /* Port227 */ + GPIO_FN(WE0_N), + GPIO_FN(RDWR_227), + + /* Port228 */ + GPIO_FN(WE1_N), + GPIO_FN(SIM0_GPO0), + + /* Port229 */ + GPIO_FN(PWMO), + GPIO_FN(VIO_CKO1_229), + + /* Port230 */ + GPIO_FN(SLIM_CLK), + GPIO_FN(VIO_CKO4_230), + + /* Port231 */ + GPIO_FN(SLIM_DATA), + GPIO_FN(VIO_CKO5_231), + + /* Port232 */ + GPIO_FN(VIO_CKO2_232), + GPIO_FN(SF_PORT_0_232), + + /* Port233 */ + GPIO_FN(VIO_CKO3_233), + GPIO_FN(SF_PORT_1_233), + + /* Port234 */ + GPIO_FN(FSIACK), + GPIO_FN(PDM3_CLK_234), + GPIO_FN(ISP_IRIS1_234), + + /* Port235 */ + GPIO_FN(FSIAISLD), + GPIO_FN(PDM3_DATA_235), + + /* Port236 */ + GPIO_FN(FSIAOMC), + GPIO_FN(PDM0_OUTCLK_236), + GPIO_FN(ISP_IRIS0_236), + + /* Port237 */ + GPIO_FN(FSIAOLR), + GPIO_FN(FSIAILR), + + /* Port238 */ + GPIO_FN(FSIAOBT), + GPIO_FN(FSIAIBT), + + /* Port239 */ + GPIO_FN(FSIAOSLD), + GPIO_FN(PDM0_OUTDATA_239), + + /* Port240 */ + GPIO_FN(FSIBISLD), + + /* Port241 */ + GPIO_FN(FSIBOLR), + GPIO_FN(FSIBILR), + + /* Port242 */ + GPIO_FN(FSIBOMC), + GPIO_FN(ISP_SHUTTER1_242), + + /* Port243 */ + GPIO_FN(FSIBOBT), + GPIO_FN(FSIBIBT), + + /* Port244 */ + GPIO_FN(FSIBOSLD), + GPIO_FN(FSIASPDIF), + + /* Port245 */ + GPIO_FN(FSIBCK), + GPIO_FN(ISP_SHUTTER0_245), + + /* Port246 - Port250 FN1 */ + GPIO_FN(ISP_IRIS1_246), + GPIO_FN(ISP_IRIS0_247), + GPIO_FN(ISP_SHUTTER1_248), + GPIO_FN(ISP_SHUTTER0_249), + GPIO_FN(ISP_STROBE_250), + + /* Port256 - Port258 */ + GPIO_FN(MSIOF0_SYNC), + GPIO_FN(MSIOF0_RXD), + GPIO_FN(MSIOF0_SCK), + + /* Port259 */ + GPIO_FN(MSIOF0_SS2), + GPIO_FN(VIO_CKO3_259), + + /* Port260 */ + GPIO_FN(MSIOF0_TXD), + + /* Port261 */ + GPIO_FN(SCIFB1_SCK_261), + GPIO_FN(CHSCIF1_HSCK), + + /* Port262 */ + GPIO_FN(SCIFB2_SCK_262), + + /* Port263 - Port266 FN1 */ + GPIO_FN(MSIOF1_SS2), + GPIO_FN(MSIOF1_TXD), + GPIO_FN(MSIOF1_RXD), + GPIO_FN(MSIOF1_SS1), + + /* Port263 - Port266 FN4 */ + GPIO_FN(MSIOF5_SS2), + GPIO_FN(MSIOF5_TXD), + GPIO_FN(MSIOF5_RXD), + GPIO_FN(MSIOF5_SS1), + + /* Port267 */ + GPIO_FN(MSIOF0_SS1), + + /* Port268 */ + GPIO_FN(MSIOF1_SCK), + GPIO_FN(MSIOF5_SCK), + + /* Port269 */ + GPIO_FN(MSIOF1_SYNC), + GPIO_FN(MSIOF5_SYNC), + + /* Port270 - Port273 FN1 */ + GPIO_FN(MSIOF2_SS1), + GPIO_FN(MSIOF2_SS2), + GPIO_FN(MSIOF3_SS2), + GPIO_FN(MSIOF3_SS1), + + /* Port270 - Port273 FN3 */ + GPIO_FN(VIO_CKO5_270), + GPIO_FN(VIO_CKO2_271), + GPIO_FN(VIO_CKO1_272), + GPIO_FN(VIO_CKO4_273), + + /* Port274 */ + GPIO_FN(MSIOF4_SS2), + GPIO_FN(TPU1TO0), + + /* Port275 - Port280 */ + GPIO_FN(IC_DP), + GPIO_FN(SIM0_RST), + GPIO_FN(IC_DM), + GPIO_FN(SIM0_BSICOMP), + GPIO_FN(SIM0_CLK), + GPIO_FN(SIM0_IO), + + /* Port281 */ + GPIO_FN(SIM1_IO), + GPIO_FN(PDM2_DATA_281), + + /* Port282 */ + GPIO_FN(SIM1_CLK), + GPIO_FN(PDM2_CLK_282), + + /* Port283 */ + GPIO_FN(SIM1_RST), + + /* Port289 */ + GPIO_FN(SDHID1_0), + GPIO_FN(STMDATA0_2), + + /* Port290 */ + GPIO_FN(SDHID1_1), + GPIO_FN(STMDATA1_2), + GPIO_FN(IRQ51), + + /* Port291 - Port294 FN1 */ + GPIO_FN(SDHID1_2), + GPIO_FN(SDHID1_3), + GPIO_FN(SDHICLK1), + GPIO_FN(SDHICMD1), + + /* Port291 - Port294 FN3 */ + GPIO_FN(STMDATA2_2), + GPIO_FN(STMDATA3_2), + GPIO_FN(STMCLK_2), + GPIO_FN(STMSIDI_2), + + /* Port295 */ + GPIO_FN(SDHID2_0), + GPIO_FN(MSIOF4_TXD), + GPIO_FN(SCIFB2_TXD_295), + GPIO_FN(MSIOF6_TXD), + + /* Port296 */ + GPIO_FN(SDHID2_1), + GPIO_FN(MSIOF6_SS2), + GPIO_FN(IRQ52), + + /* Port297 - Port300 FN1 */ + GPIO_FN(SDHID2_2), + GPIO_FN(SDHID2_3), + GPIO_FN(SDHICLK2), + GPIO_FN(SDHICMD2), + + /* Port297 - Port300 FN2 */ + GPIO_FN(MSIOF4_RXD), + GPIO_FN(MSIOF4_SYNC), + GPIO_FN(MSIOF4_SCK), + GPIO_FN(MSIOF4_SS1), + + /* Port297 - Port300 FN3 */ + GPIO_FN(SCIFB2_RXD_297), + GPIO_FN(SCIFB2_CTS_298), + GPIO_FN(SCIFB2_SCK_299), + GPIO_FN(SCIFB2_RTS_300), + + /* Port297 - Port300 FN4 */ + GPIO_FN(MSIOF6_RXD), + GPIO_FN(MSIOF6_SYNC), + GPIO_FN(MSIOF6_SCK), + GPIO_FN(MSIOF6_SS1), + + /* Port301 */ + GPIO_FN(SDHICD0), + GPIO_FN(IRQ50), + + /* Port302 - Port306 FN1 */ + GPIO_FN(SDHID0_0), + GPIO_FN(SDHID0_1), + GPIO_FN(SDHID0_2), + GPIO_FN(SDHID0_3), + GPIO_FN(SDHICMD0), + + /* Port302 - Port306 FN3 */ + GPIO_FN(STMDATA0_1), + GPIO_FN(STMDATA1_1), + GPIO_FN(STMDATA2_1), + GPIO_FN(STMDATA3_1), + GPIO_FN(STMSIDI_1), + + /* Port307 */ + GPIO_FN(SDHIWP0), + + /* Port308 */ + GPIO_FN(SDHICLK0), + GPIO_FN(STMCLK_1), + + /* Port320 - Port329 */ + GPIO_FN(IRQ16), + GPIO_FN(IRQ17), + GPIO_FN(IRQ28), + GPIO_FN(IRQ29), + GPIO_FN(IRQ30), + GPIO_FN(IRQ53), + GPIO_FN(IRQ54), + GPIO_FN(IRQ55), + GPIO_FN(IRQ56), + GPIO_FN(IRQ57), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + + PORTCR(0, 0xe6050000), + PORTCR(1, 0xe6050001), + PORTCR(2, 0xe6050002), + PORTCR(3, 0xe6050003), + PORTCR(4, 0xe6050004), + PORTCR(5, 0xe6050005), + PORTCR(6, 0xe6050006), + PORTCR(7, 0xe6050007), + PORTCR(8, 0xe6050008), + PORTCR(9, 0xe6050009), + PORTCR(10, 0xe605000A), + PORTCR(11, 0xe605000B), + PORTCR(12, 0xe605000C), + PORTCR(13, 0xe605000D), + PORTCR(14, 0xe605000E), + PORTCR(15, 0xe605000F), + PORTCR(16, 0xe6050010), + PORTCR(17, 0xe6050011), + PORTCR(18, 0xe6050012), + PORTCR(19, 0xe6050013), + PORTCR(20, 0xe6050014), + PORTCR(21, 0xe6050015), + PORTCR(22, 0xe6050016), + PORTCR(23, 0xe6050017), + PORTCR(24, 0xe6050018), + PORTCR(25, 0xe6050019), + PORTCR(26, 0xe605001A), + PORTCR(27, 0xe605001B), + PORTCR(28, 0xe605001C), + PORTCR(29, 0xe605001D), + PORTCR(30, 0xe605001E), + PORTCR(32, 0xe6051020), + PORTCR(33, 0xe6051021), + PORTCR(34, 0xe6051022), + PORTCR(35, 0xe6051023), + PORTCR(36, 0xe6051024), + PORTCR(37, 0xe6051025), + PORTCR(38, 0xe6051026), + PORTCR(39, 0xe6051027), + PORTCR(40, 0xe6051028), + PORTCR(64, 0xe6050040), + PORTCR(65, 0xe6050041), + PORTCR(66, 0xe6050042), + PORTCR(67, 0xe6050043), + PORTCR(68, 0xe6050044), + PORTCR(69, 0xe6050045), + PORTCR(70, 0xe6050046), + PORTCR(71, 0xe6050047), + PORTCR(72, 0xe6050048), + PORTCR(73, 0xe6050049), + PORTCR(74, 0xe605004A), + PORTCR(75, 0xe605004B), + PORTCR(76, 0xe605004C), + PORTCR(77, 0xe605004D), + PORTCR(78, 0xe605004E), + PORTCR(79, 0xe605004F), + PORTCR(80, 0xe6050050), + PORTCR(81, 0xe6050051), + PORTCR(82, 0xe6050052), + PORTCR(83, 0xe6050053), + PORTCR(84, 0xe6050054), + PORTCR(85, 0xe6050055), + PORTCR(96, 0xe6051060), + PORTCR(97, 0xe6051061), + PORTCR(98, 0xe6051062), + PORTCR(99, 0xe6051063), + PORTCR(100, 0xe6051064), + PORTCR(101, 0xe6051065), + PORTCR(102, 0xe6051066), + PORTCR(103, 0xe6051067), + PORTCR(104, 0xe6051068), + PORTCR(105, 0xe6051069), + PORTCR(106, 0xe605106A), + PORTCR(107, 0xe605106B), + PORTCR(108, 0xe605106C), + PORTCR(109, 0xe605106D), + PORTCR(110, 0xe605106E), + PORTCR(111, 0xe605106F), + PORTCR(112, 0xe6051070), + PORTCR(113, 0xe6051071), + PORTCR(114, 0xe6051072), + PORTCR(115, 0xe6051073), + PORTCR(116, 0xe6051074), + PORTCR(117, 0xe6051075), + PORTCR(118, 0xe6051076), + PORTCR(119, 0xe6051077), + PORTCR(120, 0xe6051078), + PORTCR(121, 0xe6051079), + PORTCR(122, 0xe605107A), + PORTCR(123, 0xe605107B), + PORTCR(124, 0xe605107C), + PORTCR(125, 0xe605107D), + PORTCR(126, 0xe605107E), + PORTCR(128, 0xe6051080), + PORTCR(129, 0xe6051081), + PORTCR(130, 0xe6051082), + PORTCR(131, 0xe6051083), + PORTCR(132, 0xe6051084), + PORTCR(133, 0xe6051085), + PORTCR(134, 0xe6051086), + PORTCR(160, 0xe60520A0), + PORTCR(161, 0xe60520A1), + PORTCR(162, 0xe60520A2), + PORTCR(163, 0xe60520A3), + PORTCR(164, 0xe60520A4), + PORTCR(165, 0xe60520A5), + PORTCR(166, 0xe60520A6), + PORTCR(167, 0xe60520A7), + PORTCR(168, 0xe60520A8), + PORTCR(169, 0xe60520A9), + PORTCR(170, 0xe60520AA), + PORTCR(171, 0xe60520AB), + PORTCR(172, 0xe60520AC), + PORTCR(173, 0xe60520AD), + PORTCR(174, 0xe60520AE), + PORTCR(175, 0xe60520AF), + PORTCR(176, 0xe60520B0), + PORTCR(177, 0xe60520B1), + PORTCR(178, 0xe60520B2), + PORTCR(192, 0xe60520C0), + PORTCR(193, 0xe60520C1), + PORTCR(194, 0xe60520C2), + PORTCR(195, 0xe60520C3), + PORTCR(196, 0xe60520C4), + PORTCR(197, 0xe60520C5), + PORTCR(198, 0xe60520C6), + PORTCR(199, 0xe60520C7), + PORTCR(200, 0xe60520C8), + PORTCR(201, 0xe60520C9), + PORTCR(202, 0xe60520CA), + PORTCR(203, 0xe60520CB), + PORTCR(204, 0xe60520CC), + PORTCR(205, 0xe60520CD), + PORTCR(206, 0xe60520CE), + PORTCR(207, 0xe60520CF), + PORTCR(208, 0xe60520D0), + PORTCR(209, 0xe60520D1), + PORTCR(210, 0xe60520D2), + PORTCR(211, 0xe60520D3), + PORTCR(212, 0xe60520D4), + PORTCR(213, 0xe60520D5), + PORTCR(214, 0xe60520D6), + PORTCR(215, 0xe60520D7), + PORTCR(216, 0xe60520D8), + PORTCR(217, 0xe60520D9), + PORTCR(218, 0xe60520DA), + PORTCR(219, 0xe60520DB), + PORTCR(220, 0xe60520DC), + PORTCR(221, 0xe60520DD), + PORTCR(222, 0xe60520DE), + PORTCR(224, 0xe60520E0), + PORTCR(225, 0xe60520E1), + PORTCR(226, 0xe60520E2), + PORTCR(227, 0xe60520E3), + PORTCR(228, 0xe60520E4), + PORTCR(229, 0xe60520E5), + PORTCR(230, 0xe60520e6), + PORTCR(231, 0xe60520E7), + PORTCR(232, 0xe60520E8), + PORTCR(233, 0xe60520E9), + PORTCR(234, 0xe60520EA), + PORTCR(235, 0xe60520EB), + PORTCR(236, 0xe60520EC), + PORTCR(237, 0xe60520ED), + PORTCR(238, 0xe60520EE), + PORTCR(239, 0xe60520EF), + PORTCR(240, 0xe60520F0), + PORTCR(241, 0xe60520F1), + PORTCR(242, 0xe60520F2), + PORTCR(243, 0xe60520F3), + PORTCR(244, 0xe60520F4), + PORTCR(245, 0xe60520F5), + PORTCR(246, 0xe60520F6), + PORTCR(247, 0xe60520F7), + PORTCR(248, 0xe60520F8), + PORTCR(249, 0xe60520F9), + PORTCR(250, 0xe60520FA), + PORTCR(256, 0xe6052100), + PORTCR(257, 0xe6052101), + PORTCR(258, 0xe6052102), + PORTCR(259, 0xe6052103), + PORTCR(260, 0xe6052104), + PORTCR(261, 0xe6052105), + PORTCR(262, 0xe6052106), + PORTCR(263, 0xe6052107), + PORTCR(264, 0xe6052108), + PORTCR(265, 0xe6052109), + PORTCR(266, 0xe605210A), + PORTCR(267, 0xe605210B), + PORTCR(268, 0xe605210C), + PORTCR(269, 0xe605210D), + PORTCR(270, 0xe605210E), + PORTCR(271, 0xe605210F), + PORTCR(272, 0xe6052110), + PORTCR(273, 0xe6052111), + PORTCR(274, 0xe6052112), + PORTCR(275, 0xe6052113), + PORTCR(276, 0xe6052114), + PORTCR(277, 0xe6052115), + PORTCR(278, 0xe6052116), + PORTCR(279, 0xe6052117), + PORTCR(280, 0xe6052118), + PORTCR(281, 0xe6052119), + PORTCR(282, 0xe605211A), + PORTCR(283, 0xe605211B), + PORTCR(288, 0xe6053120), + PORTCR(289, 0xe6053121), + PORTCR(290, 0xe6053122), + PORTCR(291, 0xe6053123), + PORTCR(292, 0xe6053124), + PORTCR(293, 0xe6053125), + PORTCR(294, 0xe6053126), + PORTCR(295, 0xe6053127), + PORTCR(296, 0xe6053128), + PORTCR(297, 0xe6053129), + PORTCR(298, 0xe605312A), + PORTCR(299, 0xe605312B), + PORTCR(300, 0xe605312C), + PORTCR(301, 0xe605312D), + PORTCR(302, 0xe605312E), + PORTCR(303, 0xe605312F), + PORTCR(304, 0xe6053130), + PORTCR(305, 0xe6053131), + PORTCR(306, 0xe6053132), + PORTCR(307, 0xe6053133), + PORTCR(308, 0xe6053134), + PORTCR(320, 0xe6053140), + PORTCR(321, 0xe6053141), + PORTCR(322, 0xe6053142), + PORTCR(323, 0xe6053143), + PORTCR(324, 0xe6053144), + PORTCR(325, 0xe6053145), + PORTCR(326, 0xe6053146), + PORTCR(327, 0xe6053147), + PORTCR(328, 0xe6053148), + PORTCR(329, 0xe6053149), + + { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { + MSEL1CR_31_0, MSEL1CR_31_1, + 0, 0, + 0, 0, + 0, 0, + MSEL1CR_27_0, MSEL1CR_27_1, + 0, 0, + MSEL1CR_25_0, MSEL1CR_25_1, + MSEL1CR_24_0, MSEL1CR_24_1, + 0, 0, + MSEL1CR_22_0, MSEL1CR_22_1, + MSEL1CR_21_0, MSEL1CR_21_1, + MSEL1CR_20_0, MSEL1CR_20_1, + MSEL1CR_19_0, MSEL1CR_19_1, + MSEL1CR_18_0, MSEL1CR_18_1, + MSEL1CR_17_0, MSEL1CR_17_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_11_0, MSEL1CR_11_1, + MSEL1CR_10_0, MSEL1CR_10_1, + MSEL1CR_09_0, MSEL1CR_09_1, + MSEL1CR_08_0, MSEL1CR_08_1, + MSEL1CR_07_0, MSEL1CR_07_1, + MSEL1CR_06_0, MSEL1CR_06_1, + MSEL1CR_05_0, MSEL1CR_05_1, + MSEL1CR_04_0, MSEL1CR_04_1, + MSEL1CR_03_0, MSEL1CR_03_1, + MSEL1CR_02_0, MSEL1CR_02_1, + MSEL1CR_01_0, MSEL1CR_01_1, + MSEL1CR_00_0, MSEL1CR_00_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { + MSEL3CR_31_0, MSEL3CR_31_1, + 0, 0, + 0, 0, + MSEL3CR_28_0, MSEL3CR_28_1, + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + 0, 0, + 0, 0, + MSEL3CR_23_0, MSEL3CR_23_1, + MSEL3CR_22_0, MSEL3CR_22_1, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + MSEL3CR_19_0, MSEL3CR_19_1, + MSEL3CR_18_0, MSEL3CR_18_1, + MSEL3CR_17_0, MSEL3CR_17_1, + MSEL3CR_16_0, MSEL3CR_16_1, + MSEL3CR_15_0, MSEL3CR_15_1, + 0, 0, + 0, 0, + MSEL3CR_12_0, MSEL3CR_12_1, + MSEL3CR_11_0, MSEL3CR_11_1, + MSEL3CR_10_0, MSEL3CR_10_1, + MSEL3CR_09_0, MSEL3CR_09_1, + 0, 0, + 0, 0, + MSEL3CR_06_0, MSEL3CR_06_1, + 0, 0, + 0, 0, + MSEL3CR_03_0, MSEL3CR_03_1, + 0, 0, + MSEL3CR_01_0, MSEL3CR_01_1, + MSEL3CR_00_0, MSEL3CR_00_1, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { + 0, 0, + MSEL4CR_30_0, MSEL4CR_30_1, + MSEL4CR_29_0, MSEL4CR_29_1, + MSEL4CR_28_0, MSEL4CR_28_1, + MSEL4CR_27_0, MSEL4CR_27_1, + MSEL4CR_26_0, MSEL4CR_26_1, + MSEL4CR_25_0, MSEL4CR_25_1, + MSEL4CR_24_0, MSEL4CR_24_1, + MSEL4CR_23_0, MSEL4CR_23_1, + MSEL4CR_22_0, MSEL4CR_22_1, + MSEL4CR_21_0, MSEL4CR_21_1, + MSEL4CR_20_0, MSEL4CR_20_1, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + MSEL4CR_13_0, MSEL4CR_13_1, + MSEL4CR_12_0, MSEL4CR_12_1, + MSEL4CR_11_0, MSEL4CR_11_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_09_0, MSEL4CR_09_1, + 0, 0, + MSEL4CR_07_0, MSEL4CR_07_1, + 0, 0, + 0, 0, + MSEL4CR_04_0, MSEL4CR_04_1, + 0, 0, + 0, 0, + MSEL4CR_01_0, MSEL4CR_01_1, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) { + MSEL5CR_31_0, MSEL5CR_31_1, + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + MSEL5CR_28_0, MSEL5CR_28_1, + MSEL5CR_27_0, MSEL5CR_27_1, + MSEL5CR_26_0, MSEL5CR_26_1, + MSEL5CR_25_0, MSEL5CR_25_1, + MSEL5CR_24_0, MSEL5CR_24_1, + MSEL5CR_23_0, MSEL5CR_23_1, + MSEL5CR_22_0, MSEL5CR_22_1, + MSEL5CR_21_0, MSEL5CR_21_1, + MSEL5CR_20_0, MSEL5CR_20_1, + MSEL5CR_19_0, MSEL5CR_19_1, + MSEL5CR_18_0, MSEL5CR_18_1, + MSEL5CR_17_0, MSEL5CR_17_1, + MSEL5CR_16_0, MSEL5CR_16_1, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + MSEL5CR_09_0, MSEL5CR_09_1, + MSEL5CR_08_0, MSEL5CR_08_1, + MSEL5CR_07_0, MSEL5CR_07_1, + MSEL5CR_06_0, MSEL5CR_06_1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL8CR_16_0, MSEL8CR_16_1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL8CR_01_0, MSEL8CR_01_1, + MSEL8CR_00_0, MSEL8CR_00_1, + } + }, + { }, +}; + +static const struct pinmux_data_reg pinmux_data_regs[] = { + + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + 0, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA, + } + }, + { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA, + } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA, + } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) { + 0, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA, + } + }, + { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA, + } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA, + } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) { + 0, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA, + } + }, + { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) { + 0, 0, 0, 0, + 0, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA, + } + }, + { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) { + 0, 0, 0, 0, + PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA, + PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, + PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, + PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, + PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA, + } + }, + { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT308_DATA, + PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, + PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, + PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, + PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, + PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA, + } + }, + { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT329_DATA, PORT328_DATA, + PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA, + PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA, + } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a73a4_pinmux_info = { + .name = "r8a73a4_pfc", + + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; From f365bfcc8723e41b9110c5e7eb292a39b26ad8ba Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:49:59 +0900 Subject: [PATCH 285/307] sh-pfc: r8a73a4: Support sparse GPIO numbers The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers in the PFC SoC data. Pin numbers shall be used with the GPIO API from this point on. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/r8a73a4.h | 2 +- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index f0b1b4a962b3..2d4af4af3634 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -86,7 +86,7 @@ enum { GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329, /* Port0 */ - GPIO_FN_LCDD0, + GPIO_FN_LCDD0 = 330, GPIO_FN_PDM2_CLK_0, GPIO_FN_DU0_DR0, GPIO_FN_IRQ0, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 47d75d5548eb..5dd68fb96274 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -1424,6 +1424,20 @@ static struct sh_pfc_pin pinmux_pins[] = { GPIO_PORT_ALL(), }; +static const struct pinmux_range pinmux_ranges[] = { + {.begin = 0, .end = 30,}, + {.begin = 32, .end = 40,}, + {.begin = 64, .end = 85,}, + {.begin = 96, .end = 126,}, + {.begin = 128, .end = 134,}, + {.begin = 160, .end = 178,}, + {.begin = 192, .end = 222,}, + {.begin = 224, .end = 250,}, + {.begin = 256, .end = 283,}, + {.begin = 288, .end = 308,}, + {.begin = 320, .end = 329,}, +}; + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) static const struct pinmux_func pinmux_func_gpios[] = { @@ -2815,6 +2829,8 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), + .ranges = pinmux_ranges, + .nr_ranges = ARRAY_SIZE(pinmux_ranges), .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), From c96931ca88b583a2d7c8bb02a33871c982bd5b68 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:50:09 +0900 Subject: [PATCH 286/307] sh-pfc: r8a73a4: GPIO IRQ support V2 of code to add GPIO -> IRQ mappings to the PFC table for the r8a73a4 SoC. Requires the IRQs to be mapped at a fixed location in Linux IRQ space. The actual IRQs are not handled by the PFC, instead IRQC is used on r8a73a4. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 5dd68fb96274..01773291ea91 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2818,6 +2818,66 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; +static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(irq_pin(0), 0), + PINMUX_IRQ(irq_pin(1), 1), + PINMUX_IRQ(irq_pin(2), 2), + PINMUX_IRQ(irq_pin(3), 3), + PINMUX_IRQ(irq_pin(4), 4), + PINMUX_IRQ(irq_pin(5), 5), + PINMUX_IRQ(irq_pin(6), 6), + PINMUX_IRQ(irq_pin(7), 7), + PINMUX_IRQ(irq_pin(8), 8), + PINMUX_IRQ(irq_pin(9), 9), + PINMUX_IRQ(irq_pin(10), 10), + PINMUX_IRQ(irq_pin(11), 11), + PINMUX_IRQ(irq_pin(12), 12), + PINMUX_IRQ(irq_pin(13), 13), + PINMUX_IRQ(irq_pin(14), 14), + PINMUX_IRQ(irq_pin(15), 15), + PINMUX_IRQ(irq_pin(16), 320), + PINMUX_IRQ(irq_pin(17), 321), + PINMUX_IRQ(irq_pin(18), 85), + PINMUX_IRQ(irq_pin(19), 84), + PINMUX_IRQ(irq_pin(20), 160), + PINMUX_IRQ(irq_pin(21), 161), + PINMUX_IRQ(irq_pin(22), 162), + PINMUX_IRQ(irq_pin(23), 163), + PINMUX_IRQ(irq_pin(24), 175), + PINMUX_IRQ(irq_pin(25), 176), + PINMUX_IRQ(irq_pin(26), 177), + PINMUX_IRQ(irq_pin(27), 178), + PINMUX_IRQ(irq_pin(28), 322), + PINMUX_IRQ(irq_pin(29), 323), + PINMUX_IRQ(irq_pin(30), 324), + PINMUX_IRQ(irq_pin(31), 192), + PINMUX_IRQ(irq_pin(32), 193), + PINMUX_IRQ(irq_pin(33), 194), + PINMUX_IRQ(irq_pin(34), 195), + PINMUX_IRQ(irq_pin(35), 196), + PINMUX_IRQ(irq_pin(36), 197), + PINMUX_IRQ(irq_pin(37), 198), + PINMUX_IRQ(irq_pin(38), 199), + PINMUX_IRQ(irq_pin(39), 200), + PINMUX_IRQ(irq_pin(40), 66), + PINMUX_IRQ(irq_pin(41), 102), + PINMUX_IRQ(irq_pin(42), 103), + PINMUX_IRQ(irq_pin(43), 109), + PINMUX_IRQ(irq_pin(44), 110), + PINMUX_IRQ(irq_pin(45), 111), + PINMUX_IRQ(irq_pin(46), 112), + PINMUX_IRQ(irq_pin(47), 113), + PINMUX_IRQ(irq_pin(48), 114), + PINMUX_IRQ(irq_pin(49), 115), + PINMUX_IRQ(irq_pin(50), 301), + PINMUX_IRQ(irq_pin(51), 290), + PINMUX_IRQ(irq_pin(52), 296), + PINMUX_IRQ(irq_pin(53), 325), + PINMUX_IRQ(irq_pin(54), 326), + PINMUX_IRQ(irq_pin(55), 327), + PINMUX_IRQ(irq_pin(56), 328), + PINMUX_IRQ(irq_pin(57), 329), +}; const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .name = "r8a73a4_pfc", @@ -2839,4 +2899,7 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .gpio_data = pinmux_data, .gpio_data_size = ARRAY_SIZE(pinmux_data), + + .gpio_irq = pinmux_irqs, + .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), }; From 57ef73b469e7e6f7d15e5467649c787bc7070819 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:50:27 +0900 Subject: [PATCH 287/307] sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support Implement pull-up/down support for r8a73a4 similar to the implementation for sh73a0. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 197 ++++++++++++++++++++++++++- 1 file changed, 196 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 01773291ea91..86a5fd33a479 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -17,10 +17,13 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include +#include #include #include +#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ @@ -1420,8 +1423,143 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQ57_MARK, PORT329_FN0), }; +#define R8A73A4_PIN(pin, cfgs) \ + { \ + .name = __stringify(PORT##pin), \ + .enum_id = PORT##pin##_DATA, \ + .configs = cfgs, \ + } + +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD) +#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O) + static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), + R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1), + R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3), + R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5), + R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7), + R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9), + R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11), + R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13), + R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15), + R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17), + R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19), + R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21), + R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23), + R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25), + R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27), + R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29), + R8A73A4_PIN_IO_PU_PD(30), + R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33), + R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35), + R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37), + R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39), + R8A73A4_PIN_IO_PU_PD(40), + R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65), + R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67), + R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69), + R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71), + R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73), + R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75), + R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77), + R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79), + R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81), + R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83), + R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85), + R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97), + R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99), + R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101), + R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103), + R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105), + R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107), + R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109), + R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111), + R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113), + R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115), + R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117), + R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119), + R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121), + R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123), + R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125), + R8A73A4_PIN_IO_PU_PD(126), + R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129), + R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131), + R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133), + R8A73A4_PIN_IO_PU_PD(134), + R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161), + R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163), + R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165), + R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167), + R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169), + R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171), + R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173), + R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175), + R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177), + R8A73A4_PIN_IO_PU_PD(178), + R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193), + R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195), + R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197), + R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199), + R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201), + R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203), + R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205), + R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207), + R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209), + R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211), + R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213), + R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215), + R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217), + R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219), + R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221), + R8A73A4_PIN_IO_PU_PD(222), + R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225), + R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227), + R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229), + R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231), + R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233), + R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235), + R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237), + R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239), + R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241), + R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243), + R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245), + R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247), + R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249), + R8A73A4_PIN_IO_PU_PD(250), + R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257), + R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259), + R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261), + R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263), + R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265), + R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267), + R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269), + R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271), + R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273), + R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275), + R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277), + R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279), + R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281), + R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283), + R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289), + R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291), + R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293), + R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295), + R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297), + R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299), + R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301), + R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303), + R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305), + R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307), + R8A73A4_PIN_IO_PU_PD(308), + R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321), + R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323), + R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325), + R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327), + R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329), }; static const struct pinmux_range pinmux_ranges[] = { @@ -2878,8 +3016,65 @@ static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(irq_pin(56), 328), PINMUX_IRQ(irq_pin(57), 329), }; + +#define PORTCR_PULMD_OFF (0 << 6) +#define PORTCR_PULMD_DOWN (2 << 6) +#define PORTCR_PULMD_UP (3 << 6) +#define PORTCR_PULMD_MASK (3 << 6) + +static const unsigned int r8a73a4_portcr_offsets[] = { + 0x00000000, 0x00001000, 0x00000000, 0x00001000, + 0x00001000, 0x00002000, 0x00002000, 0x00002000, + 0x00002000, 0x00003000, 0x00003000, +}; + +static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + void __iomem *addr; + + addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + + switch (ioread8(addr) & PORTCR_PULMD_MASK) { + case PORTCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr; + u32 value; + + addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + value = ioread8(addr) & ~PORTCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = { + .get_bias = r8a73a4_pinmux_get_bias, + .set_bias = r8a73a4_pinmux_set_bias, +}; + const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .name = "r8a73a4_pfc", + .ops = &r8a73a4_pinmux_ops, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, From 172fd616dd46a181be5c9c17bd0a84dd8ae0ce94 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:50:36 +0900 Subject: [PATCH 288/307] sh-pfc: r8a73a4: Add SCIF pin groups and functions Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and SCIFB0->SCIFB3. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 287 +++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 86a5fd33a479..cd5c5fd74ba4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -1576,6 +1576,286 @@ static const struct pinmux_range pinmux_ranges[] = { {.begin = 320, .end = 329,}, }; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* SCIFA0_RXD, SCIFA0_TXD */ + 117, 116, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCIFA0_SCK */ + 34, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* SCIFA0_RTS, SCIFA0_CTS */ + 32, 33, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* SCIFA1_RXD, SCIFA1_TXD */ + 119, 118, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCIFA1_SCK */ + 37, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* SCIFA1_RTS, SCIFA1_CTS */ + 35, 36, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* SCIFB0_RXD, SCIFB0_TXD */ + 123, 122, +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCIFB0_SCK */ + 40, +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* SCIFB0_RTS, SCIFB0_CTS */ + 38, 39, +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_MARK, SCIFB0_CTS_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* SCIFB1_RXD, SCIFB1_TXD */ + 27, 26, +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCIFB1_SCK */ + 28, +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_28_MARK, +}; +static const unsigned int scifb1_ctrl_pins[] = { + /* SCIFB1_RTS, SCIFB1_CTS */ + 24, 25, +}; +static const unsigned int scifb1_ctrl_mux[] = { + SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK, +}; +static const unsigned int scifb1_data_b_pins[] = { + /* SCIFB1_RXD, SCIFB1_TXD */ + 72, 67, +}; +static const unsigned int scifb1_data_b_mux[] = { + SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK, +}; +static const unsigned int scifb1_clk_b_pins[] = { + /* SCIFB1_SCK */ + 261, +}; +static const unsigned int scifb1_clk_b_mux[] = { + SCIFB1_SCK_261_MARK, +}; +static const unsigned int scifb1_ctrl_b_pins[] = { + /* SCIFB1_RTS, SCIFB1_CTS */ + 70, 71, +}; +static const unsigned int scifb1_ctrl_b_mux[] = { + SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* SCIFB2_RXD, SCIFB2_TXD */ + 69, 68, +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCIFB2_SCK */ + 262, +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_262_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* SCIFB2_RTS, SCIFB2_CTS */ + 73, 66, +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK, +}; +static const unsigned int scifb2_data_b_pins[] = { + /* SCIFB2_RXD, SCIFB2_TXD */ + 297, 295, +}; +static const unsigned int scifb2_data_b_mux[] = { + SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK, +}; +static const unsigned int scifb2_clk_b_pins[] = { + /* SCIFB2_SCK */ + 299, +}; +static const unsigned int scifb2_clk_b_mux[] = { + SCIFB2_SCK_299_MARK, +}; +static const unsigned int scifb2_ctrl_b_pins[] = { + /* SCIFB2_RTS, SCIFB2_CTS */ + 300, 298, +}; +static const unsigned int scifb2_ctrl_b_mux[] = { + SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK, +}; +/* - SCIFB3 ----------------------------------------------------------------- */ +static const unsigned int scifb3_data_pins[] = { + /* SCIFB3_RXD, SCIFB3_TXD */ + 22, 21, +}; +static const unsigned int scifb3_data_mux[] = { + SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK, +}; +static const unsigned int scifb3_clk_pins[] = { + /* SCIFB3_SCK */ + 23, +}; +static const unsigned int scifb3_clk_mux[] = { + SCIFB3_SCK_23_MARK, +}; +static const unsigned int scifb3_ctrl_pins[] = { + /* SCIFB3_RTS, SCIFB3_CTS */ + 19, 20, +}; +static const unsigned int scifb3_ctrl_mux[] = { + SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK, +}; +static const unsigned int scifb3_data_b_pins[] = { + /* SCIFB3_RXD, SCIFB3_TXD */ + 120, 121, +}; +static const unsigned int scifb3_data_b_mux[] = { + SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK, +}; +static const unsigned int scifb3_clk_b_pins[] = { + /* SCIFB3_SCK */ + 40, +}; +static const unsigned int scifb3_clk_b_mux[] = { + SCIFB3_SCK_40_MARK, +}; +static const unsigned int scifb3_ctrl_b_pins[] = { + /* SCIFB3_RTS, SCIFB3_CTS */ + 38, 39, +}; +static const unsigned int scifb3_ctrl_b_mux[] = { + SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb3_data), + SH_PFC_PIN_GROUP(scifb3_clk), + SH_PFC_PIN_GROUP(scifb3_ctrl), + SH_PFC_PIN_GROUP(scifb3_data_b), + SH_PFC_PIN_GROUP(scifb3_clk_b), + SH_PFC_PIN_GROUP(scifb3_ctrl_b), +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", +}; + +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", + "scifb1_ctrl", + "scifb1_data_b", + "scifb1_clk_b", + "scifb1_ctrl_b", +}; + +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", + "scifb2_data_b", + "scifb2_clk_b", + "scifb2_ctrl_b", +}; + +static const char * const scifb3_groups[] = { + "scifb3_data", + "scifb3_clk", + "scifb3_ctrl", + "scifb3_data_b", + "scifb3_clk_b", + "scifb3_ctrl_b", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scifb3), +}; + #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) static const struct pinmux_func pinmux_func_gpios[] = { @@ -3084,8 +3364,15 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), + .ranges = pinmux_ranges, .nr_ranges = ARRAY_SIZE(pinmux_ranges), + + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), From 515a828f773ba7389d77db90b980565382ece977 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:16:37 +0900 Subject: [PATCH 289/307] sh-pfc: r8a73a4: Add IRQC pin groups and functions V2 of PINCTRL support for r8a73a4 IRQC hardware and in particular the external pins IRQ0 -> IRQ57. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 186 +++++++++++++++++++++++++++ 1 file changed, 186 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index cd5c5fd74ba4..8a5288c99a83 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -1576,6 +1576,72 @@ static const struct pinmux_range pinmux_ranges[] = { {.begin = 320, .end = 329,}, }; +/* - IRQC ------------------------------------------------------------------- */ +#define IRQC_PINS_MUX(pin, irq_mark) \ +static const unsigned int irqc_irq##irq_mark##_pins[] = { \ + pin, \ +}; \ +static const unsigned int irqc_irq##irq_mark##_mux[] = { \ + IRQ##irq_mark##_MARK, \ +} +IRQC_PINS_MUX(0, 0); +IRQC_PINS_MUX(1, 1); +IRQC_PINS_MUX(2, 2); +IRQC_PINS_MUX(3, 3); +IRQC_PINS_MUX(4, 4); +IRQC_PINS_MUX(5, 5); +IRQC_PINS_MUX(6, 6); +IRQC_PINS_MUX(7, 7); +IRQC_PINS_MUX(8, 8); +IRQC_PINS_MUX(9, 9); +IRQC_PINS_MUX(10, 10); +IRQC_PINS_MUX(11, 11); +IRQC_PINS_MUX(12, 12); +IRQC_PINS_MUX(13, 13); +IRQC_PINS_MUX(14, 14); +IRQC_PINS_MUX(15, 15); +IRQC_PINS_MUX(66, 40); +IRQC_PINS_MUX(84, 19); +IRQC_PINS_MUX(85, 18); +IRQC_PINS_MUX(102, 41); +IRQC_PINS_MUX(103, 42); +IRQC_PINS_MUX(109, 43); +IRQC_PINS_MUX(110, 44); +IRQC_PINS_MUX(111, 45); +IRQC_PINS_MUX(112, 46); +IRQC_PINS_MUX(113, 47); +IRQC_PINS_MUX(114, 48); +IRQC_PINS_MUX(115, 49); +IRQC_PINS_MUX(160, 20); +IRQC_PINS_MUX(161, 21); +IRQC_PINS_MUX(162, 22); +IRQC_PINS_MUX(163, 23); +IRQC_PINS_MUX(175, 24); +IRQC_PINS_MUX(176, 25); +IRQC_PINS_MUX(177, 26); +IRQC_PINS_MUX(178, 27); +IRQC_PINS_MUX(192, 31); +IRQC_PINS_MUX(193, 32); +IRQC_PINS_MUX(194, 33); +IRQC_PINS_MUX(195, 34); +IRQC_PINS_MUX(196, 35); +IRQC_PINS_MUX(197, 36); +IRQC_PINS_MUX(198, 37); +IRQC_PINS_MUX(199, 38); +IRQC_PINS_MUX(200, 39); +IRQC_PINS_MUX(290, 51); +IRQC_PINS_MUX(296, 52); +IRQC_PINS_MUX(301, 50); +IRQC_PINS_MUX(320, 16); +IRQC_PINS_MUX(321, 17); +IRQC_PINS_MUX(322, 28); +IRQC_PINS_MUX(323, 29); +IRQC_PINS_MUX(324, 30); +IRQC_PINS_MUX(325, 53); +IRQC_PINS_MUX(326, 54); +IRQC_PINS_MUX(327, 55); +IRQC_PINS_MUX(328, 56); +IRQC_PINS_MUX(329, 57); /* - SCIFA0 ----------------------------------------------------------------- */ static const unsigned int scifa0_data_pins[] = { /* SCIFA0_RXD, SCIFA0_TXD */ @@ -1773,6 +1839,64 @@ static const unsigned int scifb3_ctrl_b_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(irqc_irq0), + SH_PFC_PIN_GROUP(irqc_irq1), + SH_PFC_PIN_GROUP(irqc_irq2), + SH_PFC_PIN_GROUP(irqc_irq3), + SH_PFC_PIN_GROUP(irqc_irq4), + SH_PFC_PIN_GROUP(irqc_irq5), + SH_PFC_PIN_GROUP(irqc_irq6), + SH_PFC_PIN_GROUP(irqc_irq7), + SH_PFC_PIN_GROUP(irqc_irq8), + SH_PFC_PIN_GROUP(irqc_irq9), + SH_PFC_PIN_GROUP(irqc_irq10), + SH_PFC_PIN_GROUP(irqc_irq11), + SH_PFC_PIN_GROUP(irqc_irq12), + SH_PFC_PIN_GROUP(irqc_irq13), + SH_PFC_PIN_GROUP(irqc_irq14), + SH_PFC_PIN_GROUP(irqc_irq15), + SH_PFC_PIN_GROUP(irqc_irq16), + SH_PFC_PIN_GROUP(irqc_irq17), + SH_PFC_PIN_GROUP(irqc_irq18), + SH_PFC_PIN_GROUP(irqc_irq19), + SH_PFC_PIN_GROUP(irqc_irq20), + SH_PFC_PIN_GROUP(irqc_irq21), + SH_PFC_PIN_GROUP(irqc_irq22), + SH_PFC_PIN_GROUP(irqc_irq23), + SH_PFC_PIN_GROUP(irqc_irq24), + SH_PFC_PIN_GROUP(irqc_irq25), + SH_PFC_PIN_GROUP(irqc_irq26), + SH_PFC_PIN_GROUP(irqc_irq27), + SH_PFC_PIN_GROUP(irqc_irq28), + SH_PFC_PIN_GROUP(irqc_irq29), + SH_PFC_PIN_GROUP(irqc_irq30), + SH_PFC_PIN_GROUP(irqc_irq31), + SH_PFC_PIN_GROUP(irqc_irq32), + SH_PFC_PIN_GROUP(irqc_irq33), + SH_PFC_PIN_GROUP(irqc_irq34), + SH_PFC_PIN_GROUP(irqc_irq35), + SH_PFC_PIN_GROUP(irqc_irq36), + SH_PFC_PIN_GROUP(irqc_irq37), + SH_PFC_PIN_GROUP(irqc_irq38), + SH_PFC_PIN_GROUP(irqc_irq39), + SH_PFC_PIN_GROUP(irqc_irq40), + SH_PFC_PIN_GROUP(irqc_irq41), + SH_PFC_PIN_GROUP(irqc_irq42), + SH_PFC_PIN_GROUP(irqc_irq43), + SH_PFC_PIN_GROUP(irqc_irq44), + SH_PFC_PIN_GROUP(irqc_irq45), + SH_PFC_PIN_GROUP(irqc_irq46), + SH_PFC_PIN_GROUP(irqc_irq47), + SH_PFC_PIN_GROUP(irqc_irq48), + SH_PFC_PIN_GROUP(irqc_irq49), + SH_PFC_PIN_GROUP(irqc_irq50), + SH_PFC_PIN_GROUP(irqc_irq51), + SH_PFC_PIN_GROUP(irqc_irq52), + SH_PFC_PIN_GROUP(irqc_irq53), + SH_PFC_PIN_GROUP(irqc_irq54), + SH_PFC_PIN_GROUP(irqc_irq55), + SH_PFC_PIN_GROUP(irqc_irq56), + SH_PFC_PIN_GROUP(irqc_irq57), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), SH_PFC_PIN_GROUP(scifa0_ctrl), @@ -1802,6 +1926,67 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb3_ctrl_b), }; +static const char * const irqc_groups[] = { + "irqc_irq0", + "irqc_irq1", + "irqc_irq2", + "irqc_irq3", + "irqc_irq4", + "irqc_irq5", + "irqc_irq6", + "irqc_irq7", + "irqc_irq8", + "irqc_irq9", + "irqc_irq10", + "irqc_irq11", + "irqc_irq12", + "irqc_irq13", + "irqc_irq14", + "irqc_irq15", + "irqc_irq16", + "irqc_irq17", + "irqc_irq18", + "irqc_irq19", + "irqc_irq20", + "irqc_irq21", + "irqc_irq22", + "irqc_irq23", + "irqc_irq24", + "irqc_irq25", + "irqc_irq26", + "irqc_irq27", + "irqc_irq28", + "irqc_irq29", + "irqc_irq30", + "irqc_irq31", + "irqc_irq32", + "irqc_irq33", + "irqc_irq34", + "irqc_irq35", + "irqc_irq36", + "irqc_irq37", + "irqc_irq38", + "irqc_irq39", + "irqc_irq40", + "irqc_irq41", + "irqc_irq42", + "irqc_irq43", + "irqc_irq44", + "irqc_irq45", + "irqc_irq46", + "irqc_irq47", + "irqc_irq48", + "irqc_irq49", + "irqc_irq50", + "irqc_irq51", + "irqc_irq52", + "irqc_irq53", + "irqc_irq54", + "irqc_irq55", + "irqc_irq56", + "irqc_irq57", +}; + static const char * const scifa0_groups[] = { "scifa0_data", "scifa0_clk", @@ -1848,6 +2033,7 @@ static const char * const scifb3_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(irqc), SH_PFC_FUNCTION(scifa0), SH_PFC_FUNCTION(scifa1), SH_PFC_FUNCTION(scifb0), From 504e584aa1937d4819859ecadf0140ea252f3a84 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:50:55 +0900 Subject: [PATCH 290/307] sh-pfc: r8a73a4: Remove SCIF function GPIOS The r8a73a4 board support will use the pinctrl API to control the SCIF pins, remove the corresponding unused function GPIOS. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 45 ---------------------------- 1 file changed, 45 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 8a5288c99a83..470b18f1a910 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2160,55 +2160,45 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port19 */ GPIO_FN(LCDD19), - GPIO_FN(SCIFB3_RTS_19), GPIO_FN(DU0_DB3), /* Port20 */ GPIO_FN(LCDD20), - GPIO_FN(SCIFB3_CTS_20), GPIO_FN(DU0_DB4), /* Port21 */ GPIO_FN(LCDD21), - GPIO_FN(SCIFB3_TXD_21), GPIO_FN(DU0_DB5), /* Port22 */ GPIO_FN(LCDD22), - GPIO_FN(SCIFB3_RXD_22), GPIO_FN(DU0_DB6), /* Port23 */ GPIO_FN(LCDD23), - GPIO_FN(SCIFB3_SCK_23), GPIO_FN(DU0_DB7), /* Port24 */ GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), - GPIO_FN(SCIFB1_RTS_24), GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N), /* Port25 */ GPIO_FN(LCDVSYN), - GPIO_FN(SCIFB1_CTS_25), GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N), /* Port26 */ GPIO_FN(LCDDCK), GPIO_FN(LCDWR), - GPIO_FN(SCIFB1_TXD_26), GPIO_FN(DU0_DOTCLKIN), /* Port27 */ GPIO_FN(LCDDISP), GPIO_FN(LCDRS), - GPIO_FN(SCIFB1_RXD_27), GPIO_FN(DU0_DOTCLKOUT), /* Port28 */ GPIO_FN(LCDRD_N), - GPIO_FN(SCIFB1_SCK_28), GPIO_FN(DU0_DOTCLKOUTB), /* Port29 */ @@ -2222,48 +2212,36 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(DU0_ODDF_N_CLAMP), /* Port32 */ - GPIO_FN(SCIFA0_RTS), GPIO_FN(SIM0_DET), GPIO_FN(CSCIF0_RTS), /* Port33 */ - GPIO_FN(SCIFA0_CTS), GPIO_FN(SIM1_DET), GPIO_FN(CSCIF0_CTS), /* Port34 */ - GPIO_FN(SCIFA0_SCK), GPIO_FN(SIM0_PWRON), GPIO_FN(CSCIF0_SCK), /* Port35 */ - GPIO_FN(SCIFA1_RTS), GPIO_FN(CSCIF1_RTS), /* Port36 */ - GPIO_FN(SCIFA1_CTS), GPIO_FN(CSCIF1_CTS), /* Port37 */ - GPIO_FN(SCIFA1_SCK), GPIO_FN(CSCIF1_SCK), /* Port38 */ - GPIO_FN(SCIFB0_RTS), GPIO_FN(TPU0TO1), - GPIO_FN(SCIFB3_RTS_38), GPIO_FN(CHSCIF0_HRTS), /* Port39 */ - GPIO_FN(SCIFB0_CTS), GPIO_FN(TPU0TO2), - GPIO_FN(SCIFB3_CTS_39), GPIO_FN(CHSCIF0_HCTS), /* Port40 */ - GPIO_FN(SCIFB0_SCK), GPIO_FN(TPU0TO3), - GPIO_FN(SCIFB3_SCK_40), GPIO_FN(CHSCIF0_HSCK), /* Port64 */ @@ -2274,52 +2252,44 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port66 */ GPIO_FN(HSI_RX_WAKE), - GPIO_FN(SCIFB2_CTS_66), GPIO_FN(MSIOF3_SYNC), GPIO_FN(GenIO4), GPIO_FN(IRQ40), /* Port67 */ GPIO_FN(HSI_RX_READY), - GPIO_FN(SCIFB1_TXD_67), GPIO_FN(GIO_OUT3_67), GPIO_FN(CHSCIF1_HTX), /* Port68 */ GPIO_FN(HSI_RX_FLAG), - GPIO_FN(SCIFB2_TXD_68), GPIO_FN(MSIOF3_TXD), GPIO_FN(GIO_OUT4_68), /* Port69 */ GPIO_FN(HSI_RX_DATA), - GPIO_FN(SCIFB2_RXD_69), GPIO_FN(MSIOF3_RXD), GPIO_FN(GIO_OUT5_69), /* Port70 */ GPIO_FN(HSI_TX_FLAG), - GPIO_FN(SCIFB1_RTS_70), GPIO_FN(GIO_OUT1_70), GPIO_FN(HSIC_TSTCLK0), GPIO_FN(CHSCIF1_HRTS), /* Port71 */ GPIO_FN(HSI_TX_DATA), - GPIO_FN(SCIFB1_CTS_71), GPIO_FN(GIO_OUT2_71), GPIO_FN(HSIC_TSTCLK1), GPIO_FN(CHSCIF1_HCTS), /* Port72 */ GPIO_FN(HSI_TX_WAKE), - GPIO_FN(SCIFB1_RXD_72), GPIO_FN(GenIO8), GPIO_FN(CHSCIF1_HRX), /* Port73 */ GPIO_FN(HSI_TX_READY), - GPIO_FN(SCIFB2_RTS_73), GPIO_FN(MSIOF3_SCK), GPIO_FN(GIO_OUT0_73), @@ -2398,36 +2368,28 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(IRQ49), /* Port116 */ - GPIO_FN(SCIFA0_TXD), GPIO_FN(CSCIF0_TX), /* Port117 */ - GPIO_FN(SCIFA0_RXD), GPIO_FN(CSCIF0_RX), /* Port118 */ - GPIO_FN(SCIFA1_TXD), GPIO_FN(CSCIF1_TX), /* Port119 */ - GPIO_FN(SCIFA1_RXD), GPIO_FN(CSCIF1_RX), /* Port120 */ GPIO_FN(SF_PORT_1_120), - GPIO_FN(SCIFB3_RXD_120), GPIO_FN(DU0_CDE), /* Port121 */ GPIO_FN(SF_PORT_0_121), - GPIO_FN(SCIFB3_TXD_121), /* Port122 */ - GPIO_FN(SCIFB0_TXD), GPIO_FN(CHSCIF0_HTX), /* Port123 */ - GPIO_FN(SCIFB0_RXD), GPIO_FN(CHSCIF0_HRX), /* Port124 */ @@ -2721,11 +2683,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MSIOF0_TXD), /* Port261 */ - GPIO_FN(SCIFB1_SCK_261), GPIO_FN(CHSCIF1_HSCK), /* Port262 */ - GPIO_FN(SCIFB2_SCK_262), /* Port263 - Port266 FN1 */ GPIO_FN(MSIOF1_SS2), @@ -2809,7 +2769,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port295 */ GPIO_FN(SDHID2_0), GPIO_FN(MSIOF4_TXD), - GPIO_FN(SCIFB2_TXD_295), GPIO_FN(MSIOF6_TXD), /* Port296 */ @@ -2830,10 +2789,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MSIOF4_SS1), /* Port297 - Port300 FN3 */ - GPIO_FN(SCIFB2_RXD_297), - GPIO_FN(SCIFB2_CTS_298), - GPIO_FN(SCIFB2_SCK_299), - GPIO_FN(SCIFB2_RTS_300), /* Port297 - Port300 FN4 */ GPIO_FN(MSIOF6_RXD), From f91663ff5619d73588fc91c3e7483bcb85570372 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:51:05 +0900 Subject: [PATCH 291/307] sh-pfc: r8a73a4: Remove IRQC function GPIOS The r8a73a4 board support will use the pinctrl API to control the external IRQ pins so remove the unused function GPIOS. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 58 ---------------------------- 1 file changed, 58 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 470b18f1a910..66fc7478a17e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2049,99 +2049,83 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(LCDD0), GPIO_FN(PDM2_CLK_0), GPIO_FN(DU0_DR0), - GPIO_FN(IRQ0), /* Port1 */ GPIO_FN(LCDD1), GPIO_FN(PDM2_DATA_1), GPIO_FN(DU0_DR19), - GPIO_FN(IRQ1), /* Port2 */ GPIO_FN(LCDD2), GPIO_FN(PDM3_CLK_2), GPIO_FN(DU0_DR2), - GPIO_FN(IRQ2), /* Port3 */ GPIO_FN(LCDD3), GPIO_FN(PDM3_DATA_3), GPIO_FN(DU0_DR3), - GPIO_FN(IRQ3), /* Port4 */ GPIO_FN(LCDD4), GPIO_FN(PDM4_CLK_4), GPIO_FN(DU0_DR4), - GPIO_FN(IRQ4), /* Port5 */ GPIO_FN(LCDD5), GPIO_FN(PDM4_DATA_5), GPIO_FN(DU0_DR5), - GPIO_FN(IRQ5), /* Port6 */ GPIO_FN(LCDD6), GPIO_FN(PDM0_OUTCLK_6), GPIO_FN(DU0_DR6), - GPIO_FN(IRQ6), /* Port7 */ GPIO_FN(LCDD7), GPIO_FN(PDM0_OUTDATA_7), GPIO_FN(DU0_DR7), - GPIO_FN(IRQ7), /* Port8 */ GPIO_FN(LCDD8), GPIO_FN(PDM1_OUTCLK_8), GPIO_FN(DU0_DG0), - GPIO_FN(IRQ8), /* Port9 */ GPIO_FN(LCDD9), GPIO_FN(PDM1_OUTDATA_9), GPIO_FN(DU0_DG1), - GPIO_FN(IRQ9), /* Port10 */ GPIO_FN(LCDD10), GPIO_FN(FSICCK), GPIO_FN(DU0_DG2), - GPIO_FN(IRQ10), /* Port11 */ GPIO_FN(LCDD11), GPIO_FN(FSICISLD), GPIO_FN(DU0_DG3), - GPIO_FN(IRQ11), /* Port12 */ GPIO_FN(LCDD12), GPIO_FN(FSICOMC), GPIO_FN(DU0_DG4), - GPIO_FN(IRQ12), /* Port13 */ GPIO_FN(LCDD13), GPIO_FN(FSICOLR), GPIO_FN(FSICILR), GPIO_FN(DU0_DG5), - GPIO_FN(IRQ13), /* Port14 */ GPIO_FN(LCDD14), GPIO_FN(FSICOBT), GPIO_FN(FSICIBT), GPIO_FN(DU0_DG6), - GPIO_FN(IRQ14), /* Port15 */ GPIO_FN(LCDD15), GPIO_FN(FSICOSLD), GPIO_FN(DU0_DG7), - GPIO_FN(IRQ15), /* Port16 */ GPIO_FN(LCDD16), @@ -2254,7 +2238,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(HSI_RX_WAKE), GPIO_FN(MSIOF3_SYNC), GPIO_FN(GenIO4), - GPIO_FN(IRQ40), /* Port67 */ GPIO_FN(HSI_RX_READY), @@ -2304,8 +2287,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(TXP2), GPIO_FN(COEX_0), GPIO_FN(COEX_1), - GPIO_FN(IRQ19), - GPIO_FN(IRQ18), /* Port96 - Port101 */ GPIO_FN(KEYIN0), @@ -2317,11 +2298,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port102 */ GPIO_FN(KEYIN6), - GPIO_FN(IRQ41), /* Port103 */ GPIO_FN(KEYIN7), - GPIO_FN(IRQ42), /* Port104 - Port108 */ GPIO_FN(KEYOUT0), @@ -2332,40 +2311,33 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port109 */ GPIO_FN(KEYOUT5), - GPIO_FN(IRQ43), /* Port110 */ GPIO_FN(KEYOUT6), - GPIO_FN(IRQ44), /* Port111 */ GPIO_FN(KEYOUT7), GPIO_FN(RFANAEN), - GPIO_FN(IRQ45), /* Port112 */ GPIO_FN(KEYIN8), GPIO_FN(KEYOUT8), GPIO_FN(SF_IRQ_04), - GPIO_FN(IRQ46), /* Port113 */ GPIO_FN(KEYIN9), GPIO_FN(KEYOUT9), GPIO_FN(SF_IRQ_05), - GPIO_FN(IRQ47), /* Port114 */ GPIO_FN(KEYIN10), GPIO_FN(KEYOUT10), GPIO_FN(SF_IRQ_06), - GPIO_FN(IRQ48), /* Port115 */ GPIO_FN(KEYIN11), GPIO_FN(KEYOUT11), GPIO_FN(SF_IRQ_07), - GPIO_FN(IRQ49), /* Port116 */ GPIO_FN(CSCIF0_TX), @@ -2444,10 +2416,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(STP_ISD_1), /* Port160 - Port178 */ - GPIO_FN(IRQ20), - GPIO_FN(IRQ21), - GPIO_FN(IRQ22), - GPIO_FN(IRQ23), GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2), @@ -2459,10 +2427,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MMCCMD0), GPIO_FN(MMCCLK0), GPIO_FN(MMCRST), - GPIO_FN(IRQ24), - GPIO_FN(IRQ25), - GPIO_FN(IRQ26), - GPIO_FN(IRQ27), /* Port192 - Port200 FN1 */ GPIO_FN(A10), @@ -2487,15 +2451,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MMCCMD1), /* Port192 - Port200 IRQ */ - GPIO_FN(IRQ31), - GPIO_FN(IRQ32), - GPIO_FN(IRQ33), - GPIO_FN(IRQ34), - GPIO_FN(IRQ35), - GPIO_FN(IRQ36), - GPIO_FN(IRQ37), - GPIO_FN(IRQ38), - GPIO_FN(IRQ39), /* Port201 */ GPIO_FN(A1), @@ -2752,7 +2707,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port290 */ GPIO_FN(SDHID1_1), GPIO_FN(STMDATA1_2), - GPIO_FN(IRQ51), /* Port291 - Port294 FN1 */ GPIO_FN(SDHID1_2), @@ -2774,7 +2728,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port296 */ GPIO_FN(SDHID2_1), GPIO_FN(MSIOF6_SS2), - GPIO_FN(IRQ52), /* Port297 - Port300 FN1 */ GPIO_FN(SDHID2_2), @@ -2798,7 +2751,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* Port301 */ GPIO_FN(SDHICD0), - GPIO_FN(IRQ50), /* Port302 - Port306 FN1 */ GPIO_FN(SDHID0_0), @@ -2822,16 +2774,6 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(STMCLK_1), /* Port320 - Port329 */ - GPIO_FN(IRQ16), - GPIO_FN(IRQ17), - GPIO_FN(IRQ28), - GPIO_FN(IRQ29), - GPIO_FN(IRQ30), - GPIO_FN(IRQ53), - GPIO_FN(IRQ54), - GPIO_FN(IRQ55), - GPIO_FN(IRQ56), - GPIO_FN(IRQ57), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From 9fdec7b1fe2b6a6566e92eb1f88800e06b555255 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:51:15 +0900 Subject: [PATCH 292/307] ARM: shmobile: r8a73a4: Remove SCIF function GPIOs Remove SCIF function GPIOs that have been deprecated by the pinctrl API. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/r8a73a4.h | 45 ------------------- 1 file changed, 45 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index 2d4af4af3634..703387a813db 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -200,55 +200,45 @@ enum { /* Port19 */ GPIO_FN_LCDD19, - GPIO_FN_SCIFB3_RTS_19, GPIO_FN_DU0_DB3, /* Port20 */ GPIO_FN_LCDD20, - GPIO_FN_SCIFB3_CTS_20, GPIO_FN_DU0_DB4, /* Port21 */ GPIO_FN_LCDD21, - GPIO_FN_SCIFB3_TXD_21, GPIO_FN_DU0_DB5, /* Port22 */ GPIO_FN_LCDD22, - GPIO_FN_SCIFB3_RXD_22, GPIO_FN_DU0_DB6, /* Port23 */ GPIO_FN_LCDD23, - GPIO_FN_SCIFB3_SCK_23, GPIO_FN_DU0_DB7, /* Port24 */ GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, - GPIO_FN_SCIFB1_RTS_24, GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N, /* Port25 */ GPIO_FN_LCDVSYN, - GPIO_FN_SCIFB1_CTS_25, GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N, /* Port26 */ GPIO_FN_LCDDCK, GPIO_FN_LCDWR, - GPIO_FN_SCIFB1_TXD_26, GPIO_FN_DU0_DOTCLKIN, /* Port27 */ GPIO_FN_LCDDISP, GPIO_FN_LCDRS, - GPIO_FN_SCIFB1_RXD_27, GPIO_FN_DU0_DOTCLKOUT, /* Port28 */ GPIO_FN_LCDRD_N, - GPIO_FN_SCIFB1_SCK_28, GPIO_FN_DU0_DOTCLKOUTB, /* Port29 */ @@ -262,48 +252,36 @@ enum { GPIO_FN_DU0_ODDF_N_CLAMP, /* Port32 */ - GPIO_FN_SCIFA0_RTS, GPIO_FN_SIM0_DET, GPIO_FN_CSCIF0_RTS, /* Port33 */ - GPIO_FN_SCIFA0_CTS, GPIO_FN_SIM1_DET, GPIO_FN_CSCIF0_CTS, /* Port34 */ - GPIO_FN_SCIFA0_SCK, GPIO_FN_SIM0_PWRON, GPIO_FN_CSCIF0_SCK, /* Port35 */ - GPIO_FN_SCIFA1_RTS, GPIO_FN_CSCIF1_RTS, /* Port36 */ - GPIO_FN_SCIFA1_CTS, GPIO_FN_CSCIF1_CTS, /* Port37 */ - GPIO_FN_SCIFA1_SCK, GPIO_FN_CSCIF1_SCK, /* Port38 */ - GPIO_FN_SCIFB0_RTS, GPIO_FN_TPU0TO1, - GPIO_FN_SCIFB3_RTS_38, GPIO_FN_CHSCIF0_HRTS, /* Port39 */ - GPIO_FN_SCIFB0_CTS, GPIO_FN_TPU0TO2, - GPIO_FN_SCIFB3_CTS_39, GPIO_FN_CHSCIF0_HCTS, /* Port40 */ - GPIO_FN_SCIFB0_SCK, GPIO_FN_TPU0TO3, - GPIO_FN_SCIFB3_SCK_40, GPIO_FN_CHSCIF0_HSCK, /* Port64 */ @@ -314,52 +292,44 @@ enum { /* Port66 */ GPIO_FN_HSI_RX_WAKE, - GPIO_FN_SCIFB2_CTS_66, GPIO_FN_MSIOF3_SYNC, GPIO_FN_GenIO4, GPIO_FN_IRQ40, /* Port67 */ GPIO_FN_HSI_RX_READY, - GPIO_FN_SCIFB1_TXD_67, GPIO_FN_GIO_OUT3_67, GPIO_FN_CHSCIF1_HTX, /* Port68 */ GPIO_FN_HSI_RX_FLAG, - GPIO_FN_SCIFB2_TXD_68, GPIO_FN_MSIOF3_TXD, GPIO_FN_GIO_OUT4_68, /* Port69 */ GPIO_FN_HSI_RX_DATA, - GPIO_FN_SCIFB2_RXD_69, GPIO_FN_MSIOF3_RXD, GPIO_FN_GIO_OUT5_69, /* Port70 */ GPIO_FN_HSI_TX_FLAG, - GPIO_FN_SCIFB1_RTS_70, GPIO_FN_GIO_OUT1_70, GPIO_FN_HSIC_TSTCLK0, GPIO_FN_CHSCIF1_HRTS, /* Port71 */ GPIO_FN_HSI_TX_DATA, - GPIO_FN_SCIFB1_CTS_71, GPIO_FN_GIO_OUT2_71, GPIO_FN_HSIC_TSTCLK1, GPIO_FN_CHSCIF1_HCTS, /* Port72 */ GPIO_FN_HSI_TX_WAKE, - GPIO_FN_SCIFB1_RXD_72, GPIO_FN_GenIO8, GPIO_FN_CHSCIF1_HRX, /* Port73 */ GPIO_FN_HSI_TX_READY, - GPIO_FN_SCIFB2_RTS_73, GPIO_FN_MSIOF3_SCK, GPIO_FN_GIO_OUT0_73, @@ -438,36 +408,28 @@ enum { GPIO_FN_IRQ49, /* Port116 */ - GPIO_FN_SCIFA0_TXD, GPIO_FN_CSCIF0_TX, /* Port117 */ - GPIO_FN_SCIFA0_RXD, GPIO_FN_CSCIF0_RX, /* Port118 */ - GPIO_FN_SCIFA1_TXD, GPIO_FN_CSCIF1_TX, /* Port119 */ - GPIO_FN_SCIFA1_RXD, GPIO_FN_CSCIF1_RX, /* Port120 */ GPIO_FN_SF_PORT_1_120, - GPIO_FN_SCIFB3_RXD_120, GPIO_FN_DU0_CDE, /* Port121 */ GPIO_FN_SF_PORT_0_121, - GPIO_FN_SCIFB3_TXD_121, /* Port122 */ - GPIO_FN_SCIFB0_TXD, GPIO_FN_CHSCIF0_HTX, /* Port123 */ - GPIO_FN_SCIFB0_RXD, GPIO_FN_CHSCIF0_HRX, /* Port124 */ @@ -761,11 +723,9 @@ enum { GPIO_FN_MSIOF0_TXD, /* Port261 */ - GPIO_FN_SCIFB1_SCK_261, GPIO_FN_CHSCIF1_HSCK, /* Port262 */ - GPIO_FN_SCIFB2_SCK_262, /* Port263 - Port266 FN1 */ GPIO_FN_MSIOF1_SS2, @@ -849,7 +809,6 @@ enum { /* Port295 */ GPIO_FN_SDHID2_0, GPIO_FN_MSIOF4_TXD, - GPIO_FN_SCIFB2_TXD_295, GPIO_FN_MSIOF6_TXD, /* Port296 */ @@ -870,10 +829,6 @@ enum { GPIO_FN_MSIOF4_SS1, /* Port297 - Port300 FN3 */ - GPIO_FN_SCIFB2_RXD_297, - GPIO_FN_SCIFB2_CTS_298, - GPIO_FN_SCIFB2_SCK_299, - GPIO_FN_SCIFB2_RTS_300, /* Port297 - Port300 FN4 */ GPIO_FN_MSIOF6_RXD, From 5260a7a36356b0b0b34aeaff8e9fc6a5a7fff9e7 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:51:24 +0900 Subject: [PATCH 293/307] ARM: shmobile: r8a73a4: Remove IRQC function GPIOs Remove IRQ pin function GPIOs that have been deprecated by the pinctrl API. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/r8a73a4.h | 58 ------------------- 1 file changed, 58 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index 703387a813db..9162e8645110 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -89,99 +89,83 @@ enum { GPIO_FN_LCDD0 = 330, GPIO_FN_PDM2_CLK_0, GPIO_FN_DU0_DR0, - GPIO_FN_IRQ0, /* Port1 */ GPIO_FN_LCDD1, GPIO_FN_PDM2_DATA_1, GPIO_FN_DU0_DR19, - GPIO_FN_IRQ1, /* Port2 */ GPIO_FN_LCDD2, GPIO_FN_PDM3_CLK_2, GPIO_FN_DU0_DR2, - GPIO_FN_IRQ2, /* Port3 */ GPIO_FN_LCDD3, GPIO_FN_PDM3_DATA_3, GPIO_FN_DU0_DR3, - GPIO_FN_IRQ3, /* Port4 */ GPIO_FN_LCDD4, GPIO_FN_PDM4_CLK_4, GPIO_FN_DU0_DR4, - GPIO_FN_IRQ4, /* Port5 */ GPIO_FN_LCDD5, GPIO_FN_PDM4_DATA_5, GPIO_FN_DU0_DR5, - GPIO_FN_IRQ5, /* Port6 */ GPIO_FN_LCDD6, GPIO_FN_PDM0_OUTCLK_6, GPIO_FN_DU0_DR6, - GPIO_FN_IRQ6, /* Port7 */ GPIO_FN_LCDD7, GPIO_FN_PDM0_OUTDATA_7, GPIO_FN_DU0_DR7, - GPIO_FN_IRQ7, /* Port8 */ GPIO_FN_LCDD8, GPIO_FN_PDM1_OUTCLK_8, GPIO_FN_DU0_DG0, - GPIO_FN_IRQ8, /* Port9 */ GPIO_FN_LCDD9, GPIO_FN_PDM1_OUTDATA_9, GPIO_FN_DU0_DG1, - GPIO_FN_IRQ9, /* Port10 */ GPIO_FN_LCDD10, GPIO_FN_FSICCK, GPIO_FN_DU0_DG2, - GPIO_FN_IRQ10, /* Port11 */ GPIO_FN_LCDD11, GPIO_FN_FSICISLD, GPIO_FN_DU0_DG3, - GPIO_FN_IRQ11, /* Port12 */ GPIO_FN_LCDD12, GPIO_FN_FSICOMC, GPIO_FN_DU0_DG4, - GPIO_FN_IRQ12, /* Port13 */ GPIO_FN_LCDD13, GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_DU0_DG5, - GPIO_FN_IRQ13, /* Port14 */ GPIO_FN_LCDD14, GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_DU0_DG6, - GPIO_FN_IRQ14, /* Port15 */ GPIO_FN_LCDD15, GPIO_FN_FSICOSLD, GPIO_FN_DU0_DG7, - GPIO_FN_IRQ15, /* Port16 */ GPIO_FN_LCDD16, @@ -294,7 +278,6 @@ enum { GPIO_FN_HSI_RX_WAKE, GPIO_FN_MSIOF3_SYNC, GPIO_FN_GenIO4, - GPIO_FN_IRQ40, /* Port67 */ GPIO_FN_HSI_RX_READY, @@ -344,8 +327,6 @@ enum { GPIO_FN_TXP2, GPIO_FN_COEX_0, GPIO_FN_COEX_1, - GPIO_FN_IRQ19, - GPIO_FN_IRQ18, /* Port96 - Port101 */ GPIO_FN_KEYIN0, @@ -357,11 +338,9 @@ enum { /* Port102 */ GPIO_FN_KEYIN6, - GPIO_FN_IRQ41, /* Port103 */ GPIO_FN_KEYIN7, - GPIO_FN_IRQ42, /* Port104 - Port108 */ GPIO_FN_KEYOUT0, @@ -372,40 +351,33 @@ enum { /* Port109 */ GPIO_FN_KEYOUT5, - GPIO_FN_IRQ43, /* Port110 */ GPIO_FN_KEYOUT6, - GPIO_FN_IRQ44, /* Port111 */ GPIO_FN_KEYOUT7, GPIO_FN_RFANAEN, - GPIO_FN_IRQ45, /* Port112 */ GPIO_FN_KEYIN8, GPIO_FN_KEYOUT8, GPIO_FN_SF_IRQ_04, - GPIO_FN_IRQ46, /* Port113 */ GPIO_FN_KEYIN9, GPIO_FN_KEYOUT9, GPIO_FN_SF_IRQ_05, - GPIO_FN_IRQ47, /* Port114 */ GPIO_FN_KEYIN10, GPIO_FN_KEYOUT10, GPIO_FN_SF_IRQ_06, - GPIO_FN_IRQ48, /* Port115 */ GPIO_FN_KEYIN11, GPIO_FN_KEYOUT11, GPIO_FN_SF_IRQ_07, - GPIO_FN_IRQ49, /* Port116 */ GPIO_FN_CSCIF0_TX, @@ -484,10 +456,6 @@ enum { GPIO_FN_STP_ISD_1, /* Port160 - Port178 */ - GPIO_FN_IRQ20, - GPIO_FN_IRQ21, - GPIO_FN_IRQ22, - GPIO_FN_IRQ23, GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2, @@ -499,10 +467,6 @@ enum { GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0, GPIO_FN_MMCRST, - GPIO_FN_IRQ24, - GPIO_FN_IRQ25, - GPIO_FN_IRQ26, - GPIO_FN_IRQ27, /* Port192 - Port200 FN1 */ GPIO_FN_A10, @@ -527,15 +491,6 @@ enum { GPIO_FN_MMCCMD1, /* Port192 - Port200 IRQ */ - GPIO_FN_IRQ31, - GPIO_FN_IRQ32, - GPIO_FN_IRQ33, - GPIO_FN_IRQ34, - GPIO_FN_IRQ35, - GPIO_FN_IRQ36, - GPIO_FN_IRQ37, - GPIO_FN_IRQ38, - GPIO_FN_IRQ39, /* Port201 */ GPIO_FN_A1, @@ -792,7 +747,6 @@ enum { /* Port290 */ GPIO_FN_SDHID1_1, GPIO_FN_STMDATA1_2, - GPIO_FN_IRQ51, /* Port291 - Port294 FN1 */ GPIO_FN_SDHID1_2, @@ -814,7 +768,6 @@ enum { /* Port296 */ GPIO_FN_SDHID2_1, GPIO_FN_MSIOF6_SS2, - GPIO_FN_IRQ52, /* Port297 - Port300 FN1 */ GPIO_FN_SDHID2_2, @@ -838,7 +791,6 @@ enum { /* Port301 */ GPIO_FN_SDHICD0, - GPIO_FN_IRQ50, /* Port302 - Port306 FN1 */ GPIO_FN_SDHID0_0, @@ -862,16 +814,6 @@ enum { GPIO_FN_STMCLK_1, /* Port320 - Port329 */ - GPIO_FN_IRQ16, - GPIO_FN_IRQ17, - GPIO_FN_IRQ28, - GPIO_FN_IRQ29, - GPIO_FN_IRQ30, - GPIO_FN_IRQ53, - GPIO_FN_IRQ54, - GPIO_FN_IRQ55, - GPIO_FN_IRQ56, - GPIO_FN_IRQ57, }; void r8a73a4_add_standard_devices(void); From 3e36ab671c36d0e9471c75d6e8b78926dc153f6b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:51:34 +0900 Subject: [PATCH 294/307] sh-pfc: r8a73a4: Remove function GPIOs All r8a73a4 platforms use the pinctrl API to control pin functions. Function GPIOs are no longer needed. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 737 --------------------------- 1 file changed, 737 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 66fc7478a17e..464c5f9ce9fa 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2042,740 +2042,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scifb3), }; -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) - -static const struct pinmux_func pinmux_func_gpios[] = { - /* Port0 */ - GPIO_FN(LCDD0), - GPIO_FN(PDM2_CLK_0), - GPIO_FN(DU0_DR0), - - /* Port1 */ - GPIO_FN(LCDD1), - GPIO_FN(PDM2_DATA_1), - GPIO_FN(DU0_DR19), - - /* Port2 */ - GPIO_FN(LCDD2), - GPIO_FN(PDM3_CLK_2), - GPIO_FN(DU0_DR2), - - /* Port3 */ - GPIO_FN(LCDD3), - GPIO_FN(PDM3_DATA_3), - GPIO_FN(DU0_DR3), - - /* Port4 */ - GPIO_FN(LCDD4), - GPIO_FN(PDM4_CLK_4), - GPIO_FN(DU0_DR4), - - /* Port5 */ - GPIO_FN(LCDD5), - GPIO_FN(PDM4_DATA_5), - GPIO_FN(DU0_DR5), - - /* Port6 */ - GPIO_FN(LCDD6), - GPIO_FN(PDM0_OUTCLK_6), - GPIO_FN(DU0_DR6), - - /* Port7 */ - GPIO_FN(LCDD7), - GPIO_FN(PDM0_OUTDATA_7), - GPIO_FN(DU0_DR7), - - /* Port8 */ - GPIO_FN(LCDD8), - GPIO_FN(PDM1_OUTCLK_8), - GPIO_FN(DU0_DG0), - - /* Port9 */ - GPIO_FN(LCDD9), - GPIO_FN(PDM1_OUTDATA_9), - GPIO_FN(DU0_DG1), - - /* Port10 */ - GPIO_FN(LCDD10), - GPIO_FN(FSICCK), - GPIO_FN(DU0_DG2), - - /* Port11 */ - GPIO_FN(LCDD11), - GPIO_FN(FSICISLD), - GPIO_FN(DU0_DG3), - - /* Port12 */ - GPIO_FN(LCDD12), - GPIO_FN(FSICOMC), - GPIO_FN(DU0_DG4), - - /* Port13 */ - GPIO_FN(LCDD13), - GPIO_FN(FSICOLR), - GPIO_FN(FSICILR), - GPIO_FN(DU0_DG5), - - /* Port14 */ - GPIO_FN(LCDD14), - GPIO_FN(FSICOBT), - GPIO_FN(FSICIBT), - GPIO_FN(DU0_DG6), - - /* Port15 */ - GPIO_FN(LCDD15), - GPIO_FN(FSICOSLD), - GPIO_FN(DU0_DG7), - - /* Port16 */ - GPIO_FN(LCDD16), - GPIO_FN(TPU1TO1), - GPIO_FN(DU0_DB0), - - /* Port17 */ - GPIO_FN(LCDD17), - GPIO_FN(SF_IRQ_00), - GPIO_FN(DU0_DB1), - - /* Port18 */ - GPIO_FN(LCDD18), - GPIO_FN(SF_IRQ_01), - GPIO_FN(DU0_DB2), - - /* Port19 */ - GPIO_FN(LCDD19), - GPIO_FN(DU0_DB3), - - /* Port20 */ - GPIO_FN(LCDD20), - GPIO_FN(DU0_DB4), - - /* Port21 */ - GPIO_FN(LCDD21), - GPIO_FN(DU0_DB5), - - /* Port22 */ - GPIO_FN(LCDD22), - GPIO_FN(DU0_DB6), - - /* Port23 */ - GPIO_FN(LCDD23), - GPIO_FN(DU0_DB7), - - /* Port24 */ - GPIO_FN(LCDHSYN), - GPIO_FN(LCDCS), - GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N), - - /* Port25 */ - GPIO_FN(LCDVSYN), - GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N), - - /* Port26 */ - GPIO_FN(LCDDCK), - GPIO_FN(LCDWR), - GPIO_FN(DU0_DOTCLKIN), - - /* Port27 */ - GPIO_FN(LCDDISP), - GPIO_FN(LCDRS), - GPIO_FN(DU0_DOTCLKOUT), - - /* Port28 */ - GPIO_FN(LCDRD_N), - GPIO_FN(DU0_DOTCLKOUTB), - - /* Port29 */ - GPIO_FN(LCDLCLK), - GPIO_FN(SF_IRQ_02), - GPIO_FN(DU0_DISP_CSYNC_N_DE), - - /* Port30 */ - GPIO_FN(LCDDON), - GPIO_FN(SF_IRQ_03), - GPIO_FN(DU0_ODDF_N_CLAMP), - - /* Port32 */ - GPIO_FN(SIM0_DET), - GPIO_FN(CSCIF0_RTS), - - /* Port33 */ - GPIO_FN(SIM1_DET), - GPIO_FN(CSCIF0_CTS), - - /* Port34 */ - GPIO_FN(SIM0_PWRON), - GPIO_FN(CSCIF0_SCK), - - /* Port35 */ - GPIO_FN(CSCIF1_RTS), - - /* Port36 */ - GPIO_FN(CSCIF1_CTS), - - /* Port37 */ - GPIO_FN(CSCIF1_SCK), - - /* Port38 */ - GPIO_FN(TPU0TO1), - GPIO_FN(CHSCIF0_HRTS), - - /* Port39 */ - GPIO_FN(TPU0TO2), - GPIO_FN(CHSCIF0_HCTS), - - /* Port40 */ - GPIO_FN(TPU0TO3), - GPIO_FN(CHSCIF0_HSCK), - - /* Port64 */ - GPIO_FN(PDM0_DATA), - - /* Port65 */ - GPIO_FN(PDM1_DATA), - - /* Port66 */ - GPIO_FN(HSI_RX_WAKE), - GPIO_FN(MSIOF3_SYNC), - GPIO_FN(GenIO4), - - /* Port67 */ - GPIO_FN(HSI_RX_READY), - GPIO_FN(GIO_OUT3_67), - GPIO_FN(CHSCIF1_HTX), - - /* Port68 */ - GPIO_FN(HSI_RX_FLAG), - GPIO_FN(MSIOF3_TXD), - GPIO_FN(GIO_OUT4_68), - - /* Port69 */ - GPIO_FN(HSI_RX_DATA), - GPIO_FN(MSIOF3_RXD), - GPIO_FN(GIO_OUT5_69), - - /* Port70 */ - GPIO_FN(HSI_TX_FLAG), - GPIO_FN(GIO_OUT1_70), - GPIO_FN(HSIC_TSTCLK0), - GPIO_FN(CHSCIF1_HRTS), - - /* Port71 */ - GPIO_FN(HSI_TX_DATA), - GPIO_FN(GIO_OUT2_71), - GPIO_FN(HSIC_TSTCLK1), - GPIO_FN(CHSCIF1_HCTS), - - /* Port72 */ - GPIO_FN(HSI_TX_WAKE), - GPIO_FN(GenIO8), - GPIO_FN(CHSCIF1_HRX), - - /* Port73 */ - GPIO_FN(HSI_TX_READY), - GPIO_FN(MSIOF3_SCK), - GPIO_FN(GIO_OUT0_73), - - /* Port74 - Port85 */ - GPIO_FN(IRDA_OUT), - GPIO_FN(IRDA_IN), - GPIO_FN(IRDA_FIRSEL), - GPIO_FN(TPU0TO0), - GPIO_FN(DIGRFEN), - GPIO_FN(GPS_TIMESTAMP), - GPIO_FN(TXP), - GPIO_FN(TXP2), - GPIO_FN(COEX_0), - GPIO_FN(COEX_1), - - /* Port96 - Port101 */ - GPIO_FN(KEYIN0), - GPIO_FN(KEYIN1), - GPIO_FN(KEYIN2), - GPIO_FN(KEYIN3), - GPIO_FN(KEYIN4), - GPIO_FN(KEYIN5), - - /* Port102 */ - GPIO_FN(KEYIN6), - - /* Port103 */ - GPIO_FN(KEYIN7), - - /* Port104 - Port108 */ - GPIO_FN(KEYOUT0), - GPIO_FN(KEYOUT1), - GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT3), - GPIO_FN(KEYOUT4), - - /* Port109 */ - GPIO_FN(KEYOUT5), - - /* Port110 */ - GPIO_FN(KEYOUT6), - - /* Port111 */ - GPIO_FN(KEYOUT7), - GPIO_FN(RFANAEN), - - /* Port112 */ - GPIO_FN(KEYIN8), - GPIO_FN(KEYOUT8), - GPIO_FN(SF_IRQ_04), - - /* Port113 */ - GPIO_FN(KEYIN9), - GPIO_FN(KEYOUT9), - GPIO_FN(SF_IRQ_05), - - /* Port114 */ - GPIO_FN(KEYIN10), - GPIO_FN(KEYOUT10), - GPIO_FN(SF_IRQ_06), - - /* Port115 */ - GPIO_FN(KEYIN11), - GPIO_FN(KEYOUT11), - GPIO_FN(SF_IRQ_07), - - /* Port116 */ - GPIO_FN(CSCIF0_TX), - - /* Port117 */ - GPIO_FN(CSCIF0_RX), - - /* Port118 */ - GPIO_FN(CSCIF1_TX), - - /* Port119 */ - GPIO_FN(CSCIF1_RX), - - /* Port120 */ - GPIO_FN(SF_PORT_1_120), - GPIO_FN(DU0_CDE), - - /* Port121 */ - GPIO_FN(SF_PORT_0_121), - - /* Port122 */ - GPIO_FN(CHSCIF0_HTX), - - /* Port123 */ - GPIO_FN(CHSCIF0_HRX), - - /* Port124 */ - GPIO_FN(ISP_STROBE_124), - - /* Port125 */ - GPIO_FN(STP_ISD_0), - GPIO_FN(PDM4_CLK_125), - GPIO_FN(MSIOF2_TXD), - GPIO_FN(SIM0_VOLTSEL0), - - /* Port126 */ - GPIO_FN(TS_SDEN), - GPIO_FN(MSIOF7_SYNC), - GPIO_FN(STP_ISEN_1), - - /* Port128 */ - GPIO_FN(STP_ISEN_0), - GPIO_FN(PDM1_OUTDATA_128), - GPIO_FN(MSIOF2_SYNC), - GPIO_FN(SIM1_VOLTSEL1), - - /* Port129 */ - GPIO_FN(TS_SPSYNC), - GPIO_FN(MSIOF7_RXD), - GPIO_FN(STP_ISSYNC_1), - - /* Port130 */ - GPIO_FN(STP_ISSYNC_0), - GPIO_FN(PDM4_DATA_130), - GPIO_FN(MSIOF2_RXD), - GPIO_FN(SIM0_VOLTSEL1), - - /* Port131 */ - GPIO_FN(STP_OPWM_0), - GPIO_FN(SIM1_PWRON), - - /* Port132 */ - GPIO_FN(TS_SCK), - GPIO_FN(MSIOF7_SCK), - GPIO_FN(STP_ISCLK_1), - - /* Port133 */ - GPIO_FN(STP_ISCLK_0), - GPIO_FN(PDM1_OUTCLK_133), - GPIO_FN(MSIOF2_SCK), - GPIO_FN(SIM1_VOLTSEL0), - - /* Port134 */ - GPIO_FN(TS_SDAT), - GPIO_FN(MSIOF7_TXD), - GPIO_FN(STP_ISD_1), - - /* Port160 - Port178 */ - GPIO_FN(MMCD0_0), - GPIO_FN(MMCD0_1), - GPIO_FN(MMCD0_2), - GPIO_FN(MMCD0_3), - GPIO_FN(MMCD0_4), - GPIO_FN(MMCD0_5), - GPIO_FN(MMCD0_6), - GPIO_FN(MMCD0_7), - GPIO_FN(MMCCMD0), - GPIO_FN(MMCCLK0), - GPIO_FN(MMCRST), - - /* Port192 - Port200 FN1 */ - GPIO_FN(A10), - GPIO_FN(A9), - GPIO_FN(A8), - GPIO_FN(A7), - GPIO_FN(A6), - GPIO_FN(A5), - GPIO_FN(A4), - GPIO_FN(A3), - GPIO_FN(A2), - - /* Port192 - Port200 FN2 */ - GPIO_FN(MMCD1_7), - GPIO_FN(MMCD1_6), - GPIO_FN(MMCD1_5), - GPIO_FN(MMCD1_4), - GPIO_FN(MMCD1_3), - GPIO_FN(MMCD1_2), - GPIO_FN(MMCD1_1), - GPIO_FN(MMCD1_0), - GPIO_FN(MMCCMD1), - - /* Port192 - Port200 IRQ */ - - /* Port201 */ - GPIO_FN(A1), - - /* Port202 */ - GPIO_FN(A0), - GPIO_FN(BS), - - /* Port203 */ - GPIO_FN(CKO), - GPIO_FN(MMCCLK1), - - /* Port204 */ - GPIO_FN(CS0_N), - GPIO_FN(SIM0_GPO1), - - /* Port205 */ - GPIO_FN(CS2_N), - GPIO_FN(SIM0_GPO2), - - /* Port206 */ - GPIO_FN(CS4_N), - GPIO_FN(VIO_VD), - GPIO_FN(SIM1_GPO0), - - /* Port207 - Port212 FN1 */ - GPIO_FN(D15), - GPIO_FN(D14), - GPIO_FN(D13), - GPIO_FN(D12), - GPIO_FN(D11), - GPIO_FN(D10), - - /* Port207 - Port212 FN5 */ - GPIO_FN(GIO_OUT15), - GPIO_FN(GIO_OUT14), - GPIO_FN(GIO_OUT13), - GPIO_FN(GIO_OUT12), - GPIO_FN(WGM_TXP2), - GPIO_FN(WGM_GPS_TIMEM_ASK_RFCLK), - - /* Port213 - Port222 FN1 */ - GPIO_FN(D9), - GPIO_FN(D8), - GPIO_FN(D7), - GPIO_FN(D6), - GPIO_FN(D5), - GPIO_FN(D4), - GPIO_FN(D3), - GPIO_FN(D2), - GPIO_FN(D1), - GPIO_FN(D0), - - /* Port213 - Port222 FN2 */ - GPIO_FN(VIO_D9), - GPIO_FN(VIO_D8), - GPIO_FN(VIO_D7), - GPIO_FN(VIO_D6), - GPIO_FN(VIO_D5), - GPIO_FN(VIO_D4), - GPIO_FN(VIO_D3), - GPIO_FN(VIO_D2), - GPIO_FN(VIO_D1), - GPIO_FN(VIO_D0), - - /* Port213 - Port222 FN5 */ - GPIO_FN(GIO_OUT9), - GPIO_FN(GIO_OUT8), - GPIO_FN(GIO_OUT7), - GPIO_FN(GIO_OUT6), - GPIO_FN(GIO_OUT5_217), - GPIO_FN(GIO_OUT4_218), - GPIO_FN(GIO_OUT3_219), - GPIO_FN(GIO_OUT2_220), - GPIO_FN(GIO_OUT1_221), - GPIO_FN(GIO_OUT0_222), - - /* Port224 */ - GPIO_FN(RDWR_224), - GPIO_FN(VIO_HD), - GPIO_FN(SIM1_GPO2), - - /* Port225 */ - GPIO_FN(RD_N), - - /* Port226 */ - GPIO_FN(WAIT_N), - GPIO_FN(VIO_CLK), - GPIO_FN(SIM1_GPO1), - - /* Port227 */ - GPIO_FN(WE0_N), - GPIO_FN(RDWR_227), - - /* Port228 */ - GPIO_FN(WE1_N), - GPIO_FN(SIM0_GPO0), - - /* Port229 */ - GPIO_FN(PWMO), - GPIO_FN(VIO_CKO1_229), - - /* Port230 */ - GPIO_FN(SLIM_CLK), - GPIO_FN(VIO_CKO4_230), - - /* Port231 */ - GPIO_FN(SLIM_DATA), - GPIO_FN(VIO_CKO5_231), - - /* Port232 */ - GPIO_FN(VIO_CKO2_232), - GPIO_FN(SF_PORT_0_232), - - /* Port233 */ - GPIO_FN(VIO_CKO3_233), - GPIO_FN(SF_PORT_1_233), - - /* Port234 */ - GPIO_FN(FSIACK), - GPIO_FN(PDM3_CLK_234), - GPIO_FN(ISP_IRIS1_234), - - /* Port235 */ - GPIO_FN(FSIAISLD), - GPIO_FN(PDM3_DATA_235), - - /* Port236 */ - GPIO_FN(FSIAOMC), - GPIO_FN(PDM0_OUTCLK_236), - GPIO_FN(ISP_IRIS0_236), - - /* Port237 */ - GPIO_FN(FSIAOLR), - GPIO_FN(FSIAILR), - - /* Port238 */ - GPIO_FN(FSIAOBT), - GPIO_FN(FSIAIBT), - - /* Port239 */ - GPIO_FN(FSIAOSLD), - GPIO_FN(PDM0_OUTDATA_239), - - /* Port240 */ - GPIO_FN(FSIBISLD), - - /* Port241 */ - GPIO_FN(FSIBOLR), - GPIO_FN(FSIBILR), - - /* Port242 */ - GPIO_FN(FSIBOMC), - GPIO_FN(ISP_SHUTTER1_242), - - /* Port243 */ - GPIO_FN(FSIBOBT), - GPIO_FN(FSIBIBT), - - /* Port244 */ - GPIO_FN(FSIBOSLD), - GPIO_FN(FSIASPDIF), - - /* Port245 */ - GPIO_FN(FSIBCK), - GPIO_FN(ISP_SHUTTER0_245), - - /* Port246 - Port250 FN1 */ - GPIO_FN(ISP_IRIS1_246), - GPIO_FN(ISP_IRIS0_247), - GPIO_FN(ISP_SHUTTER1_248), - GPIO_FN(ISP_SHUTTER0_249), - GPIO_FN(ISP_STROBE_250), - - /* Port256 - Port258 */ - GPIO_FN(MSIOF0_SYNC), - GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_SCK), - - /* Port259 */ - GPIO_FN(MSIOF0_SS2), - GPIO_FN(VIO_CKO3_259), - - /* Port260 */ - GPIO_FN(MSIOF0_TXD), - - /* Port261 */ - GPIO_FN(CHSCIF1_HSCK), - - /* Port262 */ - - /* Port263 - Port266 FN1 */ - GPIO_FN(MSIOF1_SS2), - GPIO_FN(MSIOF1_TXD), - GPIO_FN(MSIOF1_RXD), - GPIO_FN(MSIOF1_SS1), - - /* Port263 - Port266 FN4 */ - GPIO_FN(MSIOF5_SS2), - GPIO_FN(MSIOF5_TXD), - GPIO_FN(MSIOF5_RXD), - GPIO_FN(MSIOF5_SS1), - - /* Port267 */ - GPIO_FN(MSIOF0_SS1), - - /* Port268 */ - GPIO_FN(MSIOF1_SCK), - GPIO_FN(MSIOF5_SCK), - - /* Port269 */ - GPIO_FN(MSIOF1_SYNC), - GPIO_FN(MSIOF5_SYNC), - - /* Port270 - Port273 FN1 */ - GPIO_FN(MSIOF2_SS1), - GPIO_FN(MSIOF2_SS2), - GPIO_FN(MSIOF3_SS2), - GPIO_FN(MSIOF3_SS1), - - /* Port270 - Port273 FN3 */ - GPIO_FN(VIO_CKO5_270), - GPIO_FN(VIO_CKO2_271), - GPIO_FN(VIO_CKO1_272), - GPIO_FN(VIO_CKO4_273), - - /* Port274 */ - GPIO_FN(MSIOF4_SS2), - GPIO_FN(TPU1TO0), - - /* Port275 - Port280 */ - GPIO_FN(IC_DP), - GPIO_FN(SIM0_RST), - GPIO_FN(IC_DM), - GPIO_FN(SIM0_BSICOMP), - GPIO_FN(SIM0_CLK), - GPIO_FN(SIM0_IO), - - /* Port281 */ - GPIO_FN(SIM1_IO), - GPIO_FN(PDM2_DATA_281), - - /* Port282 */ - GPIO_FN(SIM1_CLK), - GPIO_FN(PDM2_CLK_282), - - /* Port283 */ - GPIO_FN(SIM1_RST), - - /* Port289 */ - GPIO_FN(SDHID1_0), - GPIO_FN(STMDATA0_2), - - /* Port290 */ - GPIO_FN(SDHID1_1), - GPIO_FN(STMDATA1_2), - - /* Port291 - Port294 FN1 */ - GPIO_FN(SDHID1_2), - GPIO_FN(SDHID1_3), - GPIO_FN(SDHICLK1), - GPIO_FN(SDHICMD1), - - /* Port291 - Port294 FN3 */ - GPIO_FN(STMDATA2_2), - GPIO_FN(STMDATA3_2), - GPIO_FN(STMCLK_2), - GPIO_FN(STMSIDI_2), - - /* Port295 */ - GPIO_FN(SDHID2_0), - GPIO_FN(MSIOF4_TXD), - GPIO_FN(MSIOF6_TXD), - - /* Port296 */ - GPIO_FN(SDHID2_1), - GPIO_FN(MSIOF6_SS2), - - /* Port297 - Port300 FN1 */ - GPIO_FN(SDHID2_2), - GPIO_FN(SDHID2_3), - GPIO_FN(SDHICLK2), - GPIO_FN(SDHICMD2), - - /* Port297 - Port300 FN2 */ - GPIO_FN(MSIOF4_RXD), - GPIO_FN(MSIOF4_SYNC), - GPIO_FN(MSIOF4_SCK), - GPIO_FN(MSIOF4_SS1), - - /* Port297 - Port300 FN3 */ - - /* Port297 - Port300 FN4 */ - GPIO_FN(MSIOF6_RXD), - GPIO_FN(MSIOF6_SYNC), - GPIO_FN(MSIOF6_SCK), - GPIO_FN(MSIOF6_SS1), - - /* Port301 */ - GPIO_FN(SDHICD0), - - /* Port302 - Port306 FN1 */ - GPIO_FN(SDHID0_0), - GPIO_FN(SDHID0_1), - GPIO_FN(SDHID0_2), - GPIO_FN(SDHID0_3), - GPIO_FN(SDHICMD0), - - /* Port302 - Port306 FN3 */ - GPIO_FN(STMDATA0_1), - GPIO_FN(STMDATA1_1), - GPIO_FN(STMDATA2_1), - GPIO_FN(STMDATA3_1), - GPIO_FN(STMSIDI_1), - - /* Port307 */ - GPIO_FN(SDHIWP0), - - /* Port308 */ - GPIO_FN(SDHICLK0), - GPIO_FN(STMCLK_1), - - /* Port320 - Port329 */ -}; - static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), @@ -3456,9 +2722,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, From 17924ac1b9d42da19320b35daa0fe6ccddd3c3c2 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:51:43 +0900 Subject: [PATCH 295/307] ARM: shmobile: r8a73a4: Remove all GPIO enums Function GPIOs are not used anymore, and all code use the GPIO numbers directly. Remove the GPIOs enumeration. Signed-off-by: Magnus Damm Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/r8a73a4.h | 815 ------------------ 1 file changed, 815 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index 9162e8645110..f043103e32c9 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -1,821 +1,6 @@ #ifndef __ASM_R8A73A4_H__ #define __ASM_R8A73A4_H__ -/* - * Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - - /* PORT */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, - - GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, - GPIO_PORT125, GPIO_PORT126, GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, - - GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, - GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, - - GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, - GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, - - GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, - GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, - - GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, - GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, - - GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT224, - GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, - - GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, - GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, - - GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, - GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, - - GPIO_PORT250, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, - - GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, - GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, - - GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, - GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, - - GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, GPIO_PORT283, - GPIO_PORT288, GPIO_PORT289, - - GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, - GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, - - GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, - GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, - - GPIO_PORT320, GPIO_PORT321, GPIO_PORT322, GPIO_PORT323, GPIO_PORT324, - GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329, - - /* Port0 */ - GPIO_FN_LCDD0 = 330, - GPIO_FN_PDM2_CLK_0, - GPIO_FN_DU0_DR0, - - /* Port1 */ - GPIO_FN_LCDD1, - GPIO_FN_PDM2_DATA_1, - GPIO_FN_DU0_DR19, - - /* Port2 */ - GPIO_FN_LCDD2, - GPIO_FN_PDM3_CLK_2, - GPIO_FN_DU0_DR2, - - /* Port3 */ - GPIO_FN_LCDD3, - GPIO_FN_PDM3_DATA_3, - GPIO_FN_DU0_DR3, - - /* Port4 */ - GPIO_FN_LCDD4, - GPIO_FN_PDM4_CLK_4, - GPIO_FN_DU0_DR4, - - /* Port5 */ - GPIO_FN_LCDD5, - GPIO_FN_PDM4_DATA_5, - GPIO_FN_DU0_DR5, - - /* Port6 */ - GPIO_FN_LCDD6, - GPIO_FN_PDM0_OUTCLK_6, - GPIO_FN_DU0_DR6, - - /* Port7 */ - GPIO_FN_LCDD7, - GPIO_FN_PDM0_OUTDATA_7, - GPIO_FN_DU0_DR7, - - /* Port8 */ - GPIO_FN_LCDD8, - GPIO_FN_PDM1_OUTCLK_8, - GPIO_FN_DU0_DG0, - - /* Port9 */ - GPIO_FN_LCDD9, - GPIO_FN_PDM1_OUTDATA_9, - GPIO_FN_DU0_DG1, - - /* Port10 */ - GPIO_FN_LCDD10, - GPIO_FN_FSICCK, - GPIO_FN_DU0_DG2, - - /* Port11 */ - GPIO_FN_LCDD11, - GPIO_FN_FSICISLD, - GPIO_FN_DU0_DG3, - - /* Port12 */ - GPIO_FN_LCDD12, - GPIO_FN_FSICOMC, - GPIO_FN_DU0_DG4, - - /* Port13 */ - GPIO_FN_LCDD13, - GPIO_FN_FSICOLR, - GPIO_FN_FSICILR, - GPIO_FN_DU0_DG5, - - /* Port14 */ - GPIO_FN_LCDD14, - GPIO_FN_FSICOBT, - GPIO_FN_FSICIBT, - GPIO_FN_DU0_DG6, - - /* Port15 */ - GPIO_FN_LCDD15, - GPIO_FN_FSICOSLD, - GPIO_FN_DU0_DG7, - - /* Port16 */ - GPIO_FN_LCDD16, - GPIO_FN_TPU1TO1, - GPIO_FN_DU0_DB0, - - /* Port17 */ - GPIO_FN_LCDD17, - GPIO_FN_SF_IRQ_00, - GPIO_FN_DU0_DB1, - - /* Port18 */ - GPIO_FN_LCDD18, - GPIO_FN_SF_IRQ_01, - GPIO_FN_DU0_DB2, - - /* Port19 */ - GPIO_FN_LCDD19, - GPIO_FN_DU0_DB3, - - /* Port20 */ - GPIO_FN_LCDD20, - GPIO_FN_DU0_DB4, - - /* Port21 */ - GPIO_FN_LCDD21, - GPIO_FN_DU0_DB5, - - /* Port22 */ - GPIO_FN_LCDD22, - GPIO_FN_DU0_DB6, - - /* Port23 */ - GPIO_FN_LCDD23, - GPIO_FN_DU0_DB7, - - /* Port24 */ - GPIO_FN_LCDHSYN, - GPIO_FN_LCDCS, - GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N, - - /* Port25 */ - GPIO_FN_LCDVSYN, - GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N, - - /* Port26 */ - GPIO_FN_LCDDCK, - GPIO_FN_LCDWR, - GPIO_FN_DU0_DOTCLKIN, - - /* Port27 */ - GPIO_FN_LCDDISP, - GPIO_FN_LCDRS, - GPIO_FN_DU0_DOTCLKOUT, - - /* Port28 */ - GPIO_FN_LCDRD_N, - GPIO_FN_DU0_DOTCLKOUTB, - - /* Port29 */ - GPIO_FN_LCDLCLK, - GPIO_FN_SF_IRQ_02, - GPIO_FN_DU0_DISP_CSYNC_N_DE, - - /* Port30 */ - GPIO_FN_LCDDON, - GPIO_FN_SF_IRQ_03, - GPIO_FN_DU0_ODDF_N_CLAMP, - - /* Port32 */ - GPIO_FN_SIM0_DET, - GPIO_FN_CSCIF0_RTS, - - /* Port33 */ - GPIO_FN_SIM1_DET, - GPIO_FN_CSCIF0_CTS, - - /* Port34 */ - GPIO_FN_SIM0_PWRON, - GPIO_FN_CSCIF0_SCK, - - /* Port35 */ - GPIO_FN_CSCIF1_RTS, - - /* Port36 */ - GPIO_FN_CSCIF1_CTS, - - /* Port37 */ - GPIO_FN_CSCIF1_SCK, - - /* Port38 */ - GPIO_FN_TPU0TO1, - GPIO_FN_CHSCIF0_HRTS, - - /* Port39 */ - GPIO_FN_TPU0TO2, - GPIO_FN_CHSCIF0_HCTS, - - /* Port40 */ - GPIO_FN_TPU0TO3, - GPIO_FN_CHSCIF0_HSCK, - - /* Port64 */ - GPIO_FN_PDM0_DATA, - - /* Port65 */ - GPIO_FN_PDM1_DATA, - - /* Port66 */ - GPIO_FN_HSI_RX_WAKE, - GPIO_FN_MSIOF3_SYNC, - GPIO_FN_GenIO4, - - /* Port67 */ - GPIO_FN_HSI_RX_READY, - GPIO_FN_GIO_OUT3_67, - GPIO_FN_CHSCIF1_HTX, - - /* Port68 */ - GPIO_FN_HSI_RX_FLAG, - GPIO_FN_MSIOF3_TXD, - GPIO_FN_GIO_OUT4_68, - - /* Port69 */ - GPIO_FN_HSI_RX_DATA, - GPIO_FN_MSIOF3_RXD, - GPIO_FN_GIO_OUT5_69, - - /* Port70 */ - GPIO_FN_HSI_TX_FLAG, - GPIO_FN_GIO_OUT1_70, - GPIO_FN_HSIC_TSTCLK0, - GPIO_FN_CHSCIF1_HRTS, - - /* Port71 */ - GPIO_FN_HSI_TX_DATA, - GPIO_FN_GIO_OUT2_71, - GPIO_FN_HSIC_TSTCLK1, - GPIO_FN_CHSCIF1_HCTS, - - /* Port72 */ - GPIO_FN_HSI_TX_WAKE, - GPIO_FN_GenIO8, - GPIO_FN_CHSCIF1_HRX, - - /* Port73 */ - GPIO_FN_HSI_TX_READY, - GPIO_FN_MSIOF3_SCK, - GPIO_FN_GIO_OUT0_73, - - /* Port74 - Port85 */ - GPIO_FN_IRDA_OUT, - GPIO_FN_IRDA_IN, - GPIO_FN_IRDA_FIRSEL, - GPIO_FN_TPU0TO0, - GPIO_FN_DIGRFEN, - GPIO_FN_GPS_TIMESTAMP, - GPIO_FN_TXP, - GPIO_FN_TXP2, - GPIO_FN_COEX_0, - GPIO_FN_COEX_1, - - /* Port96 - Port101 */ - GPIO_FN_KEYIN0, - GPIO_FN_KEYIN1, - GPIO_FN_KEYIN2, - GPIO_FN_KEYIN3, - GPIO_FN_KEYIN4, - GPIO_FN_KEYIN5, - - /* Port102 */ - GPIO_FN_KEYIN6, - - /* Port103 */ - GPIO_FN_KEYIN7, - - /* Port104 - Port108 */ - GPIO_FN_KEYOUT0, - GPIO_FN_KEYOUT1, - GPIO_FN_KEYOUT2, - GPIO_FN_KEYOUT3, - GPIO_FN_KEYOUT4, - - /* Port109 */ - GPIO_FN_KEYOUT5, - - /* Port110 */ - GPIO_FN_KEYOUT6, - - /* Port111 */ - GPIO_FN_KEYOUT7, - GPIO_FN_RFANAEN, - - /* Port112 */ - GPIO_FN_KEYIN8, - GPIO_FN_KEYOUT8, - GPIO_FN_SF_IRQ_04, - - /* Port113 */ - GPIO_FN_KEYIN9, - GPIO_FN_KEYOUT9, - GPIO_FN_SF_IRQ_05, - - /* Port114 */ - GPIO_FN_KEYIN10, - GPIO_FN_KEYOUT10, - GPIO_FN_SF_IRQ_06, - - /* Port115 */ - GPIO_FN_KEYIN11, - GPIO_FN_KEYOUT11, - GPIO_FN_SF_IRQ_07, - - /* Port116 */ - GPIO_FN_CSCIF0_TX, - - /* Port117 */ - GPIO_FN_CSCIF0_RX, - - /* Port118 */ - GPIO_FN_CSCIF1_TX, - - /* Port119 */ - GPIO_FN_CSCIF1_RX, - - /* Port120 */ - GPIO_FN_SF_PORT_1_120, - GPIO_FN_DU0_CDE, - - /* Port121 */ - GPIO_FN_SF_PORT_0_121, - - /* Port122 */ - GPIO_FN_CHSCIF0_HTX, - - /* Port123 */ - GPIO_FN_CHSCIF0_HRX, - - /* Port124 */ - GPIO_FN_ISP_STROBE_124, - - /* Port125 */ - GPIO_FN_STP_ISD_0, - GPIO_FN_PDM4_CLK_125, - GPIO_FN_MSIOF2_TXD, - GPIO_FN_SIM0_VOLTSEL0, - - /* Port126 */ - GPIO_FN_TS_SDEN, - GPIO_FN_MSIOF7_SYNC, - GPIO_FN_STP_ISEN_1, - - /* Port128 */ - GPIO_FN_STP_ISEN_0, - GPIO_FN_PDM1_OUTDATA_128, - GPIO_FN_MSIOF2_SYNC, - GPIO_FN_SIM1_VOLTSEL1, - - /* Port129 */ - GPIO_FN_TS_SPSYNC, - GPIO_FN_MSIOF7_RXD, - GPIO_FN_STP_ISSYNC_1, - - /* Port130 */ - GPIO_FN_STP_ISSYNC_0, - GPIO_FN_PDM4_DATA_130, - GPIO_FN_MSIOF2_RXD, - GPIO_FN_SIM0_VOLTSEL1, - - /* Port131 */ - GPIO_FN_STP_OPWM_0, - GPIO_FN_SIM1_PWRON, - - /* Port132 */ - GPIO_FN_TS_SCK, - GPIO_FN_MSIOF7_SCK, - GPIO_FN_STP_ISCLK_1, - - /* Port133 */ - GPIO_FN_STP_ISCLK_0, - GPIO_FN_PDM1_OUTCLK_133, - GPIO_FN_MSIOF2_SCK, - GPIO_FN_SIM1_VOLTSEL0, - - /* Port134 */ - GPIO_FN_TS_SDAT, - GPIO_FN_MSIOF7_TXD, - GPIO_FN_STP_ISD_1, - - /* Port160 - Port178 */ - GPIO_FN_MMCD0_0, - GPIO_FN_MMCD0_1, - GPIO_FN_MMCD0_2, - GPIO_FN_MMCD0_3, - GPIO_FN_MMCD0_4, - GPIO_FN_MMCD0_5, - GPIO_FN_MMCD0_6, - GPIO_FN_MMCD0_7, - GPIO_FN_MMCCMD0, - GPIO_FN_MMCCLK0, - GPIO_FN_MMCRST, - - /* Port192 - Port200 FN1 */ - GPIO_FN_A10, - GPIO_FN_A9, - GPIO_FN_A8, - GPIO_FN_A7, - GPIO_FN_A6, - GPIO_FN_A5, - GPIO_FN_A4, - GPIO_FN_A3, - GPIO_FN_A2, - - /* Port192 - Port200 FN2 */ - GPIO_FN_MMCD1_7, - GPIO_FN_MMCD1_6, - GPIO_FN_MMCD1_5, - GPIO_FN_MMCD1_4, - GPIO_FN_MMCD1_3, - GPIO_FN_MMCD1_2, - GPIO_FN_MMCD1_1, - GPIO_FN_MMCD1_0, - GPIO_FN_MMCCMD1, - - /* Port192 - Port200 IRQ */ - - /* Port201 */ - GPIO_FN_A1, - - /* Port202 */ - GPIO_FN_A0, - GPIO_FN_BS, - - /* Port203 */ - GPIO_FN_CKO, - GPIO_FN_MMCCLK1, - - /* Port204 */ - GPIO_FN_CS0_N, - GPIO_FN_SIM0_GPO1, - - /* Port205 */ - GPIO_FN_CS2_N, - GPIO_FN_SIM0_GPO2, - - /* Port206 */ - GPIO_FN_CS4_N, - GPIO_FN_VIO_VD, - GPIO_FN_SIM1_GPO0, - - /* Port207 - Port212 FN1 */ - GPIO_FN_D15, - GPIO_FN_D14, - GPIO_FN_D13, - GPIO_FN_D12, - GPIO_FN_D11, - GPIO_FN_D10, - - /* Port207 - Port212 FN5 */ - GPIO_FN_GIO_OUT15, - GPIO_FN_GIO_OUT14, - GPIO_FN_GIO_OUT13, - GPIO_FN_GIO_OUT12, - GPIO_FN_WGM_TXP2, - GPIO_FN_WGM_GPS_TIMEM_ASK_RFCLK, - - /* Port213 - Port222 FN1 */ - GPIO_FN_D9, - GPIO_FN_D8, - GPIO_FN_D7, - GPIO_FN_D6, - GPIO_FN_D5, - GPIO_FN_D4, - GPIO_FN_D3, - GPIO_FN_D2, - GPIO_FN_D1, - GPIO_FN_D0, - - /* Port213 - Port222 FN2 */ - GPIO_FN_VIO_D9, - GPIO_FN_VIO_D8, - GPIO_FN_VIO_D7, - GPIO_FN_VIO_D6, - GPIO_FN_VIO_D5, - GPIO_FN_VIO_D4, - GPIO_FN_VIO_D3, - GPIO_FN_VIO_D2, - GPIO_FN_VIO_D1, - GPIO_FN_VIO_D0, - - /* Port213 - Port222 FN5 */ - GPIO_FN_GIO_OUT9, - GPIO_FN_GIO_OUT8, - GPIO_FN_GIO_OUT7, - GPIO_FN_GIO_OUT6, - GPIO_FN_GIO_OUT5_217, - GPIO_FN_GIO_OUT4_218, - GPIO_FN_GIO_OUT3_219, - GPIO_FN_GIO_OUT2_220, - GPIO_FN_GIO_OUT1_221, - GPIO_FN_GIO_OUT0_222, - - /* Port224 */ - GPIO_FN_RDWR_224, - GPIO_FN_VIO_HD, - GPIO_FN_SIM1_GPO2, - - /* Port225 */ - GPIO_FN_RD_N, - - /* Port226 */ - GPIO_FN_WAIT_N, - GPIO_FN_VIO_CLK, - GPIO_FN_SIM1_GPO1, - - /* Port227 */ - GPIO_FN_WE0_N, - GPIO_FN_RDWR_227, - - /* Port228 */ - GPIO_FN_WE1_N, - GPIO_FN_SIM0_GPO0, - - /* Port229 */ - GPIO_FN_PWMO, - GPIO_FN_VIO_CKO1_229, - - /* Port230 */ - GPIO_FN_SLIM_CLK, - GPIO_FN_VIO_CKO4_230, - - /* Port231 */ - GPIO_FN_SLIM_DATA, - GPIO_FN_VIO_CKO5_231, - - /* Port232 */ - GPIO_FN_VIO_CKO2_232, - GPIO_FN_SF_PORT_0_232, - - /* Port233 */ - GPIO_FN_VIO_CKO3_233, - GPIO_FN_SF_PORT_1_233, - - /* Port234 */ - GPIO_FN_FSIACK, - GPIO_FN_PDM3_CLK_234, - GPIO_FN_ISP_IRIS1_234, - - /* Port235 */ - GPIO_FN_FSIAISLD, - GPIO_FN_PDM3_DATA_235, - - /* Port236 */ - GPIO_FN_FSIAOMC, - GPIO_FN_PDM0_OUTCLK_236, - GPIO_FN_ISP_IRIS0_236, - - /* Port237 */ - GPIO_FN_FSIAOLR, - GPIO_FN_FSIAILR, - - /* Port238 */ - GPIO_FN_FSIAOBT, - GPIO_FN_FSIAIBT, - - /* Port239 */ - GPIO_FN_FSIAOSLD, - GPIO_FN_PDM0_OUTDATA_239, - - /* Port240 */ - GPIO_FN_FSIBISLD, - - /* Port241 */ - GPIO_FN_FSIBOLR, - GPIO_FN_FSIBILR, - - /* Port242 */ - GPIO_FN_FSIBOMC, - GPIO_FN_ISP_SHUTTER1_242, - - /* Port243 */ - GPIO_FN_FSIBOBT, - GPIO_FN_FSIBIBT, - - /* Port244 */ - GPIO_FN_FSIBOSLD, - GPIO_FN_FSIASPDIF, - - /* Port245 */ - GPIO_FN_FSIBCK, - GPIO_FN_ISP_SHUTTER0_245, - - /* Port246 - Port250 FN1 */ - GPIO_FN_ISP_IRIS1_246, - GPIO_FN_ISP_IRIS0_247, - GPIO_FN_ISP_SHUTTER1_248, - GPIO_FN_ISP_SHUTTER0_249, - GPIO_FN_ISP_STROBE_250, - - /* Port256 - Port258 */ - GPIO_FN_MSIOF0_SYNC, - GPIO_FN_MSIOF0_RXD, - GPIO_FN_MSIOF0_SCK, - - /* Port259 */ - GPIO_FN_MSIOF0_SS2, - GPIO_FN_VIO_CKO3_259, - - /* Port260 */ - GPIO_FN_MSIOF0_TXD, - - /* Port261 */ - GPIO_FN_CHSCIF1_HSCK, - - /* Port262 */ - - /* Port263 - Port266 FN1 */ - GPIO_FN_MSIOF1_SS2, - GPIO_FN_MSIOF1_TXD, - GPIO_FN_MSIOF1_RXD, - GPIO_FN_MSIOF1_SS1, - - /* Port263 - Port266 FN4 */ - GPIO_FN_MSIOF5_SS2, - GPIO_FN_MSIOF5_TXD, - GPIO_FN_MSIOF5_RXD, - GPIO_FN_MSIOF5_SS1, - - /* Port267 */ - GPIO_FN_MSIOF0_SS1, - - /* Port268 */ - GPIO_FN_MSIOF1_SCK, - GPIO_FN_MSIOF5_SCK, - - /* Port269 */ - GPIO_FN_MSIOF1_SYNC, - GPIO_FN_MSIOF5_SYNC, - - /* Port270 - Port273 FN1 */ - GPIO_FN_MSIOF2_SS1, - GPIO_FN_MSIOF2_SS2, - GPIO_FN_MSIOF3_SS2, - GPIO_FN_MSIOF3_SS1, - - /* Port270 - Port273 FN3 */ - GPIO_FN_VIO_CKO5_270, - GPIO_FN_VIO_CKO2_271, - GPIO_FN_VIO_CKO1_272, - GPIO_FN_VIO_CKO4_273, - - /* Port274 */ - GPIO_FN_MSIOF4_SS2, - GPIO_FN_TPU1TO0, - - /* Port275 - Port280 */ - GPIO_FN_IC_DP, - GPIO_FN_SIM0_RST, - GPIO_FN_IC_DM, - GPIO_FN_SIM0_BSICOMP, - GPIO_FN_SIM0_CLK, - GPIO_FN_SIM0_IO, - - /* Port281 */ - GPIO_FN_SIM1_IO, - GPIO_FN_PDM2_DATA_281, - - /* Port282 */ - GPIO_FN_SIM1_CLK, - GPIO_FN_PDM2_CLK_282, - - /* Port283 */ - GPIO_FN_SIM1_RST, - - /* Port289 */ - GPIO_FN_SDHID1_0, - GPIO_FN_STMDATA0_2, - - /* Port290 */ - GPIO_FN_SDHID1_1, - GPIO_FN_STMDATA1_2, - - /* Port291 - Port294 FN1 */ - GPIO_FN_SDHID1_2, - GPIO_FN_SDHID1_3, - GPIO_FN_SDHICLK1, - GPIO_FN_SDHICMD1, - - /* Port291 - Port294 FN3 */ - GPIO_FN_STMDATA2_2, - GPIO_FN_STMDATA3_2, - GPIO_FN_STMCLK_2, - GPIO_FN_STMSIDI_2, - - /* Port295 */ - GPIO_FN_SDHID2_0, - GPIO_FN_MSIOF4_TXD, - GPIO_FN_MSIOF6_TXD, - - /* Port296 */ - GPIO_FN_SDHID2_1, - GPIO_FN_MSIOF6_SS2, - - /* Port297 - Port300 FN1 */ - GPIO_FN_SDHID2_2, - GPIO_FN_SDHID2_3, - GPIO_FN_SDHICLK2, - GPIO_FN_SDHICMD2, - - /* Port297 - Port300 FN2 */ - GPIO_FN_MSIOF4_RXD, - GPIO_FN_MSIOF4_SYNC, - GPIO_FN_MSIOF4_SCK, - GPIO_FN_MSIOF4_SS1, - - /* Port297 - Port300 FN3 */ - - /* Port297 - Port300 FN4 */ - GPIO_FN_MSIOF6_RXD, - GPIO_FN_MSIOF6_SYNC, - GPIO_FN_MSIOF6_SCK, - GPIO_FN_MSIOF6_SS1, - - /* Port301 */ - GPIO_FN_SDHICD0, - - /* Port302 - Port306 FN1 */ - GPIO_FN_SDHID0_0, - GPIO_FN_SDHID0_1, - GPIO_FN_SDHID0_2, - GPIO_FN_SDHID0_3, - GPIO_FN_SDHICMD0, - - /* Port302 - Port306 FN3 */ - GPIO_FN_STMDATA0_1, - GPIO_FN_STMDATA1_1, - GPIO_FN_STMDATA2_1, - GPIO_FN_STMDATA3_1, - GPIO_FN_STMSIDI_1, - - /* Port307 */ - GPIO_FN_SDHIWP0, - - /* Port308 */ - GPIO_FN_SDHICLK0, - GPIO_FN_STMCLK_1, - - /* Port320 - Port329 */ -}; - void r8a73a4_add_standard_devices(void); void r8a73a4_clock_init(void); void r8a73a4_pinmux_init(void); From 202ac6a21a79500ef5aab4cd8665be2597e9345c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 22:51:53 +0900 Subject: [PATCH 296/307] sh-pfc: r8a73a4: Remove unused GPIO bias data Remove unused pull-up/down data from the r8a73a4 PFC code. Signed-off-by: Magnus Damm Acked-by: Linus Walleij Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 176 +++------------------------ 1 file changed, 15 insertions(+), 161 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 464c5f9ce9fa..bbff5596e922 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -115,16 +115,6 @@ enum { PORT_ALL(IN), PINMUX_INPUT_END, - /* PORT0_IN_PU -> PORT329_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT329_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - /* PORT0_OUT -> PORT329_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), @@ -438,156 +428,12 @@ enum { PINMUX_MARK_END, }; +#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + static const pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ - - PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1), - PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3), - PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5), - PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7), - PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9), - - PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11), - PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15), - PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17), - PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19), - - PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21), - PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23), - PORT_DATA_IO_PU_PD(24), PORT_DATA_IO_PU_PD(25), - PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27), - PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29), - - PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32), - PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34), - PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36), - PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38), - PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40), - - PORT_DATA_IO_PU_PD(64), PORT_DATA_IO_PU_PD(65), - PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), - - PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), - PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85), - - PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), - - PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101), - PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103), - PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105), - PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107), - PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109), - - PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111), - PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113), - PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115), - PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117), - PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119), - - PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121), - PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123), - PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125), - PORT_DATA_IO_PU_PD(126), - PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129), - - PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131), - PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133), - PORT_DATA_IO_PU_PD(134), - - PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161), - PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163), - PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165), - PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167), - PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169), - - PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171), - PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173), - PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175), - PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU_PD(178), - - PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195), - PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197), - PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), - - PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201), - PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203), - PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), - PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209), - - PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211), - PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213), - PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215), - PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217), - PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219), - - PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221), - PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224), - PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226), - PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228), - PORT_DATA_IO_PU_PD(229), - - PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231), - PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233), - PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235), - PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237), - PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239), - - PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241), - PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243), - PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245), - PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247), - PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249), - - PORT_DATA_IO_PU_PD(250), - PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257), - PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259), - - PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261), - PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263), - PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265), - PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267), - PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269), - - PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271), - PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273), - PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275), - PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277), - PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279), - - PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281), - PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283), - PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289), - - PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291), - PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293), - PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295), - PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297), - PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299), - - PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301), - PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303), - PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305), - PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307), - PORT_DATA_IO_PU_PD(308), - - PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321), - PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323), - PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325), - PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327), - PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329), + PINMUX_DATA_ALL(), /* Port0 */ PINMUX_DATA(LCDD0_MARK, PORT0_FN1), @@ -2042,8 +1888,18 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scifb3), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#undef PORTCR +#define PORTCR(nr, reg) \ + { \ + PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } +static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), PORTCR(1, 0xe6050001), PORTCR(2, 0xe6050002), @@ -2706,8 +2562,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .ops = &r8a73a4_pinmux_ops, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, From 53e42c2974feaa269bc485267d0a4df0ef55e549 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 21 Mar 2013 03:03:38 -0700 Subject: [PATCH 297/307] ARM: shmobile: add R-Car M1A Bock-W platform support Add basic Bock-W board support More devices will be added on top of this patch after PICNTRL and clock framework are in better shape. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7778-bockw.dts | 32 ++++++++++++++ arch/arm/configs/bockw_defconfig | 66 ++++++++++++++++++++++++++++ arch/arm/mach-shmobile/Kconfig | 6 +++ arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/board-bockw.c | 43 ++++++++++++++++++ 6 files changed, 149 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7778-bockw.dts create mode 100644 arch/arm/configs/bockw_defconfig create mode 100644 arch/arm/mach-shmobile/board-bockw.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ee9fbe4d9912..363fa5070310 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ ccu9540.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ r8a7779-marzen-reference.dtb \ sh73a0-kzm9g.dtb \ sh73a0-kzm9g-reference.dtb \ diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts new file mode 100644 index 000000000000..735c964920f9 --- /dev/null +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -0,0 +1,32 @@ +/* + * Reference Device Tree Source for the Bock-W board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * based on r8a7779 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "r8a7778.dtsi" + +/ { + model = "bockw"; + compatible = "renesas,bockw", "renesas,r8a7778"; + + chosen { + bootargs = "console=ttySC0,115200 ignore_loglevel"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x10000000>; + }; +}; diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig new file mode 100644 index 000000000000..6037705b7b67 --- /dev/null +++ b/arch/arm/configs/bockw_defconfig @@ -0,0 +1,66 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_KERNEL_LZMA=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_R8A7778=y +CONFIG_MACH_BOCKW=y +CONFIG_MEMORY_START=0x60000000 +CONFIG_MEMORY_SIZE=0x10000000 +CONFIG_SHMOBILE_TIMER_HZ=1024 +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_EM_TIMER_STI is not set +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_458693=y +CONFIG_ARM_ERRATA_460075=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel" +CONFIG_CMDLINE_FORCE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_KEYS=y +CONFIG_CRYPTO=y +CONFIG_AVERAGE=y diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 3933a315adf2..18712ad7ccc4 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -124,6 +124,12 @@ config MACH_ARMADILLO800EVA select SND_SOC_WM8978 if SND_SIMPLE_CARD select USE_OF +config MACH_BOCKW + bool "BOCK-W platform" + depends on ARCH_R8A7778 + select ARCH_REQUIRE_GPIOLIB + select USE_OF + config MACH_MARZEN bool "MARZEN board" depends on ARCH_R8A7779 diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 0c9a2901370e..5eada967ec6b 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_KOTA2) += board-kota2.o obj-$(CONFIG_MACH_BONITO) += board-bonito.o +obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c new file mode 100644 index 000000000000..56ab56ed5f59 --- /dev/null +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -0,0 +1,43 @@ +/* + * Bock-W board support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +static void __init bockw_init(void) +{ + r8a7778_clock_init(); + r8a7778_add_standard_devices(); +} + +static const char *bockw_boards_compat_dt[] __initdata = { + "renesas,bockw", + NULL, +}; + +DT_MACHINE_START(BOCKW_DT, "bockw") + .init_early = r8a7778_init_delay, + .init_irq = r8a7778_init_irq_dt, + .init_machine = bockw_init, + .init_time = shmobile_timer_init, + .dt_compat = bockw_boards_compat_dt, +MACHINE_END From 8c1de8ee030e929f96d38415da7551e7fdd847b6 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 21 Mar 2013 17:05:44 +0100 Subject: [PATCH 298/307] ARM: shmobile: kzm9g-reference: add ethernet support Add a DT node for the SMSC 9221 ethernet chip, found on kzm9g, to its reference implementation. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index f33b5ccb7446..5972abb55f9c 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -44,6 +44,19 @@ reg_3p3v: regulator@1 { regulator-always-on; regulator-boot-on; }; + + lan9220@10000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x10000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqpin0>; + interrupts = <3 0>; /* active low */ + reg-io-width = <4>; + smsc,irq-push-pull; + smsc,save-mac-address; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; }; &mmcif { From 78ded16886f539830ed58d9bc043656c1785a082 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 29 Mar 2013 17:00:02 +0900 Subject: [PATCH 299/307] ARM: shmobile: APE6EVM base support V3 of APE6EVM base board support making use of 1 GiB of memory, the SCIFA0 serial port and ARM architected timer. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a73a4-ape6evm.dts | 31 +++++++++++++++++ arch/arm/mach-shmobile/Kconfig | 8 ++++- arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/board-ape6evm.c | 46 ++++++++++++++++++++++++++ 5 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/r8a73a4-ape6evm.dts create mode 100644 arch/arm/mach-shmobile/board-ape6evm.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 363fa5070310..a99b0f7baa72 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7779-marzen-reference.dtb \ sh73a0-kzm9g.dtb \ sh73a0-kzm9g-reference.dtb \ + r8a73a4-ape6evm.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ socfpga_vt.dtb diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts new file mode 100644 index 000000000000..833f703f9be5 --- /dev/null +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -0,0 +1,31 @@ +/* + * Device Tree Source for the APE6EVM board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "r8a73a4.dtsi" + +/ { + model = "APE6EVM"; + compatible = "renesas,ape6evm", "renesas,r8a73a4"; + + chosen { + bootargs = "console=ttySC0,115200 ignore_loglevel"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 18712ad7ccc4..c0da6afa8a51 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -96,6 +96,11 @@ config MACH_AG5EVM select REGULATOR_FIXED_VOLTAGE if REGULATOR select SH_LCD_MIPI_DSI +config MACH_APE6EVM + bool "APE6EVM board" + depends on ARCH_R8A73A4 + select USE_OF + config MACH_MACKEREL bool "mackerel board" depends on ARCH_SH7372 @@ -189,7 +194,7 @@ config MEMORY_START hex "Physical memory start address" default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \ MACH_MACKEREL || MACH_BONITO || \ - MACH_ARMADILLO800EVA + MACH_ARMADILLO800EVA || MACH_APE6EVM default "0x41000000" if MACH_KOTA2 default "0x00000000" ---help--- @@ -199,6 +204,7 @@ config MEMORY_START config MEMORY_SIZE hex "Physical memory size" + default "0x40000000" if MACH_APE6EVM default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \ MACH_ARMADILLO800EVA default "0x1e000000" if MACH_KOTA2 diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 5eada967ec6b..ec2524e43a47 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o # Board objects obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o +obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_KOTA2) += board-kota2.o obj-$(CONFIG_MACH_BONITO) += board-bonito.o diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c new file mode 100644 index 000000000000..9234d4f567ba --- /dev/null +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -0,0 +1,46 @@ +/* + * APE6EVM board support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void __init ape6evm_add_standard_devices(void) +{ + r8a73a4_clock_init(); + r8a73a4_add_standard_devices(); +} + +static const char *ape6evm_boards_compat_dt[] __initdata = { + "renesas,ape6evm", + NULL, +}; + +DT_MACHINE_START(APE6EVM_DT, "ape6evm") + .init_irq = irqchip_init, + .init_time = shmobile_timer_init, + .init_machine = ape6evm_add_standard_devices, + .dt_compat = ape6evm_boards_compat_dt, +MACHINE_END From 2c56055c46502f24097de93aabc8a4c00e12dab4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 29 Mar 2013 17:00:12 +0900 Subject: [PATCH 300/307] ARM: shmobile: APE6EVM PFC support Start using the r8a73a4 PFC on the APE6EVM board and configure the SCIFA0 console signals in the PFC via PINCTRL. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-ape6evm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 9234d4f567ba..33a8a62437f1 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -21,15 +21,25 @@ #include #include #include +#include #include #include #include #include #include +static const struct pinctrl_map ape6evm_pinctrl_map[] = { + /* SCIFA0 console */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", + "scifa0_data", "scifa0"), +}; + static void __init ape6evm_add_standard_devices(void) { r8a73a4_clock_init(); + pinctrl_register_mappings(ape6evm_pinctrl_map, + ARRAY_SIZE(ape6evm_pinctrl_map)); + r8a73a4_pinmux_init(); r8a73a4_add_standard_devices(); } From 15351a7a22c207b2e9ce83b01782a2324006014a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 29 Mar 2013 17:00:21 +0900 Subject: [PATCH 301/307] ARM: shmobile: APE6EVM LAN9220 support Add LAN9220 support to the APE6EVM board using C and DT. At this point the PFC driver lacks DT bindings so to configure the PFC we use PINCTRL in C board code. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 23 +++++++++++++++- arch/arm/mach-shmobile/board-ape6evm.c | 38 ++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 833f703f9be5..f603c6946c29 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -16,7 +16,7 @@ / { compatible = "renesas,ape6evm", "renesas,r8a73a4"; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel"; + bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"; }; memory@40000000 { @@ -24,8 +24,29 @@ memory@40000000 { reg = <0 0x40000000 0 0x40000000>; }; + ape6evm_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; + + ethernet@8000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x08000000 0x1000>; + interrupt-parent = <&irqc1>; + interrupts = <8 0x4>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&ape6evm_fixed_3v3>; + vddvario-supply = <&ape6evm_fixed_3v3>; + }; }; }; diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 33a8a62437f1..55b8c9fef954 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -18,20 +18,49 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include #include #include +#include +#include +#include #include +#include #include #include #include +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +/* SMSC LAN9220 */ +static const struct resource lan9220_res[] = { + DEFINE_RES_MEM(0x08000000, 0x1000), + { + .start = irq_pin(40), /* IRQ40 */ + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, + }, +}; + +static const struct smsc911x_platform_config lan9220_data = { + .flags = SMSC911X_USE_32BIT, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, +}; + static const struct pinctrl_map ape6evm_pinctrl_map[] = { /* SCIFA0 console */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", "scifa0_data", "scifa0"), + /* SMSC */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4", + "irqc_irq40", "irqc"), }; static void __init ape6evm_add_standard_devices(void) @@ -41,6 +70,15 @@ static void __init ape6evm_add_standard_devices(void) ARRAY_SIZE(ape6evm_pinctrl_map)); r8a73a4_pinmux_init(); r8a73a4_add_standard_devices(); + + /* LAN9220 ethernet */ + gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */ + + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + platform_device_register_resndata(&platform_bus, "smsc911x", -1, + lan9220_res, ARRAY_SIZE(lan9220_res), + &lan9220_data, sizeof(lan9220_data)); } static const char *ape6evm_boards_compat_dt[] __initdata = { From 3cc828fdb32281cc8166d3a40bee32b90ce3cad8 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 29 Mar 2013 17:49:37 +0900 Subject: [PATCH 302/307] ARM: shmobile: Initial r8a7790 Lager board support Lager base board support making use of 2 GiB of memory, the r8a7790 SoC with the SCIF0 serial port and CA15 with ARM architected timer. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7790-lager.dts | 31 +++++++++++++++++++ arch/arm/mach-shmobile/Kconfig | 9 +++++- arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/board-lager.c | 46 ++++++++++++++++++++++++++++ 5 files changed, 87 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/r8a7790-lager.dts create mode 100644 arch/arm/mach-shmobile/board-lager.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a99b0f7baa72..47b6be7cf1e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -138,6 +138,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen-reference.dtb \ + r8a7790-lager.dtb \ sh73a0-kzm9g.dtb \ sh73a0-kzm9g-reference.dtb \ r8a73a4-ape6evm.dtb \ diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts new file mode 100644 index 000000000000..09a84fce89d6 --- /dev/null +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -0,0 +1,31 @@ +/* + * Device Tree Source for the Lager board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "r8a7790.dtsi" + +/ { + model = "Lager"; + compatible = "renesas,lager", "renesas,r8a7790"; + + chosen { + bootargs = "console=ttySC6,115200 ignore_loglevel"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index c0da6afa8a51..549e05985745 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -154,6 +154,11 @@ config MACH_MARZEN_REFERENCE This is intended to aid developers +config MACH_LAGER + bool "Lager board" + depends on ARCH_R8A7790 + select USE_OF + config MACH_KZM9D bool "KZM9D board" depends on ARCH_EMEV2 @@ -194,7 +199,8 @@ config MEMORY_START hex "Physical memory start address" default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \ MACH_MACKEREL || MACH_BONITO || \ - MACH_ARMADILLO800EVA || MACH_APE6EVM + MACH_ARMADILLO800EVA || MACH_APE6EVM || \ + MACH_LAGER default "0x41000000" if MACH_KOTA2 default "0x00000000" ---help--- @@ -204,6 +210,7 @@ config MEMORY_START config MEMORY_SIZE hex "Physical memory size" + default "0x80000000" if MACH_LAGER default "0x40000000" if MACH_APE6EVM default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \ MACH_ARMADILLO800EVA diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index ec2524e43a47..068f1dadc46b 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_BONITO) += board-bonito.o obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o +obj-$(CONFIG_MACH_LAGER) += board-lager.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c new file mode 100644 index 000000000000..ea6f9e5d3500 --- /dev/null +++ b/arch/arm/mach-shmobile/board-lager.c @@ -0,0 +1,46 @@ +/* + * Lager board support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void __init lager_add_standard_devices(void) +{ + r8a7790_clock_init(); + r8a7790_add_standard_devices(); +} + +static const char *lager_boards_compat_dt[] __initdata = { + "renesas,lager", + NULL, +}; + +DT_MACHINE_START(LAGER_DT, "lager") + .init_irq = irqchip_init, + .init_time = shmobile_timer_init, + .init_machine = lager_add_standard_devices, + .dt_compat = lager_boards_compat_dt, +MACHINE_END From fb7a89c4afa43240af705db44e3e41233016adf9 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 29 Mar 2013 22:05:48 +0100 Subject: [PATCH 303/307] ARM: shmobile: mackerel: SDHI resources do not have to be numbered The SDHI driver doesn't care about platform resource order, explicit resource numbering is redundant. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 33 +++++++++---------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 1a9c75383ca0..c4f80d4e4026 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -982,21 +982,18 @@ static struct sh_mobile_sdhi_info sdhi0_info = { }; static struct resource sdhi0_resources[] = { - [0] = { + { .name = "SDHI0", .start = 0xe6850000, .end = 0xe68500ff, .flags = IORESOURCE_MEM, - }, - [1] = { + }, { .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */, .flags = IORESOURCE_IRQ, - }, - [2] = { + }, { .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, .flags = IORESOURCE_IRQ, - }, - [3] = { + }, { .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, .flags = IORESOURCE_IRQ, }, @@ -1025,23 +1022,20 @@ static struct sh_mobile_sdhi_info sdhi1_info = { }; static struct resource sdhi1_resources[] = { - [0] = { + { .name = "SDHI1", .start = 0xe6860000, .end = 0xe68600ff, .flags = IORESOURCE_MEM, - }, - [1] = { + }, { .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ .flags = IORESOURCE_IRQ, - }, - [2] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ .flags = IORESOURCE_IRQ, - }, - [3] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ .flags = IORESOURCE_IRQ, @@ -1079,23 +1073,20 @@ static struct sh_mobile_sdhi_info sdhi2_info = { }; static struct resource sdhi2_resources[] = { - [0] = { + { .name = "SDHI2", .start = 0xe6870000, .end = 0xe68700ff, .flags = IORESOURCE_MEM, - }, - [1] = { + }, { .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */ .flags = IORESOURCE_IRQ, - }, - [2] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ .flags = IORESOURCE_IRQ, - }, - [3] = { + }, { .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ .flags = IORESOURCE_IRQ, From 3f9efeecb4876661b952746c8bbe460682dce1ad Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 29 Mar 2013 22:05:49 +0100 Subject: [PATCH 304/307] ARM: shmobile: mackerel: remove OCR masks, where regulators are used Both SDHI and MMCIF drivers ignore their OCR platform values, when available voltages can be retrieved from regulators. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index c4f80d4e4026..734565d4b0f0 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1014,7 +1014,6 @@ static struct platform_device sdhi0_device = { static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, - .tmio_ocr_mask = MMC_VDD_165_195, .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL, @@ -1125,7 +1124,6 @@ static struct resource sh_mmcif_resources[] = { static struct sh_mmcif_plat_data sh_mmcif_plat = { .sup_pclk = 0, - .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NEEDS_POLL, From fe0a14417bc95492621b45a3cf088ce53ee05c36 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 29 Mar 2013 22:05:50 +0100 Subject: [PATCH 305/307] ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio Both SDHI and MMCIF drivers can use the standard slot-gpio card-detection functions. Switch mackerel to using them instead of platform callbacks. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 39 ++++++++----------------- 1 file changed, 12 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 734565d4b0f0..a47a11160693 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -963,15 +963,6 @@ static struct platform_device nand_flash_device = { }, }; -/* - * The card detect pin of the top SD/MMC slot (CN7) is active low and is - * connected to GPIO A22 of SH7372 (GPIO 41). - */ -static int slot_cn7_get_cd(struct platform_device *pdev) -{ - return !gpio_get_value(41); -} - /* SDHI0 */ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, @@ -1011,13 +1002,15 @@ static struct platform_device sdhi0_device = { #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) /* SDHI1 */ + +/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */ static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL, - .get_cd = slot_cn7_get_cd, + .cd_gpio = 41, }; static struct resource sdhi1_resources[] = { @@ -1052,23 +1045,19 @@ static struct platform_device sdhi1_device = { }; #endif +/* SDHI2 */ + /* * The card detect pin of the top SD/MMC slot (CN23) is active low and is - * connected to GPIO SCIFB_SCK of SH7372 (162). + * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162). */ -static int slot_cn23_get_cd(struct platform_device *pdev) -{ - return !gpio_get_value(162); -} - -/* SDHI2 */ static struct sh_mobile_sdhi_info sdhi2_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL, - .get_cd = slot_cn23_get_cd, + .cd_gpio = 162, }; static struct resource sdhi2_resources[] = { @@ -1127,7 +1116,9 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NEEDS_POLL, - .get_cd = slot_cn7_get_cd, + .use_cd_gpio = true, + /* card detect pin for SD/MMC slot (CN7) */ + .cd_gpio = 41, .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; @@ -1475,12 +1466,6 @@ static void __init mackerel_init(void) /* SDHI0 PORT172 card-detect IRQ26 */ gpio_request(GPIO_FN_IRQ26_172, NULL); - /* card detect pin for MMC slot (CN7) */ - gpio_request_one(41, GPIOF_IN, NULL); - - /* card detect pin for microSD slot (CN23) */ - gpio_request_one(162, GPIOF_IN, NULL); - /* FLCTL */ gpio_request(GPIO_FN_D0_NAF0, NULL); gpio_request(GPIO_FN_D1_NAF1, NULL); From 757688c8b51073450b77940dcb94f33bf4c3de88 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 29 Mar 2013 22:05:51 +0100 Subject: [PATCH 306/307] ARM: shmobile: mackerel: add interrupt names for SDHI0 To unify with SDHI1 also use named IRQs for SDHI0. This also clarifies which specific IRQs are used. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index a47a11160693..b976ad682016 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -979,12 +979,11 @@ static struct resource sdhi0_resources[] = { .end = 0xe68500ff, .flags = IORESOURCE_MEM, }, { - .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */, - .flags = IORESOURCE_IRQ, - }, { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, .flags = IORESOURCE_IRQ, }, { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, .flags = IORESOURCE_IRQ, }, @@ -1019,10 +1018,6 @@ static struct resource sdhi1_resources[] = { .start = 0xe6860000, .end = 0xe68600ff, .flags = IORESOURCE_MEM, - }, { - .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, - .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ - .flags = IORESOURCE_IRQ, }, { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ From 00ae962f8051bb143fa1c43c6a9c8274c3a9c593 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 29 Mar 2013 22:05:52 +0100 Subject: [PATCH 307/307] ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection MMCIF and SDHI1 share the same slot on mackerel. One of them is selected by a jumper, which cannot be queried from software. Currently in software one of the two interfaces is selected, depending whether or not the MMCIF driver is enabled. This is not optimal, since the kernel has to be rebuilt to switch from one interface to another. Still, so far there isn't a better option. At least make this selection consistent. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-mackerel.c | 34 ++++++++++++------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index b976ad682016..5b452e1e7d8a 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -999,7 +999,7 @@ static struct platform_device sdhi0_device = { }, }; -#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) +#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) /* SDHI1 */ /* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */ @@ -1061,10 +1061,6 @@ static struct resource sdhi2_resources[] = { .start = 0xe6870000, .end = 0xe68700ff, .flags = IORESOURCE_MEM, - }, { - .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, - .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */ - .flags = IORESOURCE_IRQ, }, { .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ @@ -1087,6 +1083,7 @@ static struct platform_device sdhi2_device = { }; /* SH_MMCIF */ +#if IS_ENABLED(CONFIG_MMC_SH_MMCIF) static struct resource sh_mmcif_resources[] = { [0] = { .name = "MMCIF", @@ -1118,7 +1115,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; -static struct platform_device sh_mmcif_device __maybe_unused = { +static struct platform_device sh_mmcif_device = { .name = "sh_mmcif", .id = 0, .dev = { @@ -1129,7 +1126,7 @@ static struct platform_device sh_mmcif_device __maybe_unused = { .num_resources = ARRAY_SIZE(sh_mmcif_resources), .resource = sh_mmcif_resources, }; - +#endif static int mackerel_camera_add(struct soc_camera_device *icd); static void mackerel_camera_del(struct soc_camera_device *icd); @@ -1236,11 +1233,12 @@ static struct platform_device *mackerel_devices[] __initdata = { &fsi_hdmi_device, &nand_flash_device, &sdhi0_device, -#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) +#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) &sdhi1_device, +#else + &sh_mmcif_device, #endif &sdhi2_device, - &sh_mmcif_device, &ceu_device, &mackerel_camera, &hdmi_device, @@ -1305,11 +1303,6 @@ static struct i2c_board_info i2c1_devices[] = { }; static const struct pinctrl_map mackerel_pinctrl_map[] = { - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_ctrl_0", "mmc0"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", "sdhi0_data4", "sdhi0"), @@ -1318,11 +1311,17 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", "sdhi0_wp", "sdhi0"), /* SDHI1 */ -#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) +#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", "sdhi1_data4", "sdhi1"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", "sdhi1_ctrl", "sdhi1"), +#else + /* MMCIF */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_data8_0", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", + "mmc0_ctrl_0", "mmc0"), #endif /* SDHI2 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", @@ -1347,10 +1346,11 @@ static void __init mackerel_init(void) { "A3SP", &usbhs0_device, }, { "A3SP", &usbhs1_device, }, { "A3SP", &nand_flash_device, }, - { "A3SP", &sh_mmcif_device, }, { "A3SP", &sdhi0_device, }, -#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) +#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) { "A3SP", &sdhi1_device, }, +#else + { "A3SP", &sh_mmcif_device, }, #endif { "A3SP", &sdhi2_device, }, { "A4R", &ceu_device, },