sh-pfc: r8a73a4: Add SCIF pin groups and functions
Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and SCIFB0->SCIFB3. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Magnus Damm
Simon Horman
parent
57ef73b469
commit
172fd616dd
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@ -1576,6 +1576,286 @@ static const struct pinmux_range pinmux_ranges[] = {
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{.begin = 320, .end = 329,},
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};
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/* - SCIFA0 ----------------------------------------------------------------- */
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static const unsigned int scifa0_data_pins[] = {
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/* SCIFA0_RXD, SCIFA0_TXD */
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117, 116,
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};
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static const unsigned int scifa0_data_mux[] = {
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SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
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};
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static const unsigned int scifa0_clk_pins[] = {
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/* SCIFA0_SCK */
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34,
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};
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static const unsigned int scifa0_clk_mux[] = {
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SCIFA0_SCK_MARK,
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};
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static const unsigned int scifa0_ctrl_pins[] = {
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/* SCIFA0_RTS, SCIFA0_CTS */
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32, 33,
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};
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static const unsigned int scifa0_ctrl_mux[] = {
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SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
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};
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/* - SCIFA1 ----------------------------------------------------------------- */
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static const unsigned int scifa1_data_pins[] = {
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/* SCIFA1_RXD, SCIFA1_TXD */
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119, 118,
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};
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static const unsigned int scifa1_data_mux[] = {
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SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
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};
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static const unsigned int scifa1_clk_pins[] = {
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/* SCIFA1_SCK */
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37,
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};
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static const unsigned int scifa1_clk_mux[] = {
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SCIFA1_SCK_MARK,
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};
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static const unsigned int scifa1_ctrl_pins[] = {
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/* SCIFA1_RTS, SCIFA1_CTS */
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35, 36,
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};
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static const unsigned int scifa1_ctrl_mux[] = {
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SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
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};
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/* - SCIFB0 ----------------------------------------------------------------- */
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static const unsigned int scifb0_data_pins[] = {
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/* SCIFB0_RXD, SCIFB0_TXD */
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123, 122,
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};
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static const unsigned int scifb0_data_mux[] = {
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SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
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};
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static const unsigned int scifb0_clk_pins[] = {
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/* SCIFB0_SCK */
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40,
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};
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static const unsigned int scifb0_clk_mux[] = {
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SCIFB0_SCK_MARK,
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};
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static const unsigned int scifb0_ctrl_pins[] = {
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/* SCIFB0_RTS, SCIFB0_CTS */
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38, 39,
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};
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static const unsigned int scifb0_ctrl_mux[] = {
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SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
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};
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/* - SCIFB1 ----------------------------------------------------------------- */
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static const unsigned int scifb1_data_pins[] = {
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/* SCIFB1_RXD, SCIFB1_TXD */
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27, 26,
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};
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static const unsigned int scifb1_data_mux[] = {
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SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
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};
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static const unsigned int scifb1_clk_pins[] = {
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/* SCIFB1_SCK */
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28,
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};
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static const unsigned int scifb1_clk_mux[] = {
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SCIFB1_SCK_28_MARK,
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};
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static const unsigned int scifb1_ctrl_pins[] = {
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/* SCIFB1_RTS, SCIFB1_CTS */
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24, 25,
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};
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static const unsigned int scifb1_ctrl_mux[] = {
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SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
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};
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static const unsigned int scifb1_data_b_pins[] = {
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/* SCIFB1_RXD, SCIFB1_TXD */
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72, 67,
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};
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static const unsigned int scifb1_data_b_mux[] = {
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SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
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};
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static const unsigned int scifb1_clk_b_pins[] = {
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/* SCIFB1_SCK */
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261,
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};
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static const unsigned int scifb1_clk_b_mux[] = {
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SCIFB1_SCK_261_MARK,
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};
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static const unsigned int scifb1_ctrl_b_pins[] = {
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/* SCIFB1_RTS, SCIFB1_CTS */
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70, 71,
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};
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static const unsigned int scifb1_ctrl_b_mux[] = {
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SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
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};
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/* - SCIFB2 ----------------------------------------------------------------- */
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static const unsigned int scifb2_data_pins[] = {
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/* SCIFB2_RXD, SCIFB2_TXD */
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69, 68,
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};
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static const unsigned int scifb2_data_mux[] = {
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SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
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};
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static const unsigned int scifb2_clk_pins[] = {
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/* SCIFB2_SCK */
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262,
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};
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static const unsigned int scifb2_clk_mux[] = {
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SCIFB2_SCK_262_MARK,
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};
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static const unsigned int scifb2_ctrl_pins[] = {
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/* SCIFB2_RTS, SCIFB2_CTS */
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73, 66,
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};
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static const unsigned int scifb2_ctrl_mux[] = {
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SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
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};
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static const unsigned int scifb2_data_b_pins[] = {
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/* SCIFB2_RXD, SCIFB2_TXD */
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297, 295,
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};
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static const unsigned int scifb2_data_b_mux[] = {
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SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
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};
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static const unsigned int scifb2_clk_b_pins[] = {
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/* SCIFB2_SCK */
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299,
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};
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static const unsigned int scifb2_clk_b_mux[] = {
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SCIFB2_SCK_299_MARK,
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};
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static const unsigned int scifb2_ctrl_b_pins[] = {
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/* SCIFB2_RTS, SCIFB2_CTS */
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300, 298,
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};
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static const unsigned int scifb2_ctrl_b_mux[] = {
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SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
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};
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/* - SCIFB3 ----------------------------------------------------------------- */
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static const unsigned int scifb3_data_pins[] = {
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/* SCIFB3_RXD, SCIFB3_TXD */
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22, 21,
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};
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static const unsigned int scifb3_data_mux[] = {
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SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
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};
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static const unsigned int scifb3_clk_pins[] = {
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/* SCIFB3_SCK */
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23,
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};
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static const unsigned int scifb3_clk_mux[] = {
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SCIFB3_SCK_23_MARK,
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};
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static const unsigned int scifb3_ctrl_pins[] = {
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/* SCIFB3_RTS, SCIFB3_CTS */
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19, 20,
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};
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static const unsigned int scifb3_ctrl_mux[] = {
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SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
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};
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static const unsigned int scifb3_data_b_pins[] = {
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/* SCIFB3_RXD, SCIFB3_TXD */
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120, 121,
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};
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static const unsigned int scifb3_data_b_mux[] = {
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SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
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};
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static const unsigned int scifb3_clk_b_pins[] = {
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/* SCIFB3_SCK */
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40,
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};
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static const unsigned int scifb3_clk_b_mux[] = {
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SCIFB3_SCK_40_MARK,
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};
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static const unsigned int scifb3_ctrl_b_pins[] = {
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/* SCIFB3_RTS, SCIFB3_CTS */
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38, 39,
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};
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static const unsigned int scifb3_ctrl_b_mux[] = {
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SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
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};
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static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scifa0_data),
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SH_PFC_PIN_GROUP(scifa0_clk),
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SH_PFC_PIN_GROUP(scifa0_ctrl),
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SH_PFC_PIN_GROUP(scifa1_data),
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SH_PFC_PIN_GROUP(scifa1_clk),
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SH_PFC_PIN_GROUP(scifa1_ctrl),
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SH_PFC_PIN_GROUP(scifb0_data),
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SH_PFC_PIN_GROUP(scifb0_clk),
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SH_PFC_PIN_GROUP(scifb0_ctrl),
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SH_PFC_PIN_GROUP(scifb1_data),
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SH_PFC_PIN_GROUP(scifb1_clk),
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SH_PFC_PIN_GROUP(scifb1_ctrl),
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SH_PFC_PIN_GROUP(scifb1_data_b),
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SH_PFC_PIN_GROUP(scifb1_clk_b),
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SH_PFC_PIN_GROUP(scifb1_ctrl_b),
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SH_PFC_PIN_GROUP(scifb2_data),
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SH_PFC_PIN_GROUP(scifb2_clk),
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SH_PFC_PIN_GROUP(scifb2_ctrl),
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SH_PFC_PIN_GROUP(scifb2_data_b),
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SH_PFC_PIN_GROUP(scifb2_clk_b),
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SH_PFC_PIN_GROUP(scifb2_ctrl_b),
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SH_PFC_PIN_GROUP(scifb3_data),
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SH_PFC_PIN_GROUP(scifb3_clk),
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SH_PFC_PIN_GROUP(scifb3_ctrl),
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SH_PFC_PIN_GROUP(scifb3_data_b),
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SH_PFC_PIN_GROUP(scifb3_clk_b),
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SH_PFC_PIN_GROUP(scifb3_ctrl_b),
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};
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static const char * const scifa0_groups[] = {
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"scifa0_data",
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"scifa0_clk",
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"scifa0_ctrl",
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};
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static const char * const scifa1_groups[] = {
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"scifa1_data",
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"scifa1_clk",
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"scifa1_ctrl",
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};
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static const char * const scifb0_groups[] = {
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"scifb0_data",
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"scifb0_clk",
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"scifb0_ctrl",
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};
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static const char * const scifb1_groups[] = {
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"scifb1_data",
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"scifb1_clk",
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"scifb1_ctrl",
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"scifb1_data_b",
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"scifb1_clk_b",
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"scifb1_ctrl_b",
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};
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static const char * const scifb2_groups[] = {
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"scifb2_data",
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"scifb2_clk",
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"scifb2_ctrl",
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"scifb2_data_b",
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"scifb2_clk_b",
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"scifb2_ctrl_b",
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};
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static const char * const scifb3_groups[] = {
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"scifb3_data",
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"scifb3_clk",
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"scifb3_ctrl",
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"scifb3_data_b",
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"scifb3_clk_b",
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"scifb3_ctrl_b",
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};
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(scifa0),
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SH_PFC_FUNCTION(scifa1),
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SH_PFC_FUNCTION(scifb0),
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SH_PFC_FUNCTION(scifb1),
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SH_PFC_FUNCTION(scifb2),
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SH_PFC_FUNCTION(scifb3),
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};
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#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
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static const struct pinmux_func pinmux_func_gpios[] = {
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@ -3084,8 +3364,15 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
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.pins = pinmux_pins,
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.nr_pins = ARRAY_SIZE(pinmux_pins),
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.ranges = pinmux_ranges,
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.nr_ranges = ARRAY_SIZE(pinmux_ranges),
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.groups = pinmux_groups,
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.nr_groups = ARRAY_SIZE(pinmux_groups),
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.functions = pinmux_functions,
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.nr_functions = ARRAY_SIZE(pinmux_functions),
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.func_gpios = pinmux_func_gpios,
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.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
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