drm/amd/display: Add dual edp optimization flag.

[Why & How]
Add a dual edp power optimization flag, so driver will
notify this flag to dmub FW to determine if apply the
power optimization.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun 2020-11-04 14:26:38 -05:00 committed by Alex Deucher
parent e26c9d80b8
commit 175f097149
4 changed files with 6 additions and 1 deletions

View file

@ -2757,6 +2757,7 @@ bool dc_link_setup_psr(struct dc_link *link,
* (Always set for DAL2, did not check ASIC)
*/
psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
/* Complete PSR entry before aborting to prevent intermittent
* freezes on certain eDPs

View file

@ -697,6 +697,7 @@ struct psr_config {
bool psr_frame_capture_indication_req;
unsigned int psr_sdp_transmit_line_num_deadline;
bool allow_smu_optimizations;
bool allow_multi_disp_optimizations;
};
union dmcu_psr_level {
@ -799,6 +800,7 @@ struct psr_context {
*/
unsigned int frame_delay;
bool allow_smu_optimizations;
bool allow_multi_disp_optimizations;
};
struct colorspace_transform {

View file

@ -261,6 +261,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
// Misc
copy_settings_data->psr_level = psr_context->psr_level.u32all;
copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
copy_settings_data->frame_delay = psr_context->frame_delay;
copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;

View file

@ -613,7 +613,8 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t smu_optimizations_en;
uint8_t frame_delay;
uint8_t frame_cap_ind;
uint8_t pad[3];
uint8_t pad[2];
uint8_t multi_disp_optimizations_en;
uint16_t init_sdp_deadline;
uint16_t pad2;
};