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drm/radeon/kms: add r100/r200 OQ support.

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This adds the relocation necessary for OQ support on the r100/r200
chipsets.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2009-08-21 10:07:54 +10:00
parent 08e4d53474
commit 17782d9950
2 changed files with 13 additions and 0 deletions
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10
drivers/gpu/drm/radeon/r100.c
View file

@ -1091,6 +1091,16 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
tmp |= tile_flags; tmp |= tile_flags;
ib[idx] = tmp; ib[idx] = tmp;
break; break;
case RADEON_RB3D_ZPASS_ADDR:
r = r100_cs_packet_next_reloc(p, &reloc);
if (r) {
DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
idx, reg);
r100_cs_dump_packet(p, pkt);
return r;
}
ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
break;
default: default:
/* FIXME: we don't want to allow anyothers packet */ /* FIXME: we don't want to allow anyothers packet */
break; break;

3
drivers/gpu/drm/radeon/radeon_reg.h
View file

@ -2337,6 +2337,9 @@
# define RADEON_RE_WIDTH_SHIFT 0 # define RADEON_RE_WIDTH_SHIFT 0
# define RADEON_RE_HEIGHT_SHIFT 16 # define RADEON_RE_HEIGHT_SHIFT 16
#define RADEON_RB3D_ZPASS_DATA 0x3290
#define RADEON_RB3D_ZPASS_ADDR 0x3294
#define RADEON_SE_CNTL 0x1c4c #define RADEON_SE_CNTL 0x1c4c
# define RADEON_FFACE_CULL_CW (0 << 0) # define RADEON_FFACE_CULL_CW (0 << 0)
# define RADEON_FFACE_CULL_CCW (1 << 0) # define RADEON_FFACE_CULL_CCW (1 << 0)