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PCI: imx: Add the imx8mm pcie support
i.MX8MM PCIe works mostly like the i.MX8MQ one, but has a different PHY and allows to output the internal PHY reference clock via the refclk pad. Add the i.MX8MM PCIe support based on the standalone PHY driver. Link: https://lore.kernel.org/r/1640312885-31142-2-git-send-email-hongxing.zhu@nxp.com Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
parent
3e15f623bb
commit
178e244cb6
1 changed files with 73 additions and 8 deletions
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@ -29,6 +29,7 @@
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <linux/phy/phy.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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@ -49,6 +50,7 @@ enum imx6_pcie_variants {
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IMX6QP,
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IMX7D,
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IMX8MQ,
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IMX8MM,
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};
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#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
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@ -88,6 +90,7 @@ struct imx6_pcie {
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struct device *pd_pcie;
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/* power domain for pcie phy */
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struct device *pd_pcie_phy;
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struct phy *phy;
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const struct imx6_pcie_drvdata *drvdata;
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};
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@ -372,6 +375,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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case IMX7D:
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case IMX8MQ:
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reset_control_assert(imx6_pcie->pciephy_reset);
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fallthrough;
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case IMX8MM:
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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case IMX6SX:
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@ -407,7 +412,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
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{
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WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
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WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
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imx6_pcie->drvdata->variant != IMX8MM);
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return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
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}
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@ -446,6 +452,11 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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break;
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case IMX7D:
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break;
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case IMX8MM:
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ret = clk_prepare_enable(imx6_pcie->pcie_aux);
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if (ret)
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dev_err(dev, "unable to enable pcie_aux clock\n");
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break;
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case IMX8MQ:
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ret = clk_prepare_enable(imx6_pcie->pcie_aux);
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if (ret) {
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@ -522,6 +533,14 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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goto err_ref_clk;
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}
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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if (phy_power_on(imx6_pcie->phy))
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dev_err(dev, "unable to power on PHY\n");
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break;
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default:
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break;
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}
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/* allow the clocks to stabilize */
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usleep_range(200, 500);
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@ -538,6 +557,10 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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case IMX8MQ:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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break;
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case IMX8MM:
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if (phy_init(imx6_pcie->phy))
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dev_err(dev, "waiting for phy ready timeout!\n");
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break;
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case IMX7D:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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@ -614,6 +637,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
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static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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/*
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* The PHY initialization had been done in the PHY
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* driver, break here directly.
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*/
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break;
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case IMX8MQ:
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/*
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* TODO: Currently this code assumes external
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@ -753,6 +782,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
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break;
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case IMX7D:
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case IMX8MQ:
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case IMX8MM:
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reset_control_deassert(imx6_pcie->apps_reset);
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break;
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}
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@ -871,6 +901,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
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IMX6Q_GPR12_PCIE_CTL_2, 0);
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break;
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case IMX7D:
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case IMX8MM:
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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default:
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@ -930,6 +961,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
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break;
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case IMX8MQ:
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case IMX8MM:
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clk_disable_unprepare(imx6_pcie->pcie_aux);
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break;
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default:
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@ -945,8 +977,16 @@ static int imx6_pcie_suspend_noirq(struct device *dev)
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return 0;
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imx6_pcie_pm_turnoff(imx6_pcie);
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imx6_pcie_clk_disable(imx6_pcie);
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imx6_pcie_ltssm_disable(dev);
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imx6_pcie_clk_disable(imx6_pcie);
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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if (phy_power_off(imx6_pcie->phy))
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dev_err(dev, "unable to power off PHY\n");
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break;
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default:
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break;
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}
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return 0;
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}
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@ -1043,11 +1083,6 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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}
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/* Fetch clocks */
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imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
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if (IS_ERR(imx6_pcie->pcie_phy))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
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"pcie_phy clock source missing or invalid\n");
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imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
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if (IS_ERR(imx6_pcie->pcie_bus))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
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@ -1089,10 +1124,35 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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dev_err(dev, "Failed to get PCIE APPS reset control\n");
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return PTR_ERR(imx6_pcie->apps_reset);
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}
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break;
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case IMX8MM:
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imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(imx6_pcie->pcie_aux))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
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"pcie_aux clock source missing or invalid\n");
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imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
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"apps");
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if (IS_ERR(imx6_pcie->apps_reset))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
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"failed to get pcie apps reset control\n");
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imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
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if (IS_ERR(imx6_pcie->phy))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
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"failed to get pcie phy\n");
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break;
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default:
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break;
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}
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/* Don't fetch the pcie_phy clock, if it has abstract PHY driver */
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if (imx6_pcie->phy == NULL) {
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imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
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if (IS_ERR(imx6_pcie->pcie_phy))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
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"pcie_phy clock source missing or invalid\n");
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}
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/* Grab turnoff reset */
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imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
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@ -1202,6 +1262,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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[IMX8MQ] = {
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.variant = IMX8MQ,
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},
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[IMX8MM] = {
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.variant = IMX8MM,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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},
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};
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static const struct of_device_id imx6_pcie_of_match[] = {
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@ -1209,7 +1273,8 @@ static const struct of_device_id imx6_pcie_of_match[] = {
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{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
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{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
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{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
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{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
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{},
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};
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