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drm/amdkfd: Update packet manager for GFX9.4.3

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In GFX 9.4.3, there can be more than 8 SDMA engines.
As a result, extended_engine_sel and engine_sel fields
in MAP_QUEUES packet need to be updated to allow correct
mapping of SDMA queues to these SDMA engines.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi 2022-12-08 12:08:17 -05:00 committed by Alex Deucher
parent 753b999afe
commit 1794e9d7e7
2 changed files with 15 additions and 4 deletions
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16
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
View file

@ -225,9 +225,19 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
engine_sel__mes_map_queues__sdma0_vi;
else {
packet->bitfields2.extended_engine_sel =
extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
packet->bitfields2.engine_sel = q->properties.sdma_engine_id;
/*
* For GFX9.4.3, SDMA engine id can be greater than 8.
* For such cases, set extended_engine_sel to 2 and
* ensure engine_sel lies between 0-7.
*/
if (q->properties.sdma_engine_id >= 8)
packet->bitfields2.extended_engine_sel =
extended_engine_sel__mes_map_queues__sdma8_to_15_sel;
else
packet->bitfields2.extended_engine_sel =
extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
packet->bitfields2.engine_sel = q->properties.sdma_engine_id % 8;
}
break;
default:

3
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
View file

@ -263,7 +263,8 @@ enum mes_map_queues_engine_sel_enum {
enum mes_map_queues_extended_engine_sel_enum {
extended_engine_sel__mes_map_queues__legacy_engine_sel = 0,
extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1
extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1,
extended_engine_sel__mes_map_queues__sdma8_to_15_sel = 2
};
struct pm4_mes_map_queues {