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arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes
Add SDHCI1/2 nodes for eMMC and uSD card respectively. Do note that most SM6350 devices seem to come with UFS. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Replaced SM6350_CX with its constant value] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-14-konrad.dybcio@somainline.org
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@ -8,6 +8,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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/ {
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@ -397,12 +398,92 @@ rng: rng@793000 {
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clock-names = "core";
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clock-names = "core";
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};
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};
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sdhc_1: sdhci@7c4000 {
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compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x007c4000 0 0x1000>,
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<0 0x007c5000 0 0x1000>,
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<0 0x007c8000 0 0x8000>;
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reg-names = "hc", "cqhci", "ice";
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interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "core", "xo";
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qcom,dll-config = <0x000f642c>;
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qcom,ddr-config = <0x80040868>;
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power-domains = <&rpmhpd 0>;
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operating-points-v2 = <&sdhc1_opp_table>;
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bus-width = <8>;
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non-removable;
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supports-cqe;
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status = "disabled";
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sdhc1_opp_table: sdhc1-opp-table {
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compatible = "operating-points-v2";
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opp-19200000 {
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opp-hz = /bits/ 64 <19200000>;
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required-opps = <&rpmhpd_opp_min_svs>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-384000000 {
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opp-hz = /bits/ 64 <384000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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tcsr_mutex: hwlock@1f40000 {
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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reg = <0x0 0x01f40000 0x0 0x40000>;
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#hwlock-cells = <1>;
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#hwlock-cells = <1>;
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};
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};
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sdhc_2: sdhci@8804000 {
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compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x08804000 0 0x1000>;
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_AHB_CLK>,
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<&gcc GCC_SDCC2_APPS_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "core", "xo";
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qcom,dll-config = <0x0007642c>;
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qcom,ddr-config = <0x80040868>;
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power-domains = <&rpmhpd 0>;
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operating-points-v2 = <&sdhc2_opp_table>;
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bus-width = <4>;
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status = "disabled";
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sdhc2_opp_table: sdhc2-opp-table {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-202000000 {
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opp-hz = /bits/ 64 <202000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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usb_1_hsphy: phy@88e3000 {
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usb_1_hsphy: phy@88e3000 {
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compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
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compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
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reg = <0 0x088e3000 0 0x400>;
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reg = <0 0x088e3000 0 0x400>;
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