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cmdq patches needed by drm driver to use cmdq interface
-----BEGIN PGP SIGNATURE----- iQJKBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl4VxLAXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH5KdQ/zBPHiZm7NcZfYWNrxoNbCAS84 +ycyXIHNT8OZsAvy3Wlmk3Y6+2KFSWCacm4bWpfopNWtHL3axPENdJgYNDvX8foG 44eExCepYrTUgPyhwsax5jWewxO04/xYuRYslyBAFjqodv2q8Zik2uP1MqMsgh/e zW13kj1qh34g1wSHTd34/blF1Jn7/zLW9UQCWdnBOV8W6rKc2mD25gJ5VdGN0Yp3 +yLP9u6+gBzqnIgtrTbwRCL1zKNnBnKe/Mzetc19G9dGkumEFnvQ6hw9XO0xl77g FJS0/mypA0NwWLLt55Q+ZJpMh7x05pUfnvuwuz0yxyo6c54ZqmAH7hPkpiDBCM9Q vZYk0b2oWbEL65bMX370SLa+EY2nPB9bOSg/sMD/t0Bw/wO04tsgYHMN20AYUGTt sAcQz698hy/zfzJK60PzoP0gQNvssi2Z1QMK+73hmaIWuqsnhFvO8EtwI4Vflw2U VtIuKQ6E46R+8jd81cWDSjSlW82SPxZ51RRfryjFCK4baQ0XrlMB39l9f7hjt1IW XcMdK4IBhsG6Mg8T5KaQz2b9kDkecwIZaPLTYBKMP4cK4MwiGrl/Bifi+eXkQMsX do2w/8BwePvau0xhqI0J5puvlUg06pNj78MRtxGF/T+XjE2Xv2mNNly6v2a1uogt vJhxuospwI5buFj1sQ== =0tI1 -----END PGP SIGNATURE----- Merge tag 'v5.5-next-cmdq-stable' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux cmdq patches needed by drm driver to use cmdq interface
This commit is contained in:
CK Hu
commit
17aab656ae
3 changed files with 185 additions and 26 deletions
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@ -9,12 +9,54 @@
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#include <linux/mailbox_controller.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#define CMDQ_ARG_A_WRITE_MASK 0xffff
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#define CMDQ_WRITE_ENABLE_MASK BIT(0)
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#define CMDQ_POLL_ENABLE_MASK BIT(0)
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#define CMDQ_EOC_IRQ_EN BIT(0)
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#define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
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<< 32 | CMDQ_EOC_IRQ_EN)
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struct cmdq_instruction {
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union {
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u32 value;
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u32 mask;
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};
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union {
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u16 offset;
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u16 event;
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};
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u8 subsys;
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u8 op;
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};
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int cmdq_dev_get_client_reg(struct device *dev,
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struct cmdq_client_reg *client_reg, int idx)
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{
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struct of_phandle_args spec;
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int err;
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if (!client_reg)
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return -ENOENT;
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err = of_parse_phandle_with_fixed_args(dev->of_node,
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"mediatek,gce-client-reg",
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3, idx, &spec);
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if (err < 0) {
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dev_err(dev,
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"error %d can't parse gce-client-reg property (%d)",
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err, idx);
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return err;
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}
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client_reg->subsys = (u8)spec.args[0];
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client_reg->offset = (u16)spec.args[1];
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client_reg->size = (u16)spec.args[2];
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of_node_put(spec.np);
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return 0;
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}
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EXPORT_SYMBOL(cmdq_dev_get_client_reg);
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static void cmdq_client_timeout(struct timer_list *t)
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{
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struct cmdq_client *client = from_timer(client, t, timer);
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@ -110,10 +152,10 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
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}
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EXPORT_SYMBOL(cmdq_pkt_destroy);
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static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
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u32 arg_a, u32 arg_b)
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static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
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struct cmdq_instruction inst)
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{
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u64 *cmd_ptr;
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struct cmdq_instruction *cmd_ptr;
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if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
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/*
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@ -129,8 +171,9 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
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__func__, (u32)pkt->buf_size);
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return -ENOMEM;
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}
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cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
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(*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
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*cmd_ptr = inst;
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pkt->cmd_buf_size += CMDQ_INST_SIZE;
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return 0;
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@ -138,24 +181,34 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
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int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
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{
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u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
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(subsys << CMDQ_SUBSYS_SHIFT);
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struct cmdq_instruction inst;
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return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
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inst.op = CMDQ_CODE_WRITE;
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inst.value = value;
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inst.offset = offset;
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inst.subsys = subsys;
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return cmdq_pkt_append_command(pkt, inst);
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}
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EXPORT_SYMBOL(cmdq_pkt_write);
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int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value, u32 mask)
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{
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u32 offset_mask = offset;
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int err = 0;
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struct cmdq_instruction inst = { {0} };
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u16 offset_mask = offset;
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int err;
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if (mask != 0xffffffff) {
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err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
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inst.op = CMDQ_CODE_MASK;
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inst.mask = ~mask;
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err = cmdq_pkt_append_command(pkt, inst);
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if (err < 0)
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return err;
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offset_mask |= CMDQ_WRITE_ENABLE_MASK;
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}
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err |= cmdq_pkt_write(pkt, subsys, offset_mask, value);
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err = cmdq_pkt_write(pkt, subsys, offset_mask, value);
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return err;
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}
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@ -163,43 +216,85 @@ EXPORT_SYMBOL(cmdq_pkt_write_mask);
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int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
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{
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u32 arg_b;
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struct cmdq_instruction inst = { {0} };
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if (event >= CMDQ_MAX_EVENT)
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return -EINVAL;
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/*
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* WFE arg_b
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* bit 0-11: wait value
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* bit 15: 1 - wait, 0 - no wait
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* bit 16-27: update value
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* bit 31: 1 - update, 0 - no update
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*/
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arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
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inst.op = CMDQ_CODE_WFE;
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inst.value = CMDQ_WFE_OPTION;
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inst.event = event;
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return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, arg_b);
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return cmdq_pkt_append_command(pkt, inst);
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}
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EXPORT_SYMBOL(cmdq_pkt_wfe);
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int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
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{
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struct cmdq_instruction inst = { {0} };
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if (event >= CMDQ_MAX_EVENT)
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return -EINVAL;
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return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event,
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CMDQ_WFE_UPDATE);
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inst.op = CMDQ_CODE_WFE;
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inst.value = CMDQ_WFE_UPDATE;
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inst.event = event;
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return cmdq_pkt_append_command(pkt, inst);
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}
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EXPORT_SYMBOL(cmdq_pkt_clear_event);
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int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value)
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{
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struct cmdq_instruction inst = { {0} };
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int err;
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inst.op = CMDQ_CODE_POLL;
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inst.value = value;
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inst.offset = offset;
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inst.subsys = subsys;
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err = cmdq_pkt_append_command(pkt, inst);
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return err;
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}
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EXPORT_SYMBOL(cmdq_pkt_poll);
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int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value, u32 mask)
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{
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struct cmdq_instruction inst = { {0} };
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int err;
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inst.op = CMDQ_CODE_MASK;
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inst.mask = ~mask;
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err = cmdq_pkt_append_command(pkt, inst);
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if (err < 0)
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return err;
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offset = offset | CMDQ_POLL_ENABLE_MASK;
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err = cmdq_pkt_poll(pkt, subsys, offset, value);
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return err;
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}
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EXPORT_SYMBOL(cmdq_pkt_poll_mask);
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static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
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{
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struct cmdq_instruction inst = { {0} };
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int err;
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/* insert EOC and generate IRQ for each command iteration */
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err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN);
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inst.op = CMDQ_CODE_EOC;
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inst.value = CMDQ_EOC_IRQ_EN;
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err = cmdq_pkt_append_command(pkt, inst);
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if (err < 0)
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return err;
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/* JUMP to end */
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err |= cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS);
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inst.op = CMDQ_CODE_JUMP;
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inst.value = CMDQ_JUMP_PASS;
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err = cmdq_pkt_append_command(pkt, inst);
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return err;
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}
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@ -20,6 +20,16 @@
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#define CMDQ_WFE_WAIT BIT(15)
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#define CMDQ_WFE_WAIT_VALUE 0x1
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/*
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* WFE arg_b
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* bit 0-11: wait value
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* bit 15: 1 - wait, 0 - no wait
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* bit 16-27: update value
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* bit 31: 1 - update, 0 - no update
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*/
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#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
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CMDQ_WFE_WAIT_VALUE)
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/** cmdq event maximum */
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#define CMDQ_MAX_EVENT 0x3ff
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@ -45,6 +55,7 @@
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enum cmdq_code {
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CMDQ_CODE_MASK = 0x02,
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CMDQ_CODE_WRITE = 0x04,
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CMDQ_CODE_POLL = 0x08,
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CMDQ_CODE_JUMP = 0x10,
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CMDQ_CODE_WFE = 0x20,
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CMDQ_CODE_EOC = 0x40,
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@ -15,6 +15,12 @@
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struct cmdq_pkt;
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struct cmdq_client_reg {
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u8 subsys;
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u16 offset;
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u16 size;
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};
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struct cmdq_client {
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spinlock_t lock;
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u32 pkt_cnt;
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@ -24,6 +30,21 @@ struct cmdq_client {
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u32 timeout_ms; /* in unit of microsecond */
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};
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/**
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* cmdq_dev_get_client_reg() - parse cmdq client reg from the device
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* node of CMDQ client
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* @dev: device of CMDQ mailbox client
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* @client_reg: CMDQ client reg pointer
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* @idx: the index of desired reg
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*
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* Return: 0 for success; else the error code is returned
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*
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* Help CMDQ client parsing the cmdq client reg
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* from the device node of CMDQ client.
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*/
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int cmdq_dev_get_client_reg(struct device *dev,
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struct cmdq_client_reg *client_reg, int idx);
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/**
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* cmdq_mbox_create() - create CMDQ mailbox client and channel
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* @dev: device of CMDQ mailbox client
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@ -99,6 +120,38 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
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*/
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int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
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/**
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* cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
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* execute an instruction that wait for a specified
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* hardware register to check for the value w/o mask.
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* All GCE hardware threads will be blocked by this
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* instruction.
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* @pkt: the CMDQ packet
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* @subsys: the CMDQ sub system code
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* @offset: register offset from CMDQ sub system
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* @value: the specified target register value
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value);
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/**
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* cmdq_pkt_poll_mask() - Append polling command to the CMDQ packet, ask GCE to
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* execute an instruction that wait for a specified
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* hardware register to check for the value w/ mask.
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* All GCE hardware threads will be blocked by this
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* instruction.
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* @pkt: the CMDQ packet
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* @subsys: the CMDQ sub system code
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* @offset: register offset from CMDQ sub system
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* @value: the specified target register value
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* @mask: the specified target register mask
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value, u32 mask);
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/**
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* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
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* packet and call back at the end of done packet
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