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arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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@ -79,28 +79,112 @@ cpu0: cpu@0 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0 0x000>;
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reg = <0 0x000>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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};
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cpu1: cpu@1 {
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cpu1: cpu@1 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0 0x001>;
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reg = <0 0x001>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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};
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cpu2: cpu@100 {
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cpu2: cpu@100 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x100>;
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reg = <0 0x100>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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enable-method = "psci";
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operating-points-v2 = <&cluster1_opp>;
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};
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};
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cpu3: cpu@101 {
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cpu3: cpu@101 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x101>;
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reg = <0 0x101>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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enable-method = "psci";
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operating-points-v2 = <&cluster1_opp>;
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};
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp@275000000 {
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opp-hz = /bits/ 64 <275000000>;
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clock-latency-ns = <300>;
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};
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opp@500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp@550000000 {
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opp-hz = /bits/ 64 <550000000>;
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clock-latency-ns = <300>;
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};
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opp@666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp@733334000 {
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opp-hz = /bits/ 64 <733334000>;
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clock-latency-ns = <300>;
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};
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opp@1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp@1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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clock-latency-ns = <300>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp@275000000 {
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opp-hz = /bits/ 64 <275000000>;
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clock-latency-ns = <300>;
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};
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opp@500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp@550000000 {
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opp-hz = /bits/ 64 <550000000>;
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clock-latency-ns = <300>;
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};
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opp@666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp@733334000 {
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opp-hz = /bits/ 64 <733334000>;
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clock-latency-ns = <300>;
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};
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opp@1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp@1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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clock-latency-ns = <300>;
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};
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};
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};
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};
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