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PCI: Handle error return from pci_reset_bridge_secondary_bus() 

Commit 01fd61c0b9 ("PCI: Add a return type for
pci_reset_bridge_secondary_bus()") added a return value to the function to
return if a device is accessible following a reset.  Callers are not
checking the value.

Pass error code up high in the stack if device is not accessible.

Fixes: 01fd61c0b9 ("PCI: Add a return type for pci_reset_bridge_secondary_bus()")
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Sinan Kaya 2018-07-19 18:04:09 -05:00 committed by Bjorn Helgaas
parent 51259d0022
commit 1842623850
4 changed files with 16 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/pci/hotplug/pciehp_hpc.c
View File

@ -728,6 +728,7 @@ int pciehp_reset_slot(struct slot *slot, int probe)
struct controller *ctrl = slot->ctrl; struct controller *ctrl = slot->ctrl;
struct pci_dev *pdev = ctrl_dev(ctrl); struct pci_dev *pdev = ctrl_dev(ctrl);
u16 stat_mask = 0, ctrl_mask = 0; u16 stat_mask = 0, ctrl_mask = 0;
int rc;
if (probe) if (probe)
return 0; return 0;
@ -745,7 +746,7 @@ int pciehp_reset_slot(struct slot *slot, int probe)
if (pciehp_poll_mode) if (pciehp_poll_mode)
del_timer_sync(&ctrl->poll_timer); del_timer_sync(&ctrl->poll_timer);
pci_reset_bridge_secondary_bus(ctrl->pcie->port); rc = pci_reset_bridge_secondary_bus(ctrl->pcie->port);
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
@ -753,7 +754,7 @@ int pciehp_reset_slot(struct slot *slot, int probe)
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
if (pciehp_poll_mode) if (pciehp_poll_mode)
int_poll_timeout(&ctrl->poll_timer); int_poll_timeout(&ctrl->poll_timer);
return 0; return rc;
} }
int pcie_init_notification(struct controller *ctrl) int pcie_init_notification(struct controller *ctrl)

12
drivers/pci/pci.c
View File

@ -4253,9 +4253,7 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
if (probe) if (probe)
return 0; return 0;
pci_reset_bridge_secondary_bus(dev->bus->self); return pci_reset_bridge_secondary_bus(dev->bus->self);
return 0;
} }
static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
@ -4850,6 +4848,8 @@ EXPORT_SYMBOL_GPL(pci_try_reset_slot);
static int pci_bus_reset(struct pci_bus *bus, int probe) static int pci_bus_reset(struct pci_bus *bus, int probe)
{ {
int ret;
if (!bus->self || !pci_bus_resetable(bus)) if (!bus->self || !pci_bus_resetable(bus))
return -ENOTTY; return -ENOTTY;
@ -4860,11 +4860,11 @@ static int pci_bus_reset(struct pci_bus *bus, int probe)
might_sleep(); might_sleep();
pci_reset_bridge_secondary_bus(bus->self); ret = pci_reset_bridge_secondary_bus(bus->self);
pci_bus_unlock(bus); pci_bus_unlock(bus);
return 0; return ret;
} }
/** /**
@ -4924,7 +4924,7 @@ int pci_try_reset_bus(struct pci_bus *bus)
if (pci_bus_trylock(bus)) { if (pci_bus_trylock(bus)) {
might_sleep(); might_sleep();
pci_reset_bridge_secondary_bus(bus->self); rc = pci_reset_bridge_secondary_bus(bus->self);
pci_bus_unlock(bus); pci_bus_unlock(bus);
} else } else
rc = -EAGAIN; rc = -EAGAIN;

5
drivers/pci/pcie/aer.c
View File

@ -1305,6 +1305,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
{ {
u32 reg32; u32 reg32;
int pos; int pos;
int rc;
pos = dev->aer_cap; pos = dev->aer_cap;
@ -1313,7 +1314,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
pci_reset_bridge_secondary_bus(dev); rc = pci_reset_bridge_secondary_bus(dev);
pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n"); pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n");
/* Clear Root Error Status */ /* Clear Root Error Status */
@ -1325,7 +1326,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
return PCI_ERS_RESULT_RECOVERED; return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
} }
/** /**

6
drivers/pci/pcie/err.c
View File

@ -175,9 +175,11 @@ out:
*/ */
static pci_ers_result_t default_reset_link(struct pci_dev *dev) static pci_ers_result_t default_reset_link(struct pci_dev *dev)
{ {
pci_reset_bridge_secondary_bus(dev); int rc;
rc = pci_reset_bridge_secondary_bus(dev);
pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n"); pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n");
return PCI_ERS_RESULT_RECOVERED; return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
} }
static pci_ers_result_t reset_link(struct pci_dev *dev, u32 service) static pci_ers_result_t reset_link(struct pci_dev *dev, u32 service)