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dmaengine: PL08x: convert to use vchan done list
Convert to use the virtual dma channel done list, tasklet, and descriptor freeing. Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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parent
879f127bb2
commit
18536134ab
1 changed files with 54 additions and 81 deletions
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@ -167,16 +167,16 @@ struct pl08x_sg {
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/**
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* struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
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* @vd: virtual DMA descriptor
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* @node: node for txd list for channels
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* @dsg_list: list of children sg's
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* @llis_bus: DMA memory address (physical) start for the LLIs
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* @llis_va: virtual memory address start for the LLIs
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* @cctl: control reg values for current txd
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* @ccfg: config reg values for current txd
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* @done: this marks completed descriptors, which should not have their
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* mux released.
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*/
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struct pl08x_txd {
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struct virt_dma_desc vd;
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struct list_head node;
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struct list_head dsg_list;
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dma_addr_t llis_bus;
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struct pl08x_lli *llis_va;
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@ -187,6 +187,7 @@ struct pl08x_txd {
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* trigger this txd. Other registers are in llis_va[0].
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*/
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u32 ccfg;
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bool done;
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};
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/**
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@ -211,11 +212,9 @@ enum pl08x_dma_chan_state {
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* struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
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* @vc: wrappped virtual channel
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* @phychan: the physical channel utilized by this channel, if there is one
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* @tasklet: tasklet scheduled by the IRQ to handle actual work etc
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* @name: name of channel
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* @cd: channel platform data
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* @runtime_addr: address for RX/TX according to the runtime config
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* @done_list: list of completed transactions
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* @at: active transaction on this channel
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* @lock: a lock for this channel data
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* @host: a pointer to the host (internal use)
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@ -227,11 +226,9 @@ enum pl08x_dma_chan_state {
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struct pl08x_dma_chan {
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struct virt_dma_chan vc;
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struct pl08x_phy_chan *phychan;
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struct tasklet_struct tasklet;
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const char *name;
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const struct pl08x_channel_data *cd;
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struct dma_slave_config cfg;
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struct list_head done_list;
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struct pl08x_txd *at;
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struct pl08x_driver_data *host;
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enum pl08x_dma_chan_state state;
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@ -1084,6 +1081,52 @@ static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
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kfree(txd);
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}
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static void pl08x_unmap_buffers(struct pl08x_txd *txd)
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{
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struct device *dev = txd->vd.tx.chan->device->dev;
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struct pl08x_sg *dsg;
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if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_single(dev, dsg->src_addr, dsg->len,
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DMA_TO_DEVICE);
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else {
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_page(dev, dsg->src_addr, dsg->len,
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DMA_TO_DEVICE);
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}
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}
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if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
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if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_single(dev, dsg->dst_addr, dsg->len,
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DMA_FROM_DEVICE);
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else
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_page(dev, dsg->dst_addr, dsg->len,
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DMA_FROM_DEVICE);
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}
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}
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static void pl08x_desc_free(struct virt_dma_desc *vd)
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{
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struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
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struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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unsigned long flags;
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if (!plchan->slave)
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pl08x_unmap_buffers(txd);
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if (!txd->done)
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pl08x_release_mux(plchan);
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spin_lock_irqsave(&pl08x->lock, flags);
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pl08x_free_txd(plchan->host, txd);
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spin_unlock_irqrestore(&pl08x->lock, flags);
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}
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static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
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struct pl08x_dma_chan *plchan)
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{
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@ -1094,9 +1137,8 @@ static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
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while (!list_empty(&head)) {
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txd = list_first_entry(&head, struct pl08x_txd, vd.node);
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pl08x_release_mux(plchan);
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list_del(&txd->vd.node);
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pl08x_free_txd(pl08x, txd);
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pl08x_desc_free(&txd->vd);
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}
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}
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@ -1541,9 +1583,7 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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}
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/* Dequeue jobs and free LLIs */
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if (plchan->at) {
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/* Killing this one off, release its mux */
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pl08x_release_mux(plchan);
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pl08x_free_txd(pl08x, plchan->at);
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pl08x_desc_free(&plchan->at->vd);
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plchan->at = NULL;
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}
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/* Dequeue jobs not yet fired as well */
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@ -1600,68 +1640,6 @@ static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
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writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
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}
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static void pl08x_unmap_buffers(struct pl08x_txd *txd)
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{
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struct device *dev = txd->vd.tx.chan->device->dev;
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struct pl08x_sg *dsg;
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if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_single(dev, dsg->src_addr, dsg->len,
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DMA_TO_DEVICE);
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else {
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_page(dev, dsg->src_addr, dsg->len,
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DMA_TO_DEVICE);
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}
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}
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if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
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if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_single(dev, dsg->dst_addr, dsg->len,
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DMA_FROM_DEVICE);
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else
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_page(dev, dsg->dst_addr, dsg->len,
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DMA_FROM_DEVICE);
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}
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}
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static void pl08x_tasklet(unsigned long data)
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{
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struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
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struct pl08x_driver_data *pl08x = plchan->host;
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&plchan->vc.lock, flags);
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list_splice_tail_init(&plchan->done_list, &head);
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spin_unlock_irqrestore(&plchan->vc.lock, flags);
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while (!list_empty(&head)) {
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struct pl08x_txd *txd = list_first_entry(&head,
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struct pl08x_txd, node);
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dma_async_tx_callback callback = txd->vd.tx.callback;
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void *callback_param = txd->vd.tx.callback_param;
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list_del(&txd->node);
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/* Don't try to unmap buffers on slave channels */
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if (!plchan->slave)
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pl08x_unmap_buffers(txd);
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/* Free the descriptor */
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spin_lock_irqsave(&plchan->vc.lock, flags);
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pl08x_free_txd(pl08x, txd);
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spin_unlock_irqrestore(&plchan->vc.lock, flags);
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/* Callback to signal completion */
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if (callback)
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callback(callback_param);
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}
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}
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static irqreturn_t pl08x_irq(int irq, void *dev)
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{
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struct pl08x_driver_data *pl08x = dev;
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@ -1704,8 +1682,8 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
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* reservation.
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*/
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pl08x_release_mux(plchan);
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dma_cookie_complete(&tx->vd.tx);
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list_add_tail(&tx->node, &plchan->done_list);
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tx->done = true;
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vchan_cookie_complete(&tx->vd);
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/*
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* And start the next descriptor (if any),
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@ -1718,8 +1696,6 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
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}
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spin_unlock(&plchan->vc.lock);
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/* Schedule tasklet on this channel */
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tasklet_schedule(&plchan->tasklet);
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mask |= (1 << i);
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}
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}
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@ -1779,10 +1755,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
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"initialize virtual channel \"%s\"\n",
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chan->name);
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INIT_LIST_HEAD(&chan->done_list);
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tasklet_init(&chan->tasklet, pl08x_tasklet,
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(unsigned long) chan);
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chan->vc.desc_free = pl08x_desc_free;
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vchan_init(&chan->vc, dmadev);
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}
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dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
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