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phy: qcom: qmp-combo: reuse register layouts for even more registers
Instead of passing additional registers to qmp_combo_configure_dp_swing(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
parent
8447fa7f7e
commit
186ad90aa4
3 changed files with 76 additions and 33 deletions
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@ -113,6 +113,10 @@ enum qphy_reg_layout {
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QPHY_DP_PHY_STATUS,
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QPHY_DP_PHY_STATUS,
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QPHY_TX_TX_POL_INV,
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QPHY_TX_TX_DRV_LVL,
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QPHY_TX_TX_EMP_POST1_LVL,
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/* Keep last to ensure regs_layout arrays are properly initialized */
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/* Keep last to ensure regs_layout arrays are properly initialized */
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QPHY_LAYOUT_SIZE
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QPHY_LAYOUT_SIZE
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};
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};
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@ -130,6 +134,10 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS,
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[QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS,
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[QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS,
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[QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS,
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[QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV,
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[QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL,
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[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL,
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};
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};
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static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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@ -147,6 +155,31 @@ static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS,
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[QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS,
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[QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS,
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[QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS,
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[QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV,
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[QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL,
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[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL,
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};
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static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
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/* In PCS_USB */
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[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
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[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
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[QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL,
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[QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS,
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[QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS,
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[QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS,
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[QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV,
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[QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL,
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[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
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};
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};
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static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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@ -164,6 +197,10 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
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[QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
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[QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
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[QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
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[QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV,
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[QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL,
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[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL,
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};
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
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static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
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@ -1648,7 +1685,7 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.vreg_list = qmp_phy_vreg_l,
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = qmp_v45_usb3phy_regs_layout,
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.regs = qmp_v5_5nm_usb3phy_regs_layout,
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};
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};
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static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
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static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
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@ -1942,8 +1979,7 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
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qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
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qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
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}
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}
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static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
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static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
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unsigned int drv_lvl_reg, unsigned int emp_post_reg)
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{
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{
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const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
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const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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@ -1972,10 +2008,10 @@ static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
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voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
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voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
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pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
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pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
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writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg);
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writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg);
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writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg);
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writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg);
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writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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return 0;
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return 0;
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}
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}
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@ -1985,8 +2021,7 @@ static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
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const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
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const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
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u32 bias_en, drvr_en;
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u32 bias_en, drvr_en;
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if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL,
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if (qmp_combo_configure_dp_swing(qmp) < 0)
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QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
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return;
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return;
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if (dp_opts->lanes == 1) {
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if (dp_opts->lanes == 1) {
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@ -2174,15 +2209,16 @@ static void qmp_v6_dp_aux_init(struct qmp_combo *qmp)
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static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
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static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
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{
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{
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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/* Program default values before writing proper values */
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/* Program default values before writing proper values */
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writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL,
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qmp_combo_configure_dp_swing(qmp);
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QSERDES_V4_TX_TX_EMP_POST1_LVL);
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}
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}
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static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
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static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
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@ -2326,14 +2362,16 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
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10000))
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10000))
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
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writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
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writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
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writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
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writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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return 0;
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return 0;
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return 0;
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}
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}
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@ -2384,14 +2422,14 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp)
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10000))
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10000))
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV);
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writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
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writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV);
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writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
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writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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return 0;
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return 0;
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}
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}
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10000))
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10000))
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
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writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
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writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
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writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
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writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
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writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
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writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
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writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
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return 0;
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return 0;
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}
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}
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#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
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#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
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#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
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#define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
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#define QSERDES_V6_TX_TX_DRV_LVL 0x14
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#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
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#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
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#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
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#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
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#define QSERDES_V6_TX_TX_BAND 0x24
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#define QSERDES_V6_TX_TX_BAND 0x24
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#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
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#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
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#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
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#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
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#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40
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#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40
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#define QSERDES_V6_TX_TX_POL_INV 0x5c
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#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
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#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
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#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
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#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
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#define QSERDES_V6_TX_LANE_MODE_1 0x84
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#define QSERDES_V6_TX_LANE_MODE_1 0x84
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#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
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#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
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#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
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#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
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#define QSERDES_V5_DP_PHY_STATUS 0x0dc
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/* Only for QMP V6 PHY - DP PHY registers */
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/* Only for QMP V6 PHY - DP PHY registers */
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#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
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#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
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#define QSERDES_V6_DP_PHY_STATUS 0x0e4
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#define QSERDES_V6_DP_PHY_STATUS 0x0e4
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