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drm/amdgpu/gfx9: allow updating gfx mgpg state
Wire up the functions to control medium grained powergating. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 50 additions and 0 deletions
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@ -1992,6 +1992,34 @@ static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
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data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
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}
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void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t data, default_data;
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default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
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if (enable == true)
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data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
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else
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data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
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if(default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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}
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void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t data, default_data;
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default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
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if (enable == true)
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data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
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else
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data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
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if(default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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}
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static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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{
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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@ -3259,6 +3287,25 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
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/* gfx_v9_0_exit_rlc_safe_mode(adev); */
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}
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static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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/* TODO: double check if we need to perform under safe mode */
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/* gfx_v9_0_enter_rlc_safe_mode(adev); */
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if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
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gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
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else
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gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
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if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
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gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
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else
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gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
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/* gfx_v9_0_exit_rlc_safe_mode(adev); */
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}
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static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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@ -3469,6 +3516,9 @@ static int gfx_v9_0_set_powergating_state(void *handle,
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/* update gfx cgpg state */
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gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
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/* update mgcg state */
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gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
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break;
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default:
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break;
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