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clk: qcom: gcc-sm8550: switch to parent_hws
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103145515.1164020-15-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
Bjorn Andersson
parent
1b299e87b1
commit
18aa0dc22d
1 changed files with 126 additions and 126 deletions
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@ -82,8 +82,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_gpll0_out_even",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_gpll0.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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@ -1198,8 +1198,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1232,8 +1232,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre_ufs_phy_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_ufs_phy_axi_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1252,8 +1252,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_ufs_phy_axi_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1272,8 +1272,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre_usb3_prim_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_usb30_prim_master_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1352,8 +1352,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cfg_noc_usb3_prim_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_usb30_prim_master_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1430,8 +1430,8 @@ static struct clk_branch gcc_gp1_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gp1_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gp1_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_gp1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1448,8 +1448,8 @@ static struct clk_branch gcc_gp2_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gp2_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gp2_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_gp2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1466,8 +1466,8 @@ static struct clk_branch gcc_gp3_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gp3_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gp3_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_gp3_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1483,8 +1483,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_gpll0_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_gpll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1500,8 +1500,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
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.enable_mask = BIT(16),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_gpll0_div_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0_out_even.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_gpll0_out_even.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1546,8 +1546,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
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.enable_mask = BIT(3),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_0_aux_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pcie_0_aux_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1594,8 +1594,8 @@ static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
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.enable_mask = BIT(22),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_0_phy_rchng_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1612,8 +1612,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_0_pipe_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pcie_0_pipe_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1658,8 +1658,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
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.enable_mask = BIT(29),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_1_aux_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pcie_1_aux_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1706,8 +1706,8 @@ static struct clk_branch gcc_pcie_1_phy_aux_clk = {
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.enable_mask = BIT(24),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_1_phy_aux_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1724,8 +1724,8 @@ static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
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.enable_mask = BIT(23),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_1_phy_rchng_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1742,8 +1742,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
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.enable_mask = BIT(30),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_1_pipe_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pcie_1_pipe_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1788,8 +1788,8 @@ static struct clk_branch gcc_pdm2_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pdm2_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pdm2_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_pdm2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1982,8 +1982,8 @@ static struct clk_branch gcc_qupv3_i2c_s0_clk = {
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.enable_mask = BIT(10),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s0_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s0_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2000,8 +2000,8 @@ static struct clk_branch gcc_qupv3_i2c_s1_clk = {
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s1_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s1_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2018,8 +2018,8 @@ static struct clk_branch gcc_qupv3_i2c_s2_clk = {
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.enable_mask = BIT(12),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s2_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s2_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2036,8 +2036,8 @@ static struct clk_branch gcc_qupv3_i2c_s3_clk = {
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.enable_mask = BIT(13),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s3_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s3_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s3_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2054,8 +2054,8 @@ static struct clk_branch gcc_qupv3_i2c_s4_clk = {
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.enable_mask = BIT(14),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s4_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s4_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s4_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2072,8 +2072,8 @@ static struct clk_branch gcc_qupv3_i2c_s5_clk = {
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s5_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s5_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s5_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2090,8 +2090,8 @@ static struct clk_branch gcc_qupv3_i2c_s6_clk = {
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.enable_mask = BIT(16),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s6_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s6_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s6_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2108,8 +2108,8 @@ static struct clk_branch gcc_qupv3_i2c_s7_clk = {
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.enable_mask = BIT(17),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s7_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s7_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s7_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2126,8 +2126,8 @@ static struct clk_branch gcc_qupv3_i2c_s8_clk = {
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.enable_mask = BIT(14),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s8_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s8_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s8_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2144,8 +2144,8 @@ static struct clk_branch gcc_qupv3_i2c_s9_clk = {
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_i2c_s9_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_i2c_s9_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&gcc_qupv3_i2c_s9_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2203,8 +2203,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
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.enable_mask = BIT(22),
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||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2221,8 +2221,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
|
|||
.enable_mask = BIT(23),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2239,8 +2239,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
|
|||
.enable_mask = BIT(24),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s2_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2257,8 +2257,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
|
|||
.enable_mask = BIT(25),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s3_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2275,8 +2275,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
|
|||
.enable_mask = BIT(26),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s4_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2293,8 +2293,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
|
|||
.enable_mask = BIT(27),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s5_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2311,8 +2311,8 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
|
|||
.enable_mask = BIT(28),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s6_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2329,8 +2329,8 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
|
|||
.enable_mask = BIT(16),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s7_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2373,8 +2373,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
|
|||
.enable_mask = BIT(4),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2391,8 +2391,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
|
|||
.enable_mask = BIT(5),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2409,8 +2409,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
|
|||
.enable_mask = BIT(6),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s2_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2427,8 +2427,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
|
|||
.enable_mask = BIT(7),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s3_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2445,8 +2445,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
|
|||
.enable_mask = BIT(8),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s4_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2463,8 +2463,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
|
|||
.enable_mask = BIT(9),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s5_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2481,8 +2481,8 @@ static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
|
|||
.enable_mask = BIT(10),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s6_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2499,8 +2499,8 @@ static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
|
|||
.enable_mask = BIT(17),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap2_s7_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2590,8 +2590,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc2_apps_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_sdcc2_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2621,8 +2621,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc4_apps_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_sdcc4_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2656,8 +2656,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_axi_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_axi_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2676,8 +2676,8 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
|
|||
.enable_mask = BIT(1),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_axi_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2696,8 +2696,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_ice_core_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2716,8 +2716,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
|
|||
.enable_mask = BIT(1),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2736,8 +2736,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_phy_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2756,8 +2756,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
|
|||
.enable_mask = BIT(1),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2774,8 +2774,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_rx_symbol_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2792,8 +2792,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_rx_symbol_1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2810,8 +2810,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_tx_symbol_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2830,8 +2830,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_unipro_core_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2850,8 +2850,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
|
|||
.enable_mask = BIT(1),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2868,8 +2868,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_prim_master_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_usb30_prim_master_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2886,8 +2886,8 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_prim_mock_utmi_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2917,8 +2917,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2935,8 +2935,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_com_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2955,8 +2955,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_pipe_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
|
|||
Loading…
Reference in a new issue