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MIPS: Add function for flushing the TLB using the TLBINV instruction
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6136/
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@ -704,6 +704,19 @@ static inline int mm_insn_16bit(u16 insn)
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return (opcode >= 1 && opcode <= 3) ? 1 : 0;
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}
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/*
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* TLB Invalidate Flush
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*/
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static inline void tlbinvf(void)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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".word 0x42000004\n\t" /* tlbinvf */
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".set pop");
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}
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/*
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* Functions to access the R10000 performance counters. These are basically
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* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
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