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drm/amd/powerplay: skip soc clk setting under pp one vf

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Under sriov pp one vf mode, there is no need to set
soc clk under pp one vf because smu firmware will depend
on the mclk to set the appropriate soc clk for it.

Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by : Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yintian Tao 2019-12-17 11:43:40 +08:00 committed by Alex Deucher
parent 8c23056bdc
commit 198e36bacb
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
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@ -3538,7 +3538,8 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
if (!data->registry_data.mclk_dpm_key_disabled) {
if (data->smc_state_table.mem_boot_level !=
data->dpm_table.mem_table.dpm_state.soft_min_level) {
if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
&& hwmgr->not_vf) {
socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinSocclkByIndex,