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Memory controller drivers for v6.9, part two

Browse source 
1. Renesas RPC-IF: add bindings for R-Car V4M.
 2. Tegra MC: correct and extend support for Tegra234 memory controller.
 3. STM32: add support for Flexible Memory Controller on MP25 SoC.
 4. NXP WEIM bindings: convert to DT schema.
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Merge tag 'memory-controller-drv-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.9, part two

1. Renesas RPC-IF: add bindings for R-Car V4M.
2. Tegra MC: correct and extend support for Tegra234 memory controller.
3. STM32: add support for Flexible Memory Controller on MP25 SoC.
4. NXP WEIM bindings: convert to DT schema.

* tag 'memory-controller-drv-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: stm32-fmc2-ebi: keep power domain on
  memory: stm32-fmc2-ebi: add MP25 RIF support
  memory: stm32-fmc2-ebi: add MP25 support
  memory: stm32-fmc2-ebi: check regmap_read return value
  dt-bindings: memory-controller: st,stm32: add MP25 support
  dt-bindings: bus: imx-weim: convert to YAML
  memory: tegra: Fix indentation
  memory: tegra: Add BPMP and ICC info for DLA clients
  memory: tegra: Correct DLA client names
  dt-bindings: memory: renesas,rpc-if: Document R-Car V4M support

Link: https://lore.kernel.org/r/20240229124600.405016-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-04 16:59:48 +01:00
commit 19a4eaaef2
9 changed files with 963 additions and 177 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

117
Documentation/devicetree/bindings/bus/imx-weim.txt
View file

@ -1,117 +0,0 @@
Device tree bindings for i.MX Wireless External Interface Module (WEIM)
The term "wireless" does not imply that the WEIM is literally an interface
without wires. It simply means that this module was originally designed for
wireless and mobile applications that use low-power technology.
The actual devices are instantiated from the child nodes of a WEIM node.
Required properties:
- compatible: Should contain one of the following:
"fsl,imx1-weim"
"fsl,imx27-weim"
"fsl,imx51-weim"
"fsl,imx50-weim"
"fsl,imx6q-weim"
- reg: A resource specifier for the register space
(see the example below)
- clocks: the clock, see the example below.
- #address-cells: Must be set to 2 to allow memory address translation
- #size-cells: Must be set to 1 to allow CS address passing
- ranges: Must be set up to reflect the memory layout with four
integer values for each chip-select line in use:
<cs-number> 0 <physical address of mapping> <size>
Optional properties:
- fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
devices, it should be the phandle to the system General
Purpose Register controller that contains WEIM CS GPR
register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
should be set up as one of the following 4 possible
values depending on the CS space configuration.
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
---------------------------------------------
05 128M 0M 0M 0M
033 64M 64M 0M 0M
0113 64M 32M 32M 0M
01111 32M 32M 32M 32M
In case that the property is absent, the reset value or
what bootloader sets up in IOMUXC_GPR1[11:0] will be
used.
- fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
devices, the presence of this property indicates that
the weim bus should operate in Burst Clock Mode.
- fsl,continuous-burst-clk Make Burst Clock to output continuous clock.
Without this option Burst Clock will output clock
only when necessary. This takes effect only if
"fsl,burst-clk-enable" is set.
Timing property for child nodes. It is mandatory, not optional.
- fsl,weim-cs-timing: The timing array, contains timing values for the
child node. We get the CS indexes from the address
ranges in the child node's "reg" property.
The number of registers depends on the selected chip:
For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
registers: CSxU, CSxL.
For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
there are three registers: CSCRxU, CSCRxL, CSCRxA.
For i.MX50, i.MX53 ("fsl,imx50-weim"),
i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
CSxRCR2, CSxWCR1, CSxWCR2.
Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
weim: weim@21b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
clocks = <&clks 196>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
fsl,weim-cs-gpr = <&gpr>;
nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};
Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
In this case, both chip select 0 and 1 will be configured with the same timing
array values.
weim: weim@21b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
clocks = <&clks 196>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x02000000
1 0 0x0a000000 0x02000000
2 0 0x0c000000 0x02000000
3 0 0x0e000000 0x02000000>;
fsl,weim-cs-gpr = <&gpr>;
acme@0 {
compatible = "acme,whatever";
reg = <0 0 0x100>, <0 0x400000 0x800>,
<1 0x400000 0x800>;
fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
0x00000000 0xa0000240 0x00000000>;
};
};

31
Documentation/devicetree/bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml Normal file
View file

@ -0,0 +1,31 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX WEIM Bus Peripheral Nodes
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Sascha Hauer <s.hauer@pengutronix.de>
description:
This binding is meant for the child nodes of the WEIM node. The node
represents any device connected to the WEIM bus. It may be a Flash chip,
RAM chip or Ethernet controller, etc. These properties are meant for
configuring the WEIM settings/timings and will accompany the bindings
supported by the respective device.
properties:
reg: true
fsl,weim-cs-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Timing values for the child node.
minItems: 2
maxItems: 6
# the WEIM child will have its own native properties
additionalProperties: true

204
Documentation/devicetree/bindings/memory-controllers/fsl/fsl,imx-weim.yaml Normal file
View file

@ -0,0 +1,204 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX Wireless External Interface Module (WEIM)
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Sascha Hauer <s.hauer@pengutronix.de>
description:
The term "wireless" does not imply that the WEIM is literally an interface
without wires. It simply means that this module was originally designed for
wireless and mobile applications that use low-power technology. The actual
devices are instantiated from the child nodes of a WEIM node.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- fsl,imx1-weim
- fsl,imx27-weim
- fsl,imx50-weim
- fsl,imx51-weim
- fsl,imx6q-weim
- items:
- enum:
- fsl,imx31-weim
- fsl,imx35-weim
- const: fsl,imx27-weim
- items:
- enum:
- fsl,imx6sx-weim
- fsl,imx6ul-weim
- const: fsl,imx6q-weim
"#address-cells":
const: 2
"#size-cells":
const: 1
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
ranges: true
fsl,weim-cs-gpr:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the system General Purpose Register controller that contains
WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
should be set up as one of the following 4 possible values depending on
the CS space configuration.
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
---------------------------------------------
05 128M 0M 0M 0M
033 64M 64M 0M 0M
0113 64M 32M 32M 0M
01111 32M 32M 32M 32M
In case that the property is absent, the reset value or what bootloader
sets up in IOMUXC_GPR1[11:0] will be used.
fsl,burst-clk-enable:
type: boolean
description:
The presence of this property indicates that the weim bus should operate
in Burst Clock Mode.
fsl,continuous-burst-clk:
type: boolean
description:
Make Burst Clock to output continuous clock. Without this option Burst
Clock will output clock only when necessary.
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
type: object
description: Devices attached to chip selects are represented as subnodes.
$ref: fsl,imx-weim-peripherals.yaml
additionalProperties: true
required:
- fsl,weim-cs-timing
required:
- compatible
- reg
- clocks
- "#address-cells"
- "#size-cells"
- ranges
allOf:
- if:
properties:
compatible:
not:
contains:
enum:
- fsl,imx50-weim
- fsl,imx6q-weim
then:
properties:
fsl,weim-cs-gpr: false
fsl,burst-clk-enable: false
- if:
not:
required:
- fsl,burst-clk-enable
then:
properties:
fsl,continuous-burst-clk: false
- if:
properties:
compatible:
contains:
const: fsl,imx1-weim
then:
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
properties:
fsl,weim-cs-timing:
items:
items:
- description: CSxU
- description: CSxL
- if:
properties:
compatible:
contains:
enum:
- fsl,imx27-weim
- fsl,imx31-weim
- fsl,imx35-weim
then:
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
properties:
fsl,weim-cs-timing:
items:
items:
- description: CSCRxU
- description: CSCRxL
- description: CSCRxA
- if:
properties:
compatible:
contains:
enum:
- fsl,imx50-weim
- fsl,imx51-weim
- fsl,imx6q-weim
- fsl,imx6sx-weim
- fsl,imx6ul-weim
then:
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
properties:
fsl,weim-cs-timing:
items:
items:
- description: CSxGCR1
- description: CSxGCR2
- description: CSxRCR1
- description: CSxRCR2
- description: CSxWCR1
- description: CSxWCR2
additionalProperties: false
examples:
- |
memory-controller@21b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
clocks = <&clks 196>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
fsl,weim-cs-gpr = <&gpr>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};

1
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
View file

@ -37,5 +37,6 @@ allOf:
- $ref: ingenic,nemc-peripherals.yaml#
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
- $ref: ti,gpmc-child.yaml#
- $ref: fsl/fsl,imx-weim-peripherals.yaml
additionalProperties: true

1
Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
View file

@ -45,6 +45,7 @@ properties:
- items:
- enum:
- renesas,r8a779g0-rpc-if # R-Car V4H
- renesas,r8a779h0-rpc-if # R-Car V4M
- const: renesas,rcar-gen4-rpc-if # a generic R-Car gen4 device
- items:

7
Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
View file

@ -23,7 +23,9 @@ maintainers:
properties:
compatible:
const: st,stm32mp1-fmc2-ebi
enum:
- st,stm32mp1-fmc2-ebi
- st,stm32mp25-fmc2-ebi
reg:
maxItems: 1
@ -34,6 +36,9 @@ properties:
resets:
maxItems: 1
power-domains:
maxItems: 1
"#address-cells":
const: 2

729
drivers/memory/stm32-fmc2-ebi.c
View file

File diff suppressed because it is too large Load diff

48
drivers/memory/tegra/tegra234.c
View file

@ -92,6 +92,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
.name = "dla0rdb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -102,6 +104,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
.name = "dla0rdb1",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -112,6 +116,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
.name = "dla0wrb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -121,7 +127,9 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
.name = "dla0rdb",
.name = "dla1rdb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
@ -407,7 +415,9 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
.name = "dla0rdb1",
.name = "dla1rdb1",
.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
@ -417,7 +427,9 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
.name = "dla0wrb",
.name = "dla1wrb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
@ -539,7 +551,7 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVJPG,
.regs = {
.regs = {
.sid = {
.override = 0x3f8,
.security = 0x3fc,
@ -660,6 +672,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -670,6 +684,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB,
.name = "dla0falrdb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -680,6 +696,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0WRA,
.name = "dla0wra",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -690,6 +708,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -699,7 +719,9 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
.name = "dla0rda",
.name = "dla1rda",
.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
@ -709,7 +731,9 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB,
.name = "dla0falrdb",
.name = "dla1falrdb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
@ -719,7 +743,9 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1WRA,
.name = "dla0wra",
.name = "dla1wra",
.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
@ -729,7 +755,9 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla0falwrb",
.name = "dla1falwrb",
.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
@ -908,6 +936,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
.name = "dla0rda1",
.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
@ -917,7 +947,7 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
.name = "dla0rda1",
.name = "dla1rda1",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {

2
drivers/staging/fieldbus/Documentation/devicetree/bindings/fieldbus/arcx,anybus-controller.txt
View file

@ -48,7 +48,7 @@ Example of usage:
-----------------
This example places the bridge on top of the i.MX WEIM parallel bus, see:
Documentation/devicetree/bindings/bus/imx-weim.txt
Documentation/devicetree/bindings/memory-controllers/fsl/fsl,imx-weim.yaml
&weim {
controller@0,0 {