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mtd: bcm47xxnflash: init NAND on BCM4706
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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2 changed files with 110 additions and 0 deletions
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bcm47xxnflash-y += main.o
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bcm47xxnflash- += ops_bcm4706.o
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obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash.o
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109
drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
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109
drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
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/*
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* BCM47XX NAND flash driver
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*
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* Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/bcma/bcma.h>
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#include "bcm47xxnflash.h"
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/**************************************************
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* Various helpers
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**************************************************/
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static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
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{
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return ((ns * 1000 * clock) / 1000000) + 1;
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}
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/**************************************************
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* NAND chip ops
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**************************************************/
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/* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
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static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
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int chip)
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{
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return;
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}
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/**************************************************
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* Init
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**************************************************/
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int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
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{
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int err;
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u32 freq;
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u16 clock;
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u8 w0, w1, w2, w3, w4;
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unsigned long chipsize; /* MiB */
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u8 tbits, col_bits, col_size, row_bits, row_bsize;
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u32 val;
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b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
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b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
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/* Enable NAND flash access */
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bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
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BCMA_CC_4706_FLASHSCFG_NF1);
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/* Configure wait counters */
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if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
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freq = 100000000;
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} else {
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freq = bcma_chipco_pll_read(b47n->cc, 4);
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freq = (freq * 0xFFF) >> 3;
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freq = (freq * 25000000) >> 3;
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}
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clock = freq / 1000000;
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w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
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w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
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w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
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w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
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w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
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bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
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(w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
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/* Scan NAND */
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err = nand_scan(&b47n->mtd, 1);
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if (err) {
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pr_err("Could not scan NAND flash: %d\n", err);
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goto exit;
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}
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/* Configure FLASH */
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chipsize = b47n->nand_chip.chipsize >> 20;
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tbits = ffs(chipsize); /* find first bit set */
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if (!tbits || tbits != fls(chipsize)) {
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pr_err("Invalid flash size: 0x%lX\n", chipsize);
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err = -ENOTSUPP;
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goto exit;
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}
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tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
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col_bits = b47n->nand_chip.page_shift + 1;
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col_size = (col_bits + 7) / 8;
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row_bits = tbits - col_bits + 1;
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row_bsize = (row_bits + 7) / 8;
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val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
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bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
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exit:
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if (err)
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bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
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~BCMA_CC_4706_FLASHSCFG_NF1);
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return err;
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}
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