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drm/amdgpu: add the CI code to enable clock level selection
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8b2e574dc4
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19fbc43a86
1 changed files with 114 additions and 0 deletions
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@ -6414,6 +6414,118 @@ static int ci_dpm_set_powergating_state(void *handle,
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return 0;
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}
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static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
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enum pp_clock_type type, char *buf)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
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struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
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struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
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int i, now, size = 0;
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uint32_t clock, pcie_speed;
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switch (type) {
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case PP_SCLK:
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amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
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clock = RREG32(mmSMC_MSG_ARG_0);
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for (i = 0; i < sclk_table->count; i++) {
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if (clock > sclk_table->dpm_levels[i].value)
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continue;
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break;
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}
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now = i;
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for (i = 0; i < sclk_table->count; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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i, sclk_table->dpm_levels[i].value / 100,
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(i == now) ? "*" : "");
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break;
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case PP_MCLK:
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amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
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clock = RREG32(mmSMC_MSG_ARG_0);
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for (i = 0; i < mclk_table->count; i++) {
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if (clock > mclk_table->dpm_levels[i].value)
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continue;
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break;
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}
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now = i;
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for (i = 0; i < mclk_table->count; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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i, mclk_table->dpm_levels[i].value / 100,
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(i == now) ? "*" : "");
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break;
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case PP_PCIE:
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pcie_speed = ci_get_current_pcie_speed(adev);
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for (i = 0; i < pcie_table->count; i++) {
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if (pcie_speed != pcie_table->dpm_levels[i].value)
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continue;
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break;
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}
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now = i;
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for (i = 0; i < pcie_table->count; i++)
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size += sprintf(buf + size, "%d: %s %s\n", i,
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(pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
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(pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
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(pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
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(i == now) ? "*" : "");
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break;
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default:
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break;
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}
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return size;
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}
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static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
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enum pp_clock_type type, uint32_t mask)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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if (adev->pm.dpm.forced_level
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!= AMDGPU_DPM_FORCED_LEVEL_MANUAL)
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return -EINVAL;
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switch (type) {
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case PP_SCLK:
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if (!pi->sclk_dpm_key_disabled)
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amdgpu_ci_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_SCLKDPM_SetEnabledMask,
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pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
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break;
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case PP_MCLK:
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if (!pi->mclk_dpm_key_disabled)
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amdgpu_ci_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_MCLKDPM_SetEnabledMask,
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pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
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break;
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case PP_PCIE:
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{
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uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
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uint32_t level = 0;
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while (tmp >>= 1)
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level++;
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if (!pi->pcie_dpm_key_disabled)
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amdgpu_ci_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_PCIeDPM_ForceLevel,
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level);
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break;
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}
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default:
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break;
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}
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return 0;
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}
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const struct amd_ip_funcs ci_dpm_ip_funcs = {
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.name = "ci_dpm",
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.early_init = ci_dpm_early_init,
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@ -6448,6 +6560,8 @@ static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
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.get_fan_control_mode = &ci_dpm_get_fan_control_mode,
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.set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
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.get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
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.print_clock_levels = ci_dpm_print_clock_levels,
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.force_clock_level = ci_dpm_force_clock_level,
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};
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static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
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