ARM: dts: stm32: add support for Protonic PRTT1x boards
This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Oleksij Rempel
Alexandre Torgue
parent
9ad65d245b
commit
1a43e9b281
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@ -1156,6 +1156,9 @@ dtb-$(CONFIG_ARCH_STM32) += \
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stm32h743i-disco.dtb \
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stm32h750i-art-pi.dtb \
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stm32mp135f-dk.dtb \
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stm32mp151a-prtt1a.dtb \
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stm32mp151a-prtt1c.dtb \
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stm32mp151a-prtt1s.dtb \
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stm32mp153c-dhcom-drc02.dtb \
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stm32mp157a-avenger96.dtb \
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stm32mp157a-dhcor-avenger96.dtb \
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@ -0,0 +1,52 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) Protonic Holland
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* Author: David Jander <david@protonic.nl>
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*/
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/dts-v1/;
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#include "stm32mp151a-prtt1l.dtsi"
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/ {
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model = "Protonic PRTT1A";
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compatible = "prt,prtt1a", "st,stm32mp151";
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};
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ðernet0 {
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phy-handle = <&phy0>;
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};
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&mdio0 {
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/* TI DP83TD510E */
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id2000.0181";
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reg = <0>;
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interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10>;
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reset-deassert-us = <35>;
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};
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};
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&pwm5_pins_a {
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pins {
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pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */
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};
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};
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&pwm5_sleep_pins_a {
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pins {
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pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* TIM5_CH1 */
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};
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};
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&timers5 {
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status = "okay";
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pwm {
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pinctrl-0 = <&pwm5_pins_a>;
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pinctrl-1 = <&pwm5_sleep_pins_a>;
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pinctrl-names = "default", "sleep";
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status = "okay";
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};
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};
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@ -0,0 +1,304 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) Protonic Holland
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* Author: David Jander <david@protonic.nl>
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*/
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/dts-v1/;
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#include "stm32mp151a-prtt1l.dtsi"
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/ {
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model = "Protonic PRTT1C";
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compatible = "prt,prtt1c", "st,stm32mp151";
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clock_ksz9031: clock-ksz9031 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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clock_sja1105: clock-sja1105 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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mdio0: mdio {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
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&gpioa 2 GPIO_ACTIVE_HIGH>;
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};
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wifi_pwrseq: wifi-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
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};
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};
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ðernet0 {
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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&gpioa {
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gpio-line-names =
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"", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "",
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"", "", "", "", "", "", "", "SPI1_nSS";
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};
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&gpiod {
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gpio-line-names =
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"", "", "", "", "", "", "", "",
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"WFM_RESET", "", "", "", "", "", "", "";
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};
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&gpioe {
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gpio-line-names =
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"SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "",
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"", "", "", "", "WFM_nIRQ", "", "", "";
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};
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&gpiog {
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gpio-line-names =
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"", "", "", "", "", "", "", "PHY3_nINT",
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"PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET",
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"PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", "";
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};
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&mdio0 {
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/* All this DP83TD510E PHYs can't be probed before switch@0 is
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* probed so we need to use compatible with PHYid
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*/
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/* TI DP83TD510E */
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t1l0_phy: ethernet-phy@6 {
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compatible = "ethernet-phy-id2000.0181";
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reg = <6>;
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interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10>;
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reset-deassert-us = <35>;
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};
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/* TI DP83TD510E */
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t1l1_phy: ethernet-phy@7 {
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compatible = "ethernet-phy-id2000.0181";
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reg = <7>;
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interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10>;
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reset-deassert-us = <35>;
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};
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/* TI DP83TD510E */
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t1l2_phy: ethernet-phy@10 {
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compatible = "ethernet-phy-id2000.0181";
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reg = <10>;
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interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10>;
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reset-deassert-us = <35>;
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};
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/* Micrel KSZ9031 */
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rj45_phy: ethernet-phy@2 {
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reg = <2>;
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interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <1000>;
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clocks = <&clock_ksz9031>;
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};
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};
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&qspi {
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status = "disabled";
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};
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&sdmmc2 {
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pinctrl-names = "default", "opendrain", "sleep";
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pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
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pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
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pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
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non-removable;
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no-sd;
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no-sdio;
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no-1-8-v;
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st,neg-edge;
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bus-width = <8>;
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vmmc-supply = <®_3v3>;
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vqmmc-supply = <®_3v3>;
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status = "okay";
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};
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&sdmmc2_b4_od_pins_a {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
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};
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};
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&sdmmc2_b4_pins_a {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
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<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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};
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};
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&sdmmc2_b4_sleep_pins_a {
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pins {
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pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
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<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
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<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
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};
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};
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&sdmmc2_d47_pins_a {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
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<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
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<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
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<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
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};
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};
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&sdmmc2_d47_sleep_pins_a {
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pins {
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pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
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<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
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<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
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<STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
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};
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};
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&sdmmc3 {
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pinctrl-names = "default", "opendrain", "sleep";
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pinctrl-0 = <&sdmmc3_b4_pins_b>;
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pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
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pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
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non-removable;
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no-1-8-v;
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st,neg-edge;
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bus-width = <4>;
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vmmc-supply = <®_3v3>;
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vqmmc-supply = <®_3v3>;
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mmc-pwrseq = <&wifi_pwrseq>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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mmc@1 {
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compatible = "prt,prtt1c-wfm200", "silabs,wf200";
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reg = <1>;
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};
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};
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&sdmmc3_b4_od_pins_b {
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pins1 {
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pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
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<STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
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<STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
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<STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
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};
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};
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&sdmmc3_b4_pins_b {
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pins1 {
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pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
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<STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
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<STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
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<STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
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<STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
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};
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};
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&sdmmc3_b4_sleep_pins_b {
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pins {
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pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
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<STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
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<STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
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<STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
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<STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
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<STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
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};
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};
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&spi1 {
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pinctrl-0 = <&spi1_pins_b>;
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pinctrl-names = "default";
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cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "okay";
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switch@0 {
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compatible = "nxp,sja1105q";
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reg = <0>;
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spi-max-frequency = <4000000>;
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spi-rx-delay-us = <1>;
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spi-tx-delay-us = <1>;
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spi-cpha;
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reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
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clocks = <&clock_sja1105>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "t1l0";
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phy-mode = "rmii";
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phy-handle = <&t1l0_phy>;
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};
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port@1 {
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reg = <1>;
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label = "t1l1";
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phy-mode = "rmii";
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phy-handle = <&t1l1_phy>;
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};
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port@2 {
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reg = <2>;
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label = "t1l2";
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phy-mode = "rmii";
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phy-handle = <&t1l2_phy>;
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};
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port@3 {
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reg = <3>;
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label = "rj45";
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phy-handle = <&rj45_phy>;
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phy-mode = "rgmii-id";
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};
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port@4 {
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reg = <4>;
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label = "cpu";
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ethernet = <ðernet0>;
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phy-mode = "rmii";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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};
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};
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@ -0,0 +1,229 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) Protonic Holland
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* Author: David Jander <david@protonic.nl>
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*/
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/dts-v1/;
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#include "stm32mp151.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxad-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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ethernet0 = ðernet0;
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mdio-gpio0 = &mdio0;
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serial0 = &uart4;
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};
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led-controller-0 {
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compatible = "gpio-leds";
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led-0 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_INDICATOR;
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gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
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};
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led-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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};
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/* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce
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* stmmac MDC clock without reducing system bus rate, we need to use
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* gpio based MDIO bus.
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*/
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mdio0: mdio {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
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&gpioa 2 GPIO_ACTIVE_HIGH>;
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};
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reg_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&dts {
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status = "okay";
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};
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ðernet0 {
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pinctrl-0 = <ðernet0_rmii_pins_a>;
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pinctrl-1 = <ðernet0_rmii_sleep_pins_a>;
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pinctrl-names = "default", "sleep";
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phy-mode = "rmii";
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status = "okay";
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};
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ðernet0_rmii_pins_a {
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pins1 {
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pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
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<STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
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<STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
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||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
|
||||
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
|
||||
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK input */
|
||||
<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0_rmii_sleep_pins_a {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */
|
||||
<STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */
|
||||
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
|
||||
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
|
||||
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
|
||||
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
|
||||
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <104000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi_bk1_pins_a {
|
||||
pins1 {
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_3v3>;
|
||||
vqmmc-supply = <®_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1_b4_od_pins_a {
|
||||
pins1 {
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1_b4_pins_a {
|
||||
pins1 {
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4_idle_pins_a {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart4_pins_a {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart4_sleep_pins_a {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */
|
||||
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
|
||||
};
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
phy-names = "usb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "host";
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <®_3v3>;
|
||||
};
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) Protonic Holland
|
||||
* Author: David Jander <david@protonic.nl>
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp151a-prtt1l.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Protonic PRTT1S";
|
||||
compatible = "prt,prtt1s", "st,stm32mp151";
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-1 = <&i2c1_sleep_pins_a>;
|
||||
clock-frequency = <100000>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
|
||||
humidity-sensor@40 {
|
||||
compatible = "ti,hdc1080";
|
||||
reg = <0x40>;
|
||||
};
|
||||
|
||||
co2-sensor@62 {
|
||||
compatible = "sensirion,scd41";
|
||||
reg = <0x62>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1_pins_a {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1_sleep_pins_a {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('D', 13, ANALOG)>; /* I2C1_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
/* TI DP83TD510E */
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id2000.0181";
|
||||
reg = <0>;
|
||||
interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10>;
|
||||
reset-deassert-us = <35>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue