drm/i915/gem: Use to_gt() helper
Use to_gt() helper consistently throughout the codebase. Pure mechanical s/i915->gt/to_gt(i915). No functional changes. Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211214193346.21231-6-andi.shyti@linux.intel.com
This commit is contained in:
parent
c14adcbd1a
commit
1a9c4db4ca
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@ -237,7 +237,7 @@ static int proto_context_set_persistence(struct drm_i915_private *i915,
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* colateral damage, and we should not pretend we can by
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* exposing the interface.
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*/
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if (!intel_has_reset_engine(&i915->gt))
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if (!intel_has_reset_engine(to_gt(i915)))
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return -ENODEV;
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pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE);
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@ -254,7 +254,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915,
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if (!protected) {
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pc->uses_protected_content = false;
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} else if (!intel_pxp_is_enabled(&i915->gt.pxp)) {
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} else if (!intel_pxp_is_enabled(&to_gt(i915)->pxp)) {
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ret = -ENODEV;
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} else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
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!(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
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@ -268,8 +268,8 @@ static int proto_context_set_protected(struct drm_i915_private *i915,
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*/
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pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm);
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if (!intel_pxp_is_active(&i915->gt.pxp))
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ret = intel_pxp_start(&i915->gt.pxp);
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if (!intel_pxp_is_active(&to_gt(i915)->pxp))
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ret = intel_pxp_start(&to_gt(i915)->pxp);
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}
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return ret;
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@ -571,7 +571,7 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
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intel_engine_mask_t prev_mask;
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/* FIXME: This is NIY for execlists */
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if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
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if (!(intel_uc_uses_guc_submission(&to_gt(i915)->uc)))
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return -ENODEV;
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if (get_user(slot, &ext->engine_index))
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@ -833,7 +833,7 @@ static int set_proto_ctx_sseu(struct drm_i915_file_private *fpriv,
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sseu = &pc->legacy_rcs_sseu;
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}
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ret = i915_gem_user_to_context_sseu(&i915->gt, &user_sseu, sseu);
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ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu);
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if (ret)
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return ret;
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@ -1044,7 +1044,7 @@ static struct i915_gem_engines *alloc_engines(unsigned int count)
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static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
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struct intel_sseu rcs_sseu)
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{
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const struct intel_gt *gt = &ctx->i915->gt;
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const struct intel_gt *gt = to_gt(ctx->i915);
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struct intel_engine_cs *engine;
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struct i915_gem_engines *e, *err;
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enum intel_engine_id id;
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@ -1521,7 +1521,7 @@ static int __context_set_persistence(struct i915_gem_context *ctx, bool state)
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* colateral damage, and we should not pretend we can by
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* exposing the interface.
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*/
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if (!intel_has_reset_engine(&ctx->i915->gt))
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if (!intel_has_reset_engine(to_gt(ctx->i915)))
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return -ENODEV;
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i915_gem_context_clear_persistence(ctx);
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@ -1559,7 +1559,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
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} else if (HAS_FULL_PPGTT(i915)) {
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struct i915_ppgtt *ppgtt;
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ppgtt = i915_ppgtt_create(&i915->gt, 0);
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ppgtt = i915_ppgtt_create(to_gt(i915), 0);
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if (IS_ERR(ppgtt)) {
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drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
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PTR_ERR(ppgtt));
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@ -1742,7 +1742,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
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if (args->flags)
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return -EINVAL;
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ppgtt = i915_ppgtt_create(&i915->gt, 0);
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ppgtt = i915_ppgtt_create(to_gt(i915), 0);
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if (IS_ERR(ppgtt))
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return PTR_ERR(ppgtt);
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@ -2194,7 +2194,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
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if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
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return -EINVAL;
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ret = intel_gt_terminally_wedged(&i915->gt);
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ret = intel_gt_terminally_wedged(to_gt(i915));
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if (ret)
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return ret;
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@ -379,7 +379,7 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data
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if (ext.flags)
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return -EINVAL;
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if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
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if (!intel_pxp_is_enabled(&to_gt(ext_data->i915)->pxp))
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return -ENODEV;
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ext_data->flags |= I915_BO_PROTECTED;
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@ -2361,9 +2361,9 @@ static int eb_submit(struct i915_execbuffer *eb)
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return err;
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}
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static int num_vcs_engines(const struct drm_i915_private *i915)
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static int num_vcs_engines(struct drm_i915_private *i915)
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{
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return hweight_long(VDBOX_MASK(&i915->gt));
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return hweight_long(VDBOX_MASK(to_gt(i915)));
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}
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/*
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@ -645,7 +645,7 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
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goto insert;
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/* Attempt to reap some mmap space from dead objects */
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err = intel_gt_retire_requests_timeout(&i915->gt, MAX_SCHEDULE_TIMEOUT,
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err = intel_gt_retire_requests_timeout(to_gt(i915), MAX_SCHEDULE_TIMEOUT,
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NULL);
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if (err)
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goto err;
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@ -19,6 +19,7 @@
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static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
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{
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struct address_space *mapping = obj->base.filp->f_mapping;
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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struct scatterlist *sg;
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struct sg_table *st;
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dma_addr_t dma;
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@ -73,7 +74,7 @@ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
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dst += PAGE_SIZE;
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}
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intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
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intel_gt_chipset_flush(to_gt(i915));
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/* We're no longer struct page backed */
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obj->mem_flags &= ~I915_BO_FLAG_STRUCT_PAGE;
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@ -140,6 +141,7 @@ int i915_gem_object_pwrite_phys(struct drm_i915_gem_object *obj,
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{
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void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
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char __user *user_data = u64_to_user_ptr(args->data_ptr);
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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int err;
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err = i915_gem_object_wait(obj,
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@ -159,7 +161,7 @@ int i915_gem_object_pwrite_phys(struct drm_i915_gem_object *obj,
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return -EFAULT;
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drm_clflush_virt_range(vaddr, args->size);
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intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
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intel_gt_chipset_flush(to_gt(i915));
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i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
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return 0;
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@ -35,7 +35,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
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* state. Fortunately, the kernel_context is disposable and we do
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* not rely on its state.
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*/
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intel_gt_suspend_prepare(&i915->gt);
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intel_gt_suspend_prepare(to_gt(i915));
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i915_gem_drain_freed_objects(i915);
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}
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@ -153,7 +153,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
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* machine in an unusable condition.
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*/
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intel_gt_suspend_late(&i915->gt);
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intel_gt_suspend_late(to_gt(i915));
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spin_lock_irqsave(&i915->mm.obj_lock, flags);
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for (phase = phases; *phase; phase++) {
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@ -223,7 +223,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
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* guarantee that the context image is complete. So let's just reset
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* it and start again.
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*/
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intel_gt_resume(&i915->gt);
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intel_gt_resume(to_gt(i915));
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ret = lmem_restore(i915, I915_TTM_BACKUP_ALLOW_GPU);
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GEM_WARN_ON(ret);
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@ -153,7 +153,7 @@ i915_gem_shrink(struct i915_gem_ww_ctx *ww,
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*/
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if (shrink & I915_SHRINK_ACTIVE)
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/* Retire requests to unpin all idle contexts */
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intel_gt_retire_requests(&i915->gt);
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intel_gt_retire_requests(to_gt(i915));
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/*
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* As we may completely rewrite the (un)bound list whilst unbinding
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@ -38,12 +38,13 @@ i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
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{
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const unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
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struct drm_i915_file_private *file_priv = file->driver_priv;
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struct drm_i915_private *i915 = to_i915(dev);
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struct i915_gem_context *ctx;
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unsigned long idx;
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long ret;
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/* ABI: return -EIO if already wedged */
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ret = intel_gt_terminally_wedged(&to_i915(dev)->gt);
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ret = intel_gt_terminally_wedged(to_gt(i915));
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if (ret)
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return ret;
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@ -397,7 +397,7 @@ static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo,
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enum i915_cache_level src_level, dst_level;
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int ret;
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if (!i915->gt.migrate.context || intel_gt_is_wedged(&i915->gt))
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if (!to_gt(i915)->migrate.context || intel_gt_is_wedged(to_gt(i915)))
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return ERR_PTR(-EINVAL);
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/* With fail_gpu_migration, we always perform a GPU clear. */
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!I915_SELFTEST_ONLY(fail_gpu_migration))
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return ERR_PTR(-EINVAL);
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intel_engine_pm_get(i915->gt.migrate.context->engine);
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ret = intel_context_migrate_clear(i915->gt.migrate.context, dep,
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intel_engine_pm_get(to_gt(i915)->migrate.context->engine);
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ret = intel_context_migrate_clear(to_gt(i915)->migrate.context, dep,
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dst_st->sgl, dst_level,
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i915_ttm_gtt_binds_lmem(dst_mem),
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0, &rq);
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@ -423,8 +423,8 @@ static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo,
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return ERR_CAST(src_rsgt);
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src_level = i915_ttm_cache_level(i915, bo->resource, src_ttm);
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intel_engine_pm_get(i915->gt.migrate.context->engine);
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ret = intel_context_migrate_copy(i915->gt.migrate.context,
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intel_engine_pm_get(to_gt(i915)->migrate.context->engine);
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ret = intel_context_migrate_copy(to_gt(i915)->migrate.context,
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dep, src_rsgt->table.sgl,
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src_level,
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i915_ttm_gtt_binds_lmem(bo->resource),
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@ -435,7 +435,7 @@ static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo,
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i915_refct_sgt_put(src_rsgt);
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}
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intel_engine_pm_put(i915->gt.migrate.context->engine);
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intel_engine_pm_put(to_gt(i915)->migrate.context->engine);
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if (ret && rq) {
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i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
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@ -529,7 +529,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
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* On almost all of the older hw, we cannot tell the GPU that
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* a page is readonly.
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*/
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if (!dev_priv->gt.vm->has_read_only)
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if (!to_gt(dev_priv)->vm->has_read_only)
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return -ENODEV;
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}
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@ -1705,7 +1705,7 @@ int i915_gem_huge_page_mock_selftests(void)
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mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
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mkwrite_device_info(dev_priv)->ppgtt_size = 48;
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ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
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ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);
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if (IS_ERR(ppgtt)) {
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err = PTR_ERR(ppgtt);
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goto out_unlock;
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@ -1747,7 +1747,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
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return 0;
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}
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if (intel_gt_is_wedged(&i915->gt))
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if (intel_gt_is_wedged(to_gt(i915)))
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return 0;
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return i915_live_subtests(tests, i915);
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@ -592,7 +592,7 @@ int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915)
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SUBTEST(igt_client_tiled_blits),
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};
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if (intel_gt_is_wedged(&i915->gt))
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if (intel_gt_is_wedged(to_gt(i915)))
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return 0;
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return i915_live_subtests(tests, i915);
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@ -90,7 +90,7 @@ static int live_nop_switch(void *arg)
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}
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if (i915_request_wait(rq, 0, 10 * HZ) < 0) {
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pr_err("Failed to populated %d contexts\n", nctx);
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intel_gt_set_wedged(&i915->gt);
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intel_gt_set_wedged(to_gt(i915));
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i915_request_put(rq);
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err = -EIO;
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goto out_file;
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@ -146,7 +146,7 @@ static int live_nop_switch(void *arg)
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if (i915_request_wait(rq, 0, HZ / 5) < 0) {
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pr_err("Switching between %ld contexts timed out\n",
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prime);
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intel_gt_set_wedged(&i915->gt);
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intel_gt_set_wedged(to_gt(i915));
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i915_request_put(rq);
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break;
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}
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@ -1223,7 +1223,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
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return 0;
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if (flags & TEST_RESET)
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igt_global_reset_lock(&i915->gt);
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igt_global_reset_lock(to_gt(i915));
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obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(obj)) {
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@ -1306,7 +1306,7 @@ out_put:
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out_unlock:
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if (flags & TEST_RESET)
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igt_global_reset_unlock(&i915->gt);
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igt_global_reset_unlock(to_gt(i915));
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if (ret)
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pr_err("%s: Failed with %d!\n", name, ret);
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@ -1877,7 +1877,7 @@ int i915_gem_context_live_selftests(struct drm_i915_private *i915)
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SUBTEST(igt_vm_isolation),
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};
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if (intel_gt_is_wedged(&i915->gt))
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if (intel_gt_is_wedged(to_gt(i915)))
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return 0;
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return i915_live_subtests(tests, i915);
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@ -261,5 +261,5 @@ int i915_gem_migrate_live_selftests(struct drm_i915_private *i915)
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if (!HAS_LMEM(i915))
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return 0;
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return intel_gt_live_subtests(tests, &i915->gt);
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return intel_gt_live_subtests(tests, to_gt(i915));
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}
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@ -84,6 +84,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
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struct rnd_state *prng)
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{
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const unsigned long npages = obj->base.size / PAGE_SIZE;
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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struct i915_ggtt_view view;
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struct i915_vma *vma;
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unsigned long page;
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@ -141,7 +142,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
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if (offset >= obj->base.size)
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goto out;
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intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
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intel_gt_flush_ggtt_writes(to_gt(i915));
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p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
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cpu = kmap(p) + offset_in_page(offset);
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@ -175,6 +176,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj,
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{
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const unsigned int nreal = obj->scratch / PAGE_SIZE;
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const unsigned long npages = obj->base.size / PAGE_SIZE;
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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struct i915_vma *vma;
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unsigned long page;
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int err;
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@ -234,7 +236,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj,
|
|||
if (offset >= obj->base.size)
|
||||
continue;
|
||||
|
||||
intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
|
||||
intel_gt_flush_ggtt_writes(to_gt(i915));
|
||||
|
||||
p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
|
||||
cpu = kmap(p) + offset_in_page(offset);
|
||||
|
@ -616,14 +618,14 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
|
|||
static void disable_retire_worker(struct drm_i915_private *i915)
|
||||
{
|
||||
i915_gem_driver_unregister__shrinker(i915);
|
||||
intel_gt_pm_get(&i915->gt);
|
||||
cancel_delayed_work_sync(&i915->gt.requests.retire_work);
|
||||
intel_gt_pm_get(to_gt(i915));
|
||||
cancel_delayed_work_sync(&to_gt(i915)->requests.retire_work);
|
||||
}
|
||||
|
||||
static void restore_retire_worker(struct drm_i915_private *i915)
|
||||
{
|
||||
igt_flush_test(i915);
|
||||
intel_gt_pm_put(&i915->gt);
|
||||
intel_gt_pm_put(to_gt(i915));
|
||||
i915_gem_driver_register__shrinker(i915);
|
||||
}
|
||||
|
||||
|
@ -651,8 +653,8 @@ static int igt_mmap_offset_exhaustion(void *arg)
|
|||
|
||||
/* Disable background reaper */
|
||||
disable_retire_worker(i915);
|
||||
GEM_BUG_ON(!i915->gt.awake);
|
||||
intel_gt_retire_requests(&i915->gt);
|
||||
GEM_BUG_ON(!to_gt(i915)->awake);
|
||||
intel_gt_retire_requests(to_gt(i915));
|
||||
i915_gem_drain_freed_objects(i915);
|
||||
|
||||
/* Trim the device mmap space to only a page */
|
||||
|
@ -728,7 +730,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
|
|||
|
||||
/* Now fill with busy dead objects that we expect to reap */
|
||||
for (loop = 0; loop < 3; loop++) {
|
||||
if (intel_gt_is_wedged(&i915->gt))
|
||||
if (intel_gt_is_wedged(to_gt(i915)))
|
||||
break;
|
||||
|
||||
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
|
||||
|
@ -942,7 +944,7 @@ static int __igt_mmap(struct drm_i915_private *i915,
|
|||
}
|
||||
|
||||
if (type == I915_MMAP_TYPE_GTT)
|
||||
intel_gt_flush_ggtt_writes(&i915->gt);
|
||||
intel_gt_flush_ggtt_writes(to_gt(i915));
|
||||
|
||||
err = wc_check(obj);
|
||||
if (err == -ENXIO)
|
||||
|
@ -1049,7 +1051,7 @@ static int __igt_mmap_access(struct drm_i915_private *i915,
|
|||
goto out_unmap;
|
||||
}
|
||||
|
||||
intel_gt_flush_ggtt_writes(&i915->gt);
|
||||
intel_gt_flush_ggtt_writes(to_gt(i915));
|
||||
|
||||
err = access_process_vm(current, addr, &x, sizeof(x), 0);
|
||||
if (err != sizeof(x)) {
|
||||
|
@ -1065,7 +1067,7 @@ static int __igt_mmap_access(struct drm_i915_private *i915,
|
|||
goto out_unmap;
|
||||
}
|
||||
|
||||
intel_gt_flush_ggtt_writes(&i915->gt);
|
||||
intel_gt_flush_ggtt_writes(to_gt(i915));
|
||||
|
||||
err = __get_user(y, ptr);
|
||||
if (err) {
|
||||
|
@ -1165,7 +1167,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
|
|||
}
|
||||
|
||||
if (type == I915_MMAP_TYPE_GTT)
|
||||
intel_gt_flush_ggtt_writes(&i915->gt);
|
||||
intel_gt_flush_ggtt_writes(to_gt(i915));
|
||||
|
||||
for_each_uabi_engine(engine, i915) {
|
||||
struct i915_request *rq;
|
||||
|
|
Loading…
Reference in New Issue