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drm/i915: Parametrize VLV_DDL registers
The VLV/CHV DDL registers are uniform, and neatly enough the register offsets are sane so we can easily unify them to a single set of defines and just pass the pipe as the parameter to compute the register offset. Note that we now fill out the drain latency for pipe C on CHV which we didn't do before. The rest of the pipe C watermarks are still untouched but that will be remedied later by adding a proper cherryview_update_wm() function. v2: Add a note about CHV pipe C changes (Paulo) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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0a56067469
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2 changed files with 32 additions and 66 deletions
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@ -3999,47 +3999,19 @@ enum punit_power_well {
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/* drain latency register values*/
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#define DRAIN_LATENCY_PRECISION_32 32
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#define DRAIN_LATENCY_PRECISION_64 64
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#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
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#define DDL_CURSORA_PRECISION_64 (1<<31)
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#define DDL_CURSORA_PRECISION_32 (0<<31)
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#define DDL_CURSORA_SHIFT 24
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#define DDL_SPRITEB_PRECISION_64 (1<<23)
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#define DDL_SPRITEB_PRECISION_32 (0<<23)
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#define DDL_SPRITEB_SHIFT 16
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#define DDL_SPRITEA_PRECISION_64 (1<<15)
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#define DDL_SPRITEA_PRECISION_32 (0<<15)
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#define DDL_SPRITEA_SHIFT 8
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#define DDL_PLANEA_PRECISION_64 (1<<7)
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#define DDL_PLANEA_PRECISION_32 (0<<7)
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#define DDL_PLANEA_SHIFT 0
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#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
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#define DDL_CURSORB_PRECISION_64 (1<<31)
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#define DDL_CURSORB_PRECISION_32 (0<<31)
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#define DDL_CURSORB_SHIFT 24
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#define DDL_SPRITED_PRECISION_64 (1<<23)
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#define DDL_SPRITED_PRECISION_32 (0<<23)
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#define DDL_SPRITED_SHIFT 16
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#define DDL_SPRITEC_PRECISION_64 (1<<15)
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#define DDL_SPRITEC_PRECISION_32 (0<<15)
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#define DDL_SPRITEC_SHIFT 8
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#define DDL_PLANEB_PRECISION_64 (1<<7)
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#define DDL_PLANEB_PRECISION_32 (0<<7)
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#define DDL_PLANEB_SHIFT 0
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#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058)
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#define DDL_CURSORC_PRECISION_64 (1<<31)
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#define DDL_CURSORC_PRECISION_32 (0<<31)
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#define DDL_CURSORC_SHIFT 24
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#define DDL_SPRITEF_PRECISION_64 (1<<23)
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#define DDL_SPRITEF_PRECISION_32 (0<<23)
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#define DDL_SPRITEF_SHIFT 16
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#define DDL_SPRITEE_PRECISION_64 (1<<15)
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#define DDL_SPRITEE_PRECISION_32 (0<<15)
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#define DDL_SPRITEE_SHIFT 8
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#define DDL_PLANEC_PRECISION_64 (1<<7)
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#define DDL_PLANEC_PRECISION_32 (0<<7)
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#define DDL_PLANEC_SHIFT 0
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#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
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#define DDL_CURSOR_PRECISION_64 (1<<31)
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#define DDL_CURSOR_PRECISION_32 (0<<31)
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#define DDL_CURSOR_SHIFT 24
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#define DDL_SPRITE1_PRECISION_64 (1<<23)
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#define DDL_SPRITE1_PRECISION_32 (0<<23)
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#define DDL_SPRITE1_SHIFT 16
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#define DDL_SPRITE0_PRECISION_64 (1<<15)
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#define DDL_SPRITE0_PRECISION_32 (0<<15)
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#define DDL_SPRITE0_SHIFT 8
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#define DDL_PLANE_PRECISION_64 (1<<7)
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#define DDL_PLANE_PRECISION_32 (0<<7)
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#define DDL_PLANE_SHIFT 0
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/* FIFO watermark sizes etc */
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#define G4X_FIFO_LINE_SIZE 64
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@ -1313,35 +1313,29 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
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static void vlv_update_drain_latency(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int planea_prec, planea_dl, planeb_prec, planeb_dl;
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int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
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int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
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either 16 or 32 */
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enum pipe pipe;
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/* For plane A, Cursor A */
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if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
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&cursor_prec_mult, &cursora_dl)) {
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cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
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DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
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planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
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DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
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for_each_pipe(pipe) {
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int plane_prec, plane_dl;
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int cursor_prec, cursor_dl;
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int plane_prec_mult, cursor_prec_mult;
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I915_WRITE(VLV_DDL1, cursora_prec |
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(cursora_dl << DDL_CURSORA_SHIFT) |
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planea_prec | planea_dl);
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}
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if (!vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,
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&cursor_prec_mult, &cursor_dl))
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continue;
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/* For plane B, Cursor B */
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if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
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&cursor_prec_mult, &cursorb_dl)) {
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cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
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DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
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planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
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DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
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/*
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* FIXME CHV spec still lists 16 and 32 as the precision
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* values. Need to figure out if spec is outdated or what.
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*/
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cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
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DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;
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plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
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DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32;
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I915_WRITE(VLV_DDL2, cursorb_prec |
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(cursorb_dl << DDL_CURSORB_SHIFT) |
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planeb_prec | planeb_dl);
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I915_WRITE(VLV_DDL(pipe), cursor_prec |
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(cursor_dl << DDL_CURSOR_SHIFT) |
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plane_prec | (plane_dl << DDL_PLANE_SHIFT));
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}
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}
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