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crypto: caam - optimize RNG sample size
TRNG "sample size" (the total number of entropy samples that will be taken during entropy generation) default / POR value is very conservatively set to 2500. Let's set it to 512, the same as the caam driver in U-boot (drivers/crypto/fsl_caam.c) does. This solves the issue of RNG performance dropping after a suspend/resume cycle on parts where caam loses power, since the initial U-boot setttings are lost and kernel does not restore them when resuming. Note: when changing the sample size, the self-test parameters need to be updated accordingly. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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2be0d806e2
commit
1abc89661a
2 changed files with 43 additions and 21 deletions
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@ -358,7 +358,7 @@ static void kick_trng(struct device *dev, int ent_delay)
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struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
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struct caam_ctrl __iomem *ctrl;
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struct rng4tst __iomem *r4tst;
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u32 val;
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u32 val, rtsdctl;
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ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
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r4tst = &ctrl->r4tst[0];
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@ -374,26 +374,38 @@ static void kick_trng(struct device *dev, int ent_delay)
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* Performance-wise, it does not make sense to
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* set the delay to a value that is lower
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* than the last one that worked (i.e. the state handles
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* were instantiated properly. Thus, instead of wasting
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* time trying to set the values controlling the sample
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* frequency, the function simply returns.
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* were instantiated properly).
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*/
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val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
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>> RTSDCTL_ENT_DLY_SHIFT;
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if (ent_delay <= val)
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goto start_rng;
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rtsdctl = rd_reg32(&r4tst->rtsdctl);
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val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT;
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if (ent_delay > val) {
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val = ent_delay;
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/* min. freq. count, equal to 1/4 of the entropy sample length */
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wr_reg32(&r4tst->rtfrqmin, val >> 2);
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/* max. freq. count, equal to 16 times the entropy sample length */
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wr_reg32(&r4tst->rtfrqmax, val << 4);
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}
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wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |
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RTSDCTL_SAMP_SIZE_VAL);
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/*
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* To avoid reprogramming the self-test parameters over and over again,
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* use RTSDCTL[SAMP_SIZE] as an indicator.
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*/
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if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) {
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wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);
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wr_reg32(&r4tst->rtpkrrng, 570);
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wr_reg32(&r4tst->rtpkrmax, 1600);
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wr_reg32(&r4tst->rtscml, (122 << 16) | 317);
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wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);
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wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);
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wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);
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wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);
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wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);
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wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);
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}
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val = rd_reg32(&r4tst->rtsdctl);
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val = (val & ~RTSDCTL_ENT_DLY_MASK) |
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(ent_delay << RTSDCTL_ENT_DLY_SHIFT);
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wr_reg32(&r4tst->rtsdctl, val);
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/* min. freq. count, equal to 1/4 of the entropy sample length */
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wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
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/* max. freq. count, equal to 16 times the entropy sample length */
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wr_reg32(&r4tst->rtfrqmax, ent_delay << 4);
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/* read the control register */
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val = rd_reg32(&r4tst->rtmctl);
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start_rng:
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/*
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* select raw sampling in both entropy shifter
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* and statistical checker; ; put RNG4 into run mode
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@ -3,7 +3,7 @@
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* CAAM hardware register-level view
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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* Copyright 2018, 2023 NXP
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*/
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#ifndef REGS_H
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@ -523,6 +523,8 @@ struct rng4tst {
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#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
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#define RTSDCTL_ENT_DLY_MIN 3200
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#define RTSDCTL_ENT_DLY_MAX 12800
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#define RTSDCTL_SAMP_SIZE_MASK 0xffff
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#define RTSDCTL_SAMP_SIZE_VAL 512
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u32 rtsdctl; /* seed control register */
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union {
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u32 rtsblim; /* PRGM=1: sparse bit limit register */
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@ -534,7 +536,15 @@ struct rng4tst {
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u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
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u32 rtfrqcnt; /* PRGM=0: freq. count register */
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};
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u32 rsvd1[40];
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union {
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u32 rtscmc; /* statistical check run monobit count */
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u32 rtscml; /* statistical check run monobit limit */
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};
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union {
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u32 rtscrc[6]; /* statistical check run length count */
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u32 rtscrl[6]; /* statistical check run length limit */
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};
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u32 rsvd1[33];
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#define RDSTA_SKVT 0x80000000
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#define RDSTA_SKVN 0x40000000
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#define RDSTA_PR0 BIT(4)
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