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drm/i915/dsb: function to trigger workload execution of DSB.
Batch buffer will be created through dsb-reg-write function which can have single/multiple request based on usecase and once the buffer is ready commit function will trigger the execution of the batch buffer. All the registers will be updated simultaneously. v1: Initial version. v2: Optimized code few places. (Chris) v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank) v4: reset ins_start_offset after commit. (Jani) Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190920115930.27829-8-animesh.manna@intel.com
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3 changed files with 46 additions and 0 deletions
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@ -224,3 +224,46 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
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(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
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i915_mmio_reg_offset(reg);
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}
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void intel_dsb_commit(struct intel_dsb *dsb)
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{
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struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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enum pipe pipe = crtc->pipe;
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u32 tail;
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if (!dsb->free_pos)
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return;
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if (!intel_dsb_enable_engine(dsb))
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goto reset;
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if (is_dsb_busy(dsb)) {
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DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
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goto reset;
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}
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I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
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tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
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if (tail > dsb->free_pos * 4)
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memset(&dsb->cmd_buf[dsb->free_pos], 0,
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(tail - dsb->free_pos * 4));
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if (is_dsb_busy(dsb)) {
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DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
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goto reset;
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}
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DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
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i915_ggtt_offset(dsb->vma), tail);
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I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
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if (wait_for(!is_dsb_busy(dsb), 1)) {
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DRM_ERROR("Timed out waiting for DSB workload completion.\n");
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goto reset;
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}
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reset:
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dsb->free_pos = 0;
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dsb->ins_start_offset = 0;
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intel_dsb_disable_engine(dsb);
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}
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@ -47,5 +47,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
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void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
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void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
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u32 val);
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void intel_dsb_commit(struct intel_dsb *dsb);
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#endif
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@ -11702,6 +11702,8 @@ enum skl_power_gate {
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#define _DSBSL_INSTANCE_BASE 0x70B00
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#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
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(pipe) * 0x1000 + (id) * 100)
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#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
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#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
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#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
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#define DSB_ENABLE (1 << 31)
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#define DSB_STATUS (1 << 0)
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