Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue
Tony Nguyen says: ==================== Intel Wired LAN Driver Updates 2024-03-27 (e1000e) This series contains updates to e1000e driver only. Vitaly adds retry mechanism for some PHY operations to workaround MDI error and moves SMBus configuration to avoid possible PHY loss. * '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue: e1000e: move force SMBUS from enable ulp function to avoid PHY loss issue e1000e: Workaround for sporadic MDI error on Meteor Lake systems ==================== Link: https://lore.kernel.org/r/20240327185517.2587564-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
commit
1ae289b0b0
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@ -628,6 +628,7 @@ struct e1000_phy_info {
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u32 id;
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u32 id;
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u32 reset_delay_us; /* in usec */
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u32 reset_delay_us; /* in usec */
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u32 revision;
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u32 revision;
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u32 retry_count;
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enum e1000_media_type media_type;
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enum e1000_media_type media_type;
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@ -644,6 +645,7 @@ struct e1000_phy_info {
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bool polarity_correction;
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bool polarity_correction;
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bool speed_downgraded;
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bool speed_downgraded;
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bool autoneg_wait_to_complete;
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bool autoneg_wait_to_complete;
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bool retry_enabled;
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};
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};
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struct e1000_nvm_info {
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struct e1000_nvm_info {
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@ -222,11 +222,18 @@ out:
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if (hw->mac.type >= e1000_pch_lpt) {
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if (hw->mac.type >= e1000_pch_lpt) {
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/* Only unforce SMBus if ME is not active */
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/* Only unforce SMBus if ME is not active */
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if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
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if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
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/* Switching PHY interface always returns MDI error
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* so disable retry mechanism to avoid wasting time
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*/
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e1000e_disable_phy_retry(hw);
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/* Unforce SMBus mode in PHY */
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/* Unforce SMBus mode in PHY */
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e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
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e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
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phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
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phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
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e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
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e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
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e1000e_enable_phy_retry(hw);
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/* Unforce SMBus mode in MAC */
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/* Unforce SMBus mode in MAC */
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mac_reg = er32(CTRL_EXT);
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mac_reg = er32(CTRL_EXT);
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mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
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mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
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@ -310,6 +317,11 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
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goto out;
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goto out;
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}
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}
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/* There is no guarantee that the PHY is accessible at this time
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* so disable retry mechanism to avoid wasting time
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*/
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e1000e_disable_phy_retry(hw);
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/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
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/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
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* inaccessible and resetting the PHY is not blocked, toggle the
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* inaccessible and resetting the PHY is not blocked, toggle the
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* LANPHYPC Value bit to force the interconnect to PCIe mode.
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* LANPHYPC Value bit to force the interconnect to PCIe mode.
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@ -380,6 +392,8 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
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break;
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break;
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}
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}
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e1000e_enable_phy_retry(hw);
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hw->phy.ops.release(hw);
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hw->phy.ops.release(hw);
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if (!ret_val) {
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if (!ret_val) {
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@ -449,6 +463,11 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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phy->id = e1000_phy_unknown;
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phy->id = e1000_phy_unknown;
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if (hw->mac.type == e1000_pch_mtp) {
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phy->retry_count = 2;
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e1000e_enable_phy_retry(hw);
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}
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ret_val = e1000_init_phy_workarounds_pchlan(hw);
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ret_val = e1000_init_phy_workarounds_pchlan(hw);
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if (ret_val)
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if (ret_val)
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return ret_val;
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return ret_val;
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@ -1146,18 +1165,6 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
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if (ret_val)
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if (ret_val)
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goto out;
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goto out;
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/* Force SMBus mode in PHY */
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ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
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if (ret_val)
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goto release;
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phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
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e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
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/* Force SMBus mode in MAC */
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mac_reg = er32(CTRL_EXT);
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mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
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ew32(CTRL_EXT, mac_reg);
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/* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
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/* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
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* LPLU and disable Gig speed when entering ULP
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* LPLU and disable Gig speed when entering ULP
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*/
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*/
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@ -1313,6 +1320,11 @@ static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
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/* Toggle LANPHYPC Value bit */
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/* Toggle LANPHYPC Value bit */
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e1000_toggle_lanphypc_pch_lpt(hw);
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e1000_toggle_lanphypc_pch_lpt(hw);
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/* Switching PHY interface always returns MDI error
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* so disable retry mechanism to avoid wasting time
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*/
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e1000e_disable_phy_retry(hw);
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/* Unforce SMBus mode in PHY */
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/* Unforce SMBus mode in PHY */
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ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
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ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
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if (ret_val) {
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if (ret_val) {
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@ -1333,6 +1345,8 @@ static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
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phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
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phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
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e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
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e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
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e1000e_enable_phy_retry(hw);
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/* Unforce SMBus mode in MAC */
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/* Unforce SMBus mode in MAC */
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mac_reg = er32(CTRL_EXT);
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mac_reg = er32(CTRL_EXT);
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mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
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mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
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@ -6623,6 +6623,7 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
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struct e1000_hw *hw = &adapter->hw;
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struct e1000_hw *hw = &adapter->hw;
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u32 ctrl, ctrl_ext, rctl, status, wufc;
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u32 ctrl, ctrl_ext, rctl, status, wufc;
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int retval = 0;
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int retval = 0;
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u16 smb_ctrl;
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/* Runtime suspend should only enable wakeup for link changes */
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/* Runtime suspend should only enable wakeup for link changes */
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if (runtime)
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if (runtime)
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@ -6696,6 +6697,23 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
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if (retval)
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if (retval)
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return retval;
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return retval;
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}
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}
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/* Force SMBUS to allow WOL */
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/* Switching PHY interface always returns MDI error
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* so disable retry mechanism to avoid wasting time
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*/
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e1000e_disable_phy_retry(hw);
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e1e_rphy(hw, CV_SMB_CTRL, &smb_ctrl);
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smb_ctrl |= CV_SMB_CTRL_FORCE_SMBUS;
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e1e_wphy(hw, CV_SMB_CTRL, smb_ctrl);
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e1000e_enable_phy_retry(hw);
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/* Force SMBus mode in MAC */
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ctrl_ext = er32(CTRL_EXT);
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ctrl_ext |= E1000_CTRL_EXT_FORCE_SMBUS;
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ew32(CTRL_EXT, ctrl_ext);
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}
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}
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/* Ensure that the appropriate bits are set in LPI_CTRL
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/* Ensure that the appropriate bits are set in LPI_CTRL
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@ -107,6 +107,16 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
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return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
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return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
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}
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}
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void e1000e_disable_phy_retry(struct e1000_hw *hw)
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{
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hw->phy.retry_enabled = false;
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}
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void e1000e_enable_phy_retry(struct e1000_hw *hw)
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{
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hw->phy.retry_enabled = true;
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}
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/**
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/**
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* e1000e_read_phy_reg_mdic - Read MDI control register
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* e1000e_read_phy_reg_mdic - Read MDI control register
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* @hw: pointer to the HW structure
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* @hw: pointer to the HW structure
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@ -118,55 +128,73 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
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**/
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**/
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s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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{
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u32 i, mdic = 0, retry_counter, retry_max;
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struct e1000_phy_info *phy = &hw->phy;
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, mdic = 0;
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bool success;
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if (offset > MAX_PHY_REG_ADDRESS) {
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if (offset > MAX_PHY_REG_ADDRESS) {
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e_dbg("PHY Address %d is out of range\n", offset);
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e_dbg("PHY Address %d is out of range\n", offset);
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return -E1000_ERR_PARAM;
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return -E1000_ERR_PARAM;
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}
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}
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retry_max = phy->retry_enabled ? phy->retry_count : 0;
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/* Set up Op-code, Phy Address, and register offset in the MDI
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/* Set up Op-code, Phy Address, and register offset in the MDI
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* Control register. The MAC will take care of interfacing with the
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* Control register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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* PHY to retrieve the desired data.
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*/
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*/
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mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
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(phy->addr << E1000_MDIC_PHY_SHIFT) |
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success = true;
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(E1000_MDIC_OP_READ));
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ew32(MDIC, mdic);
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mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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(phy->addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_READ));
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/* Poll the ready bit to see if the MDI read completed
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ew32(MDIC, mdic);
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* Increasing the time out as testing showed failures with
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* the lower time out
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*/
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for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
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udelay(50);
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mdic = er32(MDIC);
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if (mdic & E1000_MDIC_READY)
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break;
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}
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if (!(mdic & E1000_MDIC_READY)) {
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e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
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|
||||||
return -E1000_ERR_PHY;
|
|
||||||
}
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|
||||||
if (mdic & E1000_MDIC_ERROR) {
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|
||||||
e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
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|
||||||
return -E1000_ERR_PHY;
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|
||||||
}
|
|
||||||
if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
|
|
||||||
e_dbg("MDI Read offset error - requested %d, returned %d\n",
|
|
||||||
offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
|
|
||||||
return -E1000_ERR_PHY;
|
|
||||||
}
|
|
||||||
*data = (u16)mdic;
|
|
||||||
|
|
||||||
/* Allow some time after each MDIC transaction to avoid
|
/* Poll the ready bit to see if the MDI read completed
|
||||||
* reading duplicate data in the next MDIC transaction.
|
* Increasing the time out as testing showed failures with
|
||||||
*/
|
* the lower time out
|
||||||
if (hw->mac.type == e1000_pch2lan)
|
*/
|
||||||
udelay(100);
|
for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
|
||||||
return 0;
|
usleep_range(50, 60);
|
||||||
|
mdic = er32(MDIC);
|
||||||
|
if (mdic & E1000_MDIC_READY)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (!(mdic & E1000_MDIC_READY)) {
|
||||||
|
e_dbg("MDI Read PHY Reg Address %d did not complete\n",
|
||||||
|
offset);
|
||||||
|
success = false;
|
||||||
|
}
|
||||||
|
if (mdic & E1000_MDIC_ERROR) {
|
||||||
|
e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
|
||||||
|
success = false;
|
||||||
|
}
|
||||||
|
if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
|
||||||
|
e_dbg("MDI Read offset error - requested %d, returned %d\n",
|
||||||
|
offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
|
||||||
|
success = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allow some time after each MDIC transaction to avoid
|
||||||
|
* reading duplicate data in the next MDIC transaction.
|
||||||
|
*/
|
||||||
|
if (hw->mac.type == e1000_pch2lan)
|
||||||
|
usleep_range(100, 150);
|
||||||
|
|
||||||
|
if (success) {
|
||||||
|
*data = (u16)mdic;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (retry_counter != retry_max) {
|
||||||
|
e_dbg("Perform retry on PHY transaction...\n");
|
||||||
|
mdelay(10);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return -E1000_ERR_PHY;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -179,56 +207,72 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
|
||||||
**/
|
**/
|
||||||
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
|
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
|
||||||
{
|
{
|
||||||
|
u32 i, mdic = 0, retry_counter, retry_max;
|
||||||
struct e1000_phy_info *phy = &hw->phy;
|
struct e1000_phy_info *phy = &hw->phy;
|
||||||
u32 i, mdic = 0;
|
bool success;
|
||||||
|
|
||||||
if (offset > MAX_PHY_REG_ADDRESS) {
|
if (offset > MAX_PHY_REG_ADDRESS) {
|
||||||
e_dbg("PHY Address %d is out of range\n", offset);
|
e_dbg("PHY Address %d is out of range\n", offset);
|
||||||
return -E1000_ERR_PARAM;
|
return -E1000_ERR_PARAM;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
retry_max = phy->retry_enabled ? phy->retry_count : 0;
|
||||||
|
|
||||||
/* Set up Op-code, Phy Address, and register offset in the MDI
|
/* Set up Op-code, Phy Address, and register offset in the MDI
|
||||||
* Control register. The MAC will take care of interfacing with the
|
* Control register. The MAC will take care of interfacing with the
|
||||||
* PHY to retrieve the desired data.
|
* PHY to retrieve the desired data.
|
||||||
*/
|
*/
|
||||||
mdic = (((u32)data) |
|
for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
|
||||||
(offset << E1000_MDIC_REG_SHIFT) |
|
success = true;
|
||||||
(phy->addr << E1000_MDIC_PHY_SHIFT) |
|
|
||||||
(E1000_MDIC_OP_WRITE));
|
|
||||||
|
|
||||||
ew32(MDIC, mdic);
|
mdic = (((u32)data) |
|
||||||
|
(offset << E1000_MDIC_REG_SHIFT) |
|
||||||
|
(phy->addr << E1000_MDIC_PHY_SHIFT) |
|
||||||
|
(E1000_MDIC_OP_WRITE));
|
||||||
|
|
||||||
/* Poll the ready bit to see if the MDI read completed
|
ew32(MDIC, mdic);
|
||||||
* Increasing the time out as testing showed failures with
|
|
||||||
* the lower time out
|
/* Poll the ready bit to see if the MDI read completed
|
||||||
*/
|
* Increasing the time out as testing showed failures with
|
||||||
for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
|
* the lower time out
|
||||||
udelay(50);
|
*/
|
||||||
mdic = er32(MDIC);
|
for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
|
||||||
if (mdic & E1000_MDIC_READY)
|
usleep_range(50, 60);
|
||||||
break;
|
mdic = er32(MDIC);
|
||||||
}
|
if (mdic & E1000_MDIC_READY)
|
||||||
if (!(mdic & E1000_MDIC_READY)) {
|
break;
|
||||||
e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
|
}
|
||||||
return -E1000_ERR_PHY;
|
if (!(mdic & E1000_MDIC_READY)) {
|
||||||
}
|
e_dbg("MDI Write PHY Reg Address %d did not complete\n",
|
||||||
if (mdic & E1000_MDIC_ERROR) {
|
offset);
|
||||||
e_dbg("MDI Write PHY Red Address %d Error\n", offset);
|
success = false;
|
||||||
return -E1000_ERR_PHY;
|
}
|
||||||
}
|
if (mdic & E1000_MDIC_ERROR) {
|
||||||
if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
|
e_dbg("MDI Write PHY Reg Address %d Error\n", offset);
|
||||||
e_dbg("MDI Write offset error - requested %d, returned %d\n",
|
success = false;
|
||||||
offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
|
}
|
||||||
return -E1000_ERR_PHY;
|
if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
|
||||||
|
e_dbg("MDI Write offset error - requested %d, returned %d\n",
|
||||||
|
offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
|
||||||
|
success = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allow some time after each MDIC transaction to avoid
|
||||||
|
* reading duplicate data in the next MDIC transaction.
|
||||||
|
*/
|
||||||
|
if (hw->mac.type == e1000_pch2lan)
|
||||||
|
usleep_range(100, 150);
|
||||||
|
|
||||||
|
if (success)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (retry_counter != retry_max) {
|
||||||
|
e_dbg("Perform retry on PHY transaction...\n");
|
||||||
|
mdelay(10);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Allow some time after each MDIC transaction to avoid
|
return -E1000_ERR_PHY;
|
||||||
* reading duplicate data in the next MDIC transaction.
|
|
||||||
*/
|
|
||||||
if (hw->mac.type == e1000_pch2lan)
|
|
||||||
udelay(100);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -51,6 +51,8 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||||
s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
|
s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
|
||||||
void e1000_power_up_phy_copper(struct e1000_hw *hw);
|
void e1000_power_up_phy_copper(struct e1000_hw *hw);
|
||||||
void e1000_power_down_phy_copper(struct e1000_hw *hw);
|
void e1000_power_down_phy_copper(struct e1000_hw *hw);
|
||||||
|
void e1000e_disable_phy_retry(struct e1000_hw *hw);
|
||||||
|
void e1000e_enable_phy_retry(struct e1000_hw *hw);
|
||||||
s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
|
s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||||
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
|
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
|
||||||
s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
|
s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||||
|
|
Loading…
Reference in New Issue