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powerpc/47x: Use the new ppc-opcode infrastructure
Don't use 47x only #defines for TLBIVAX or ICBT, supply and use helpers in ppc-opcode.h This fixes a compile breakage. Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2 changed files with 8 additions and 11 deletions
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@ -86,6 +86,7 @@
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#define PPC_INST_DCBA_MASK 0xfc0007fe
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#define PPC_INST_DCBA_MASK 0xfc0007fe
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#define PPC_INST_DCBAL 0x7c2005ec
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#define PPC_INST_DCBAL 0x7c2005ec
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#define PPC_INST_DCBZL 0x7c2007ec
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#define PPC_INST_DCBZL 0x7c2007ec
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#define PPC_INST_ICBT 0x7c00002c
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#define PPC_INST_ISEL 0x7c00001e
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#define PPC_INST_ISEL 0x7c00001e
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#define PPC_INST_ISEL_MASK 0xfc00003e
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#define PPC_INST_ISEL_MASK 0xfc00003e
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#define PPC_INST_LDARX 0x7c0000a8
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#define PPC_INST_LDARX 0x7c0000a8
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@ -198,6 +199,7 @@
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#define __PPC_MB(s) (((s) & 0x1f) << 6)
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#define __PPC_MB(s) (((s) & 0x1f) << 6)
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#define __PPC_ME(s) (((s) & 0x1f) << 1)
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#define __PPC_ME(s) (((s) & 0x1f) << 1)
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#define __PPC_BI(s) (((s) & 0x1f) << 16)
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#define __PPC_BI(s) (((s) & 0x1f) << 16)
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#define __PPC_CT(t) (((t) & 0x0f) << 21)
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/*
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/*
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* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
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* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
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@ -260,6 +262,8 @@
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__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
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__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
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#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
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#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
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__PPC_RT(t) | __PPC_RB(b))
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__PPC_RT(t) | __PPC_RB(b))
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#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
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__PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
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/* PASemi instructions */
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/* PASemi instructions */
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#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
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#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
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__PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
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__PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
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@ -190,12 +190,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
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#ifdef CONFIG_PPC_47x
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#ifdef CONFIG_PPC_47x
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/*
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* 47x variant of icbt
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*/
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# define ICBT(CT,RA,RB) \
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.long 0x7c00002c | ((CT) << 21) | ((RA) << 16) | ((RB) << 11)
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/*
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/*
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* _tlbivax_bcast is only on 47x. We don't bother doing a runtime
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* _tlbivax_bcast is only on 47x. We don't bother doing a runtime
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* check though, it will blow up soon enough if we mistakenly try
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* check though, it will blow up soon enough if we mistakenly try
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@ -208,8 +202,7 @@ _GLOBAL(_tlbivax_bcast)
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wrteei 0
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wrteei 0
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mtspr SPRN_MMUCR,r5
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mtspr SPRN_MMUCR,r5
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isync
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isync
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/* tlbivax 0,r3 - use .long to avoid binutils deps */
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PPC_TLBIVAX(0, R3)
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.long 0x7c000624 | (r3 << 11)
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isync
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isync
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eieio
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eieio
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tlbsync
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tlbsync
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@ -227,11 +220,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_476_DD2)
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bl 2f
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bl 2f
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2: mflr r6
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2: mflr r6
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li r7,32
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li r7,32
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ICBT(0,r6,r7) /* touch next cache line */
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PPC_ICBT(0,R6,R7) /* touch next cache line */
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add r6,r6,r7
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add r6,r6,r7
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ICBT(0,r6,r7) /* touch next cache line */
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PPC_ICBT(0,R6,R7) /* touch next cache line */
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add r6,r6,r7
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add r6,r6,r7
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ICBT(0,r6,r7) /* touch next cache line */
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PPC_ICBT(0,R6,R7) /* touch next cache line */
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sync
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sync
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nop
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nop
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nop
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nop
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