mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-04 09:59:32 +00:00
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: Blackfin arch: make sure cycles is marked as volatile so gcc doesnt reorder on us Blackfin arch: disable CONFIG_HW_RANDOM and CONFIG_DAB in defconfig files Blackfin arch: update cache flush prototypes with argument names to make them less mysterious Blackfin arch: move bfin_addr_dcachable() and friends into the cacheflush header where it belongs Blackfin arch: use the new bfin_addr_dcachable() function Blackfin arch: fix bug - build kernel failed at head.S when reprogram clock on all platforms Blackfin arch: unify/cleanup cache code Blackfin arch: update AD7879 platform resources in board file Blackfin arch: Zero out bss region in L1/L2 memory. Blackfin arch: add read/write IO accessor functions to Blackfin Blackfin arch: fix bug - some serial header files set RTS to an input when they should all be outputs
This commit is contained in:
commit
1b821bfb03
29 changed files with 210 additions and 174 deletions
|
@ -748,7 +748,7 @@ CONFIG_BFIN_OTP=y
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|||
#
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||||
# CONFIG_CAN4LINUX is not set
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||||
# CONFIG_IPMI_HANDLER is not set
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||||
CONFIG_HW_RANDOM=y
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||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_R3964 is not set
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||||
# CONFIG_RAW_DRIVER is not set
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||||
# CONFIG_TCG_TPM is not set
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||||
|
|
|
@ -772,7 +772,7 @@ CONFIG_UNIX98_PTYS=y
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|||
#
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||||
# CONFIG_CAN4LINUX is not set
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# CONFIG_IPMI_HANDLER is not set
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||||
CONFIG_HW_RANDOM=y
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||||
# CONFIG_HW_RANDOM is not set
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||||
# CONFIG_GEN_RTC is not set
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||||
# CONFIG_R3964 is not set
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||||
# CONFIG_RAW_DRIVER is not set
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||||
|
|
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@ -674,7 +674,7 @@ CONFIG_UNIX98_PTYS=y
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|||
#
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||||
# CONFIG_CAN4LINUX is not set
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||||
# CONFIG_IPMI_HANDLER is not set
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||||
CONFIG_HW_RANDOM=y
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||||
# CONFIG_HW_RANDOM is not set
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||||
# CONFIG_GEN_RTC is not set
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||||
# CONFIG_R3964 is not set
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||||
# CONFIG_RAW_DRIVER is not set
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||||
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@ -740,7 +740,7 @@ CONFIG_SSB_POSSIBLE=y
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#
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# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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||||
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||||
#
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||||
# Graphics support
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|
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@ -681,7 +681,7 @@ CONFIG_UNIX98_PTYS=y
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|||
#
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||||
# CONFIG_CAN4LINUX is not set
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# CONFIG_IPMI_HANDLER is not set
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CONFIG_HW_RANDOM=y
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||||
# CONFIG_HW_RANDOM is not set
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||||
# CONFIG_GEN_RTC is not set
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||||
# CONFIG_R3964 is not set
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# CONFIG_RAW_DRIVER is not set
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|
|
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@ -731,7 +731,7 @@ CONFIG_CAN4LINUX=y
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|||
# CONFIG_CAN_UNCTWINCAN is not set
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CONFIG_CAN_BLACKFIN=m
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# CONFIG_IPMI_HANDLER is not set
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CONFIG_HW_RANDOM=y
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||||
# CONFIG_HW_RANDOM is not set
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||||
# CONFIG_GEN_RTC is not set
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||||
# CONFIG_R3964 is not set
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# CONFIG_RAW_DRIVER is not set
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@ -871,7 +871,7 @@ CONFIG_SSB_POSSIBLE=y
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#
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# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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||||
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||||
#
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# Graphics support
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|
|
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@ -855,7 +855,7 @@ CONFIG_UNIX98_PTYS=y
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|||
#
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||||
# CONFIG_CAN4LINUX is not set
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# CONFIG_IPMI_HANDLER is not set
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CONFIG_HW_RANDOM=y
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# CONFIG_HW_RANDOM is not set
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# CONFIG_GEN_RTC is not set
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# CONFIG_R3964 is not set
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# CONFIG_RAW_DRIVER is not set
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@ -1001,7 +1001,7 @@ CONFIG_SSB_POSSIBLE=y
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#
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# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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# CONFIG_USB_DABUSB is not set
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#
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|
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@ -719,7 +719,7 @@ CONFIG_UNIX98_PTYS=y
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|||
#
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# CONFIG_CAN4LINUX is not set
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# CONFIG_IPMI_HANDLER is not set
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CONFIG_HW_RANDOM=y
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# CONFIG_HW_RANDOM is not set
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# CONFIG_GEN_RTC is not set
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# CONFIG_R3964 is not set
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# CONFIG_RAW_DRIVER is not set
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@ -785,7 +785,7 @@ CONFIG_SSB_POSSIBLE=y
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|||
#
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# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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|
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#
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# Graphics support
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|
|
|
@ -679,7 +679,7 @@ CONFIG_UNIX98_PTYS=y
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#
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# CONFIG_CAN4LINUX is not set
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# CONFIG_IPMI_HANDLER is not set
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||||
CONFIG_HW_RANDOM=y
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||||
# CONFIG_HW_RANDOM is not set
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||||
# CONFIG_GEN_RTC is not set
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# CONFIG_R3964 is not set
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# CONFIG_RAW_DRIVER is not set
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|
|
|
@ -672,7 +672,7 @@ CONFIG_HWMON=y
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#
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# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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#
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# Graphics support
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|
|
|
@ -703,7 +703,7 @@ CONFIG_HWMON=y
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#
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# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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||||
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||||
#
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# Graphics support
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|
|
|
@ -683,7 +683,7 @@ CONFIG_HWMON=y
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#
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# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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||||
|
||||
#
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# Graphics support
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|
|
|
@ -762,7 +762,7 @@ CONFIG_UNIX98_PTYS=y
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#
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||||
# CONFIG_CAN4LINUX is not set
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||||
# CONFIG_IPMI_HANDLER is not set
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CONFIG_HW_RANDOM=y
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||||
# CONFIG_HW_RANDOM is not set
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# CONFIG_GEN_RTC is not set
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# CONFIG_R3964 is not set
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# CONFIG_RAW_DRIVER is not set
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|
@ -909,7 +909,7 @@ CONFIG_SSB_POSSIBLE=y
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|||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
# CONFIG_DVB_CORE is not set
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||||
CONFIG_DAB=y
|
||||
# CONFIG_DAB is not set
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||||
# CONFIG_USB_DABUSB is not set
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||||
|
||||
#
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||||
|
|
|
@ -684,7 +684,7 @@ CONFIG_SSB_POSSIBLE=y
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|||
#
|
||||
# CONFIG_VIDEO_DEV is not set
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# CONFIG_DVB_CORE is not set
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CONFIG_DAB=y
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# CONFIG_DAB is not set
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#
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# Graphics support
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|
|
@ -30,11 +30,11 @@
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#ifndef _BLACKFIN_CACHEFLUSH_H
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#define _BLACKFIN_CACHEFLUSH_H
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extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
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extern void blackfin_icache_flush_range(unsigned int, unsigned int);
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extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
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extern void blackfin_dcache_invalidate_range(unsigned int, unsigned int);
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extern void blackfin_dflush_page(void *);
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extern void blackfin_icache_dcache_flush_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dflush_page(void *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -85,4 +85,21 @@ do { memcpy(dst, src, len); \
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# define flush_dcache_page(page) do { } while (0)
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#endif
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extern unsigned long reserved_mem_dcache_on;
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extern unsigned long reserved_mem_icache_on;
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static inline int bfin_addr_dcachable(unsigned long addr)
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{
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#ifdef CONFIG_BFIN_DCACHE
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if (addr < (_ramend - DMA_UNCACHED_REGION))
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return 1;
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#endif
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if (reserved_mem_dcache_on &&
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addr >= _ramend && addr < physical_mem_end)
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return 1;
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return 0;
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}
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#endif /* _BLACKFIN_ICACHEFLUSH_H */
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@ -87,23 +87,6 @@ extern u_long dpdt_swapcount_table[];
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#endif /* CONFIG_MPU */
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extern unsigned long reserved_mem_dcache_on;
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extern unsigned long reserved_mem_icache_on;
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extern void generate_cplb_tables(void);
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static inline int bfin_addr_dcachable(unsigned long addr)
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{
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#ifdef CONFIG_BFIN_DCACHE
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if (addr < (_ramend - DMA_UNCACHED_REGION))
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return 1;
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#endif
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if (reserved_mem_dcache_on &&
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addr >= _ramend && addr < physical_mem_end)
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return 1;
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return 0;
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}
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#endif
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@ -134,6 +134,36 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
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extern void dma_insw(unsigned long port, void *addr, unsigned short count);
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extern void dma_insl(unsigned long port, void *addr, unsigned short count);
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static inline void readsl(const void __iomem *addr, void *buf, int len)
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{
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insl((unsigned long)addr, buf, len);
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}
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static inline void readsw(const void __iomem *addr, void *buf, int len)
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{
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insw((unsigned long)addr, buf, len);
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}
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static inline void readsb(const void __iomem *addr, void *buf, int len)
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{
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insb((unsigned long)addr, buf, len);
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}
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static inline void writesl(const void __iomem *addr, const void *buf, int len)
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{
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outsl((unsigned long)addr, buf, len);
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}
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static inline void writesw(const void __iomem *addr, const void *buf, int len)
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{
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outsw((unsigned long)addr, buf, len);
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}
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static inline void writesb(const void __iomem *addr, const void *buf, int len)
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{
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outsb((unsigned long)addr, buf, len);
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}
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/*
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* Map some physical address range into the kernel address space.
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*/
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|
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@ -16,7 +16,7 @@ typedef unsigned long long cycles_t;
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static inline cycles_t get_cycles(void)
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{
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unsigned long tmp, tmp2;
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__asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
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__asm__ __volatile__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
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return tmp | ((cycles_t)tmp2 << 32);
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}
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|
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@ -21,6 +21,7 @@
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#include <linux/mm.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
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#include <asm/cplbinit.h>
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#include <asm/mmu_context.h>
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|
@ -144,9 +145,7 @@ static noinline int dcplb_miss(void)
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d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
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#ifdef CONFIG_BFIN_DCACHE
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if (addr < _ramend - DMA_UNCACHED_REGION ||
|
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(reserved_mem_dcache_on && addr >= _ramend &&
|
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addr < physical_mem_end)) {
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if (bfin_addr_dcachable(addr)) {
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d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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#ifdef CONFIG_BFIN_WT
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d_data |= CPLB_L1_AOW | CPLB_WT;
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|
|
|
@ -23,6 +23,7 @@
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|||
#include <linux/module.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/cacheflush.h>
|
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#include <asm/cplb.h>
|
||||
#include <asm/cplbinit.h>
|
||||
|
||||
|
|
|
@ -88,7 +88,7 @@ ENTRY(_start_dma_code)
|
|||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
#ifdef ANOMALY_05000265
|
||||
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
#endif
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
|
|
|
@ -79,7 +79,7 @@ ENTRY(_start_dma_code)
|
|||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
#ifdef ANOMALY_05000265
|
||||
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
#endif
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
|
|
|
@ -158,7 +158,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
|
|||
}
|
||||
if (uart->rts_pin >= 0) {
|
||||
gpio_request(uart->rts_pin, DRIVER_NAME);
|
||||
gpio_direction_input(uart->rts_pin, 0);
|
||||
gpio_direction_output(uart->rts_pin, 0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -577,11 +577,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
|
|||
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
|
||||
#include <linux/spi/ad7879.h>
|
||||
static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
|
||||
static const struct ad7879_platform_data bfin_ad7879_ts_info = {
|
||||
.model = 7879, /* Model = AD7879 */
|
||||
.x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
|
||||
|
@ -597,6 +592,13 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
|
||||
static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
|
||||
.enable_dma = 0,
|
||||
.bits_per_word = 16,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
|
||||
static struct bfin5xx_spi_chip spidev_chip_info = {
|
||||
.enable_dma = 0,
|
||||
|
@ -750,7 +752,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
|||
.controller_data = &spi_ad7877_chip_info,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
|
||||
{
|
||||
.modalias = "ad7879",
|
||||
.platform_data = &bfin_ad7879_ts_info,
|
||||
|
@ -935,7 +937,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
|
|||
#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE)
|
||||
{
|
||||
I2C_BOARD_INFO("ad7142_joystick", 0x2C),
|
||||
.irq = 55,
|
||||
.irq = IRQ_PF5,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
|
||||
|
@ -946,7 +948,14 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
|
|||
#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
|
||||
{
|
||||
I2C_BOARD_INFO("pcf8574_keypad", 0x27),
|
||||
.irq = 72,
|
||||
.irq = IRQ_PG6,
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
|
||||
{
|
||||
I2C_BOARD_INFO("ad7879", 0x2F),
|
||||
.irq = IRQ_PG5,
|
||||
.platform_data = (void *)&bfin_ad7879_ts_info,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
|
|
@ -88,7 +88,7 @@ ENTRY(_start_dma_code)
|
|||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
#ifdef ANOMALY_05000265
|
||||
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
#endif
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
|
|
|
@ -95,7 +95,7 @@ ENTRY(_start_dma_code)
|
|||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
#ifdef ANOMALY_05000265
|
||||
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
#endif
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
|
|
|
@ -78,7 +78,7 @@ ENTRY(_start_dma_code)
|
|||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
#ifdef ANOMALY_05000265
|
||||
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
|
||||
#endif
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
|
|
|
@ -158,7 +158,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
|
|||
}
|
||||
if (uart->rts_pin >= 0) {
|
||||
gpio_request(uart->rts_pin, DRIVER_NAME);
|
||||
gpio_direction_input(uart->rts_pin, 0);
|
||||
gpio_direction_output(uart->rts_pin, 0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -1,148 +1,91 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-common/cache.S
|
||||
* Based on:
|
||||
* Author: LG Soft India
|
||||
* Blackfin cache control code
|
||||
*
|
||||
* Created:
|
||||
* Description: cache control support
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2006 Analog Devices Inc.
|
||||
* Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/cplb.h>
|
||||
#include <asm/entry.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
.text
|
||||
|
||||
/*
|
||||
* blackfin_cache_flush_range(start, end)
|
||||
* Invalidate all cache lines assocoiated with this
|
||||
* area of memory.
|
||||
/* Since all L1 caches work the same way, we use the same method for flushing
|
||||
* them. Only the actual flush instruction differs. We write this in asm as
|
||||
* GCC can be hard to coax into writing nice hardware loops.
|
||||
*
|
||||
* start: Start address
|
||||
* end: End address
|
||||
* Also, we assume the following register setup:
|
||||
* R0 = start address
|
||||
* R1 = end address
|
||||
*/
|
||||
ENTRY(_blackfin_icache_flush_range)
|
||||
.macro do_flush flushins:req optflushins optnopins label
|
||||
|
||||
/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
|
||||
R1 += -1;
|
||||
R2 = -L1_CACHE_BYTES;
|
||||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC(R3);
|
||||
IFLUSH [P0];
|
||||
R1 = R1 & R2;
|
||||
R1 += L1_CACHE_BYTES;
|
||||
|
||||
/* count = (end - start) >> L1_CACHE_SHIFT */
|
||||
R2 = R1 - R0;
|
||||
R2 >>= L1_CACHE_SHIFT;
|
||||
P1 = R2;
|
||||
|
||||
.ifnb \label
|
||||
\label :
|
||||
.endif
|
||||
P0 = R0;
|
||||
LSETUP (1f, 2f) LC1 = P1;
|
||||
1:
|
||||
IFLUSH [P0++];
|
||||
CC = P0 < P1 (iu);
|
||||
IF CC JUMP 1b (bp);
|
||||
IFLUSH [P0];
|
||||
SSYNC(R3);
|
||||
.ifnb \optflushins
|
||||
\optflushins [P0];
|
||||
.endif
|
||||
.ifb \optnopins
|
||||
2:
|
||||
.endif
|
||||
\flushins [P0++];
|
||||
.ifnb \optnopins
|
||||
2: \optnopins;
|
||||
.endif
|
||||
|
||||
RTS;
|
||||
.endm
|
||||
|
||||
/* Invalidate all instruction cache lines assocoiated with this memory area */
|
||||
ENTRY(_blackfin_icache_flush_range)
|
||||
do_flush IFLUSH, , nop
|
||||
ENDPROC(_blackfin_icache_flush_range)
|
||||
|
||||
/*
|
||||
* blackfin_icache_dcache_flush_range(start, end)
|
||||
* FLUSH all cache lines assocoiated with this
|
||||
* area of memory.
|
||||
*
|
||||
* start: Start address
|
||||
* end: End address
|
||||
*/
|
||||
|
||||
/* Flush all cache lines assocoiated with this area of memory. */
|
||||
ENTRY(_blackfin_icache_dcache_flush_range)
|
||||
R2 = -L1_CACHE_BYTES;
|
||||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC(R3);
|
||||
IFLUSH [P0];
|
||||
1:
|
||||
FLUSH [P0];
|
||||
IFLUSH [P0++];
|
||||
CC = P0 < P1 (iu);
|
||||
IF CC JUMP 1b (bp);
|
||||
IFLUSH [P0];
|
||||
FLUSH [P0];
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
do_flush IFLUSH, FLUSH
|
||||
ENDPROC(_blackfin_icache_dcache_flush_range)
|
||||
|
||||
/* Throw away all D-cached data in specified region without any obligation to
|
||||
* write them back. However, we must clean the D-cached entries around the
|
||||
* boundaries of the start and/or end address is not cache aligned.
|
||||
*
|
||||
* Start: start address,
|
||||
* end : end address.
|
||||
* write them back. Since the Blackfin ISA does not have an "invalidate"
|
||||
* instruction, we use flush/invalidate. Perhaps as a speed optimization we
|
||||
* could bang on the DTEST MMRs ...
|
||||
*/
|
||||
|
||||
ENTRY(_blackfin_dcache_invalidate_range)
|
||||
R2 = -L1_CACHE_BYTES;
|
||||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC(R3);
|
||||
FLUSHINV[P0];
|
||||
1:
|
||||
FLUSHINV[P0++];
|
||||
CC = P0 < P1 (iu);
|
||||
IF CC JUMP 1b (bp);
|
||||
|
||||
/* If the data crosses a cache line, then we'll be pointing to
|
||||
* the last cache line, but won't have flushed/invalidated it yet,
|
||||
* so do one more.
|
||||
*/
|
||||
FLUSHINV[P0];
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
do_flush FLUSHINV
|
||||
ENDPROC(_blackfin_dcache_invalidate_range)
|
||||
|
||||
/* Flush all data cache lines assocoiated with this memory area */
|
||||
ENTRY(_blackfin_dcache_flush_range)
|
||||
R2 = -L1_CACHE_BYTES;
|
||||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC(R3);
|
||||
FLUSH[P0];
|
||||
1:
|
||||
FLUSH[P0++];
|
||||
CC = P0 < P1 (iu);
|
||||
IF CC JUMP 1b (bp);
|
||||
|
||||
/* If the data crosses a cache line, then we'll be pointing to
|
||||
* the last cache line, but won't have flushed it yet, so do
|
||||
* one more.
|
||||
*/
|
||||
FLUSH[P0];
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
do_flush FLUSH, , , .Ldfr
|
||||
ENDPROC(_blackfin_dcache_flush_range)
|
||||
|
||||
/* Our headers convert the page structure to an address, so just need to flush
|
||||
* its contents like normal. We know the start address is page aligned (which
|
||||
* greater than our cache alignment), as is the end address. So just jump into
|
||||
* the middle of the dcache flush function.
|
||||
*/
|
||||
ENTRY(_blackfin_dflush_page)
|
||||
P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
|
||||
P0 = R0;
|
||||
CSYNC(R3);
|
||||
FLUSH[P0];
|
||||
LSETUP (.Lfl1, .Lfl1) LC0 = P1;
|
||||
.Lfl1: FLUSH [P0++];
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
jump .Ldfr;
|
||||
ENDPROC(_blackfin_dflush_page)
|
||||
|
|
|
@ -206,6 +206,60 @@ ENTRY(_real_start)
|
|||
w[p0] = r0;
|
||||
ssync;
|
||||
|
||||
#if L1_DATA_A_LENGTH > 0
|
||||
r1.l = __sbss_l1;
|
||||
r1.h = __sbss_l1;
|
||||
r2.l = __ebss_l1;
|
||||
r2.h = __ebss_l1;
|
||||
r0 = 0 (z);
|
||||
r2 = r2 - r1;
|
||||
cc = r2 == 0;
|
||||
if cc jump .L_a_l1_done;
|
||||
r2 >>= 2;
|
||||
p1 = r1;
|
||||
p2 = r2;
|
||||
lsetup (.L_clear_a_l1, .L_clear_a_l1 ) lc0 = p2;
|
||||
.L_clear_a_l1:
|
||||
[p1++] = r0;
|
||||
.L_a_l1_done:
|
||||
#endif
|
||||
|
||||
#if L1_DATA_B_LENGTH > 0
|
||||
r1.l = __sbss_b_l1;
|
||||
r1.h = __sbss_b_l1;
|
||||
r2.l = __ebss_b_l1;
|
||||
r2.h = __ebss_b_l1;
|
||||
r0 = 0 (z);
|
||||
r2 = r2 - r1;
|
||||
cc = r2 == 0;
|
||||
if cc jump .L_b_l1_done;
|
||||
r2 >>= 2;
|
||||
p1 = r1;
|
||||
p2 = r2;
|
||||
lsetup (.L_clear_b_l1, .L_clear_b_l1 ) lc0 = p2;
|
||||
.L_clear_b_l1:
|
||||
[p1++] = r0;
|
||||
.L_b_l1_done:
|
||||
#endif
|
||||
|
||||
#if L2_LENGTH > 0
|
||||
r1.l = __sbss_l2;
|
||||
r1.h = __sbss_l2;
|
||||
r2.l = __ebss_l2;
|
||||
r2.h = __ebss_l2;
|
||||
r0 = 0 (z);
|
||||
r2 = r2 - r1;
|
||||
cc = r2 == 0;
|
||||
if cc jump .L_l2_done;
|
||||
r2 >>= 2;
|
||||
p1 = r1;
|
||||
p2 = r2;
|
||||
lsetup (.L_clear_l2, .L_clear_l2 ) lc0 = p2;
|
||||
.L_clear_l2:
|
||||
[p1++] = r0;
|
||||
.L_l2_done:
|
||||
#endif
|
||||
|
||||
/* Zero out the bss region
|
||||
* Note: this will fail if bss is 0 bytes ...
|
||||
*/
|
||||
|
|
Loading…
Reference in a new issue