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arm64: dts: mt8192: Add video-codec nodes
Add video-codec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230303013842.23259-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -1641,6 +1641,65 @@ larb11: larb@1582e000 {
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power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
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};
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vcodec_dec: video-codec@16000000 {
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compatible = "mediatek,mt8192-vcodec-dec";
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reg = <0 0x16000000 0 0x1000>;
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mediatek,scp = <&scp>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0x16000000 0 0x26000>;
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video-codec@10000 {
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compatible = "mediatek,mtk-vcodec-lat";
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reg = <0x0 0x10000 0 0x800>;
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interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
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<&vdecsys_soc CLK_VDEC_SOC_LAT>,
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<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
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};
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video-codec@25000 {
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compatible = "mediatek,mtk-vcodec-core";
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reg = <0 0x25000 0 0x1000>;
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interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys CLK_VDEC_VDEC>,
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<&vdecsys CLK_VDEC_LAT>,
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<&vdecsys CLK_VDEC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
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};
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};
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larb5: larb@1600d000 {
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compatible = "mediatek,mt8192-smi-larb";
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reg = <0 0x1600d000 0 0x1000>;
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