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spi: spi-cadence: Reverse the order of interleaved write and read operations
[ Upstream commit633cd6fe6e
] In the existing implementation, when executing interleaved write and read operations in the ISR for a transfer length greater than the FIFO size, the TXFIFO write precedes the RXFIFO read. Consequently, the initially received data in the RXFIFO is pushed out and lost, leading to a failure in data integrity. To address this issue, reverse the order of interleaved operations and conduct the RXFIFO read followed by the TXFIFO write. Fixes:6afe2ae8dc
("spi: spi-cadence: Interleave write of TX and read of RX FIFO") Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Link: https://msgid.link/r/20231218090652.18403-1-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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parent
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commit
1bd81374bc
1 changed files with 9 additions and 8 deletions
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@ -317,6 +317,15 @@ static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
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xspi->rx_bytes -= nrx;
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while (ntx || nrx) {
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if (nrx) {
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u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
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if (xspi->rxbuf)
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*xspi->rxbuf++ = data;
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nrx--;
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}
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if (ntx) {
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if (xspi->txbuf)
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cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
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@ -326,14 +335,6 @@ static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
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ntx--;
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}
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if (nrx) {
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u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
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if (xspi->rxbuf)
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*xspi->rxbuf++ = data;
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nrx--;
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}
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}
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}
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