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arm64: mte: Allow user control of the tag check mode via prctl()
By default, even if PROT_MTE is set on a memory range, there is no tag check fault reporting (SIGSEGV). Introduce a set of option to the exiting prctl(PR_SET_TAGGED_ADDR_CTRL) to allow user control of the tag check fault mode: PR_MTE_TCF_NONE - no reporting (default) PR_MTE_TCF_SYNC - synchronous tag check fault reporting PR_MTE_TCF_ASYNC - asynchronous tag check fault reporting These options translate into the corresponding SCTLR_EL1.TCF0 bitfield, context-switched by the kernel. Note that the kernel accesses to the user address space (e.g. read() system call) are not checked if the user thread tag checking mode is PR_MTE_TCF_NONE or PR_MTE_TCF_ASYNC. If the tag checking mode is PR_MTE_TCF_SYNC, the kernel makes a best effort to check its user address accesses, however it cannot always guarantee it. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org>
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51b0bff2f7
commit
1c101da8b9
5 changed files with 123 additions and 3 deletions
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@ -21,6 +21,9 @@ void mte_clear_page_tags(void *addr);
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void mte_sync_tags(pte_t *ptep, pte_t pte);
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void mte_copy_page_tags(void *kto, const void *kfrom);
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void flush_mte_state(void);
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void mte_thread_switch(struct task_struct *next);
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long set_mte_ctrl(unsigned long arg);
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long get_mte_ctrl(void);
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#else
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@ -36,6 +39,17 @@ static inline void mte_copy_page_tags(void *kto, const void *kfrom)
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static inline void flush_mte_state(void)
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{
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}
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static inline void mte_thread_switch(struct task_struct *next)
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{
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}
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static inline long set_mte_ctrl(unsigned long arg)
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{
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return 0;
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}
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static inline long get_mte_ctrl(void)
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{
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return 0;
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}
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#endif
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@ -151,6 +151,9 @@ struct thread_struct {
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struct ptrauth_keys_user keys_user;
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struct ptrauth_keys_kernel keys_kernel;
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#endif
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#ifdef CONFIG_ARM64_MTE
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u64 sctlr_tcf0;
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#endif
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};
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static inline void arch_thread_struct_whitelist(unsigned long *offset,
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@ -5,6 +5,8 @@
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#include <linux/bitops.h>
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#include <linux/mm.h>
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#include <linux/prctl.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/thread_info.h>
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@ -49,6 +51,26 @@ int memcmp_pages(struct page *page1, struct page *page2)
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return ret;
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}
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static void update_sctlr_el1_tcf0(u64 tcf0)
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{
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/* ISB required for the kernel uaccess routines */
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF0_MASK, tcf0);
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isb();
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}
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static void set_sctlr_el1_tcf0(u64 tcf0)
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{
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/*
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* mte_thread_switch() checks current->thread.sctlr_tcf0 as an
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* optimisation. Disable preemption so that it does not see
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* the variable update before the SCTLR_EL1.TCF0 one.
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*/
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preempt_disable();
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current->thread.sctlr_tcf0 = tcf0;
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update_sctlr_el1_tcf0(tcf0);
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preempt_enable();
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}
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void flush_mte_state(void)
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{
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if (!system_supports_mte())
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@ -58,4 +80,59 @@ void flush_mte_state(void)
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dsb(ish);
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write_sysreg_s(0, SYS_TFSRE0_EL1);
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clear_thread_flag(TIF_MTE_ASYNC_FAULT);
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/* disable tag checking */
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set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE);
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}
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void mte_thread_switch(struct task_struct *next)
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{
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if (!system_supports_mte())
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return;
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/* avoid expensive SCTLR_EL1 accesses if no change */
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if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0)
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update_sctlr_el1_tcf0(next->thread.sctlr_tcf0);
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}
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long set_mte_ctrl(unsigned long arg)
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{
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u64 tcf0;
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if (!system_supports_mte())
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return 0;
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switch (arg & PR_MTE_TCF_MASK) {
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case PR_MTE_TCF_NONE:
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tcf0 = SCTLR_EL1_TCF0_NONE;
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break;
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case PR_MTE_TCF_SYNC:
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tcf0 = SCTLR_EL1_TCF0_SYNC;
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break;
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case PR_MTE_TCF_ASYNC:
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tcf0 = SCTLR_EL1_TCF0_ASYNC;
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break;
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default:
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return -EINVAL;
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}
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set_sctlr_el1_tcf0(tcf0);
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return 0;
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}
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long get_mte_ctrl(void)
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{
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if (!system_supports_mte())
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return 0;
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switch (current->thread.sctlr_tcf0) {
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case SCTLR_EL1_TCF0_NONE:
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return PR_MTE_TCF_NONE;
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case SCTLR_EL1_TCF0_SYNC:
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return PR_MTE_TCF_SYNC;
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case SCTLR_EL1_TCF0_ASYNC:
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return PR_MTE_TCF_ASYNC;
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}
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return 0;
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}
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@ -577,6 +577,13 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
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*/
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dsb(ish);
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/*
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* MTE thread switching must happen after the DSB above to ensure that
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* any asynchronous tag check faults have been logged in the TFSR*_EL1
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* registers.
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*/
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mte_thread_switch(next);
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/* the actual thread switch */
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last = cpu_switch_to(prev, next);
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@ -636,9 +643,15 @@ static unsigned int tagged_addr_disabled;
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long set_tagged_addr_ctrl(unsigned long arg)
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{
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unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
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if (is_compat_task())
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return -EINVAL;
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if (arg & ~PR_TAGGED_ADDR_ENABLE)
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if (system_supports_mte())
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valid_mask |= PR_MTE_TCF_MASK;
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if (arg & ~valid_mask)
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return -EINVAL;
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/*
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@ -648,6 +661,9 @@ long set_tagged_addr_ctrl(unsigned long arg)
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if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
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return -EINVAL;
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if (set_mte_ctrl(arg) != 0)
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return -EINVAL;
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update_thread_flag(TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
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return 0;
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@ -655,13 +671,17 @@ long set_tagged_addr_ctrl(unsigned long arg)
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long get_tagged_addr_ctrl(void)
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{
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long ret = 0;
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if (is_compat_task())
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return -EINVAL;
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if (test_thread_flag(TIF_TAGGED_ADDR))
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return PR_TAGGED_ADDR_ENABLE;
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ret = PR_TAGGED_ADDR_ENABLE;
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return 0;
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ret |= get_mte_ctrl();
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return ret;
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}
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/*
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@ -233,6 +233,12 @@ struct prctl_mm_map {
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#define PR_SET_TAGGED_ADDR_CTRL 55
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#define PR_GET_TAGGED_ADDR_CTRL 56
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# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
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/* MTE tag check fault modes */
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# define PR_MTE_TCF_SHIFT 1
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# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
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/* Control reclaim behavior when allocating memory */
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#define PR_SET_IO_FLUSHER 57
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