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sound updates for 4.16-rc1 

The major changes in the core API side in this cycle are the still
 on-going ASoC componentization works.  Other than that, only few small
 changes such as 20bit PCM format support are found.
 
 Meanwhile the rest majority of changes are for ASoC drivers:
 - Large cleanups of some of the TI CODEC drivers
 - Continued work on Intel ASoC stuff for new quirks, ACPI GPIO
   handling, Kconfigs and lots of cleanups
 - Refactoring of the Freescale SSI driver, as preliminary work for the
   upcoming changes
 - Work on ST DFSDM driver, including the required IIO patches
 - New drivers for Allwinner A83T, Maxim MAX89373, SocioNext UiniPhier
   EVEA Tempo Semiconductor TSCS42xx and TI PCM816x, TAS5722 and TAS6424
   devices
 - Removal of dead codes for SN95031 and board drivers
 
 Last but not least, a few HD-audio and USB-audio quirks are included
 as usual, too.
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Merge tag 'sound-4.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai:
 "The major changes in the core API side in this cycle are the still
  on-going ASoC componentization works. Other than that, only few small
  changes such as 20bit PCM format support are found.

  Meanwhile the rest majority of changes are for ASoC drivers:

   - Large cleanups of some of the TI CODEC drivers

   - Continued work on Intel ASoC stuff for new quirks, ACPI GPIO
     handling, Kconfigs and lots of cleanups

   - Refactoring of the Freescale SSI driver, as preliminary work for
     the upcoming changes

   - Work on ST DFSDM driver, including the required IIO patches

   - New drivers for Allwinner A83T, Maxim MAX89373, SocioNext UiniPhier
     EVEA Tempo Semiconductor TSCS42xx and TI PCM816x, TAS5722 and
     TAS6424 devices

   - Removal of dead codes for SN95031 and board drivers

  Last but not least, a few HD-audio and USB-audio quirks are included
  as usual, too"

* tag 'sound-4.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (303 commits)
  ALSA: hda - Reduce the suspend time consumption for ALC256
  ASoC: use seq_file to dump the contents of dai_list,platform_list and codec_list
  ASoC: soc-core: add missing EXPORT_SYMBOL_GPL() for snd_soc_rtdcom_lookup
  IIO: ADC: stm32-dfsdm: remove unused variable again
  ASoC: bcm2835: fix hw_params error when device is in prepared state
  ASoC: mxs-sgtl5000: Do not print error on probe deferral
  ASoC: sgtl5000: Do not print error on probe deferral
  ASoC: Intel: remove select on non-existing SND_SOC_INTEL_COMMON
  ALSA: usb-audio: Support changing input on Sound Blaster E1
  ASoC: Intel: remove second duplicated assignment to pointer 'res'
  ALSA: hda/realtek - update ALC215 depop optimize
  ALSA: hda/realtek - Support headset mode for ALC215/ALC285/ALC289
  ALSA: pcm: Fix trailing semicolon
  ASoC: add Component level .read/.write
  ASoC: cx20442: fix regression by adding back .read/.write
  ASoC: uda1380: fix regression by adding back .read/.write
  ASoC: tlv320dac33: fix regression by adding back .read/.write
  ALSA: hda - Use IS_REACHABLE() for dependency on input
  IIO: ADC: stm32-dfsdm: fix static check warning
  IIO: ADC: stm32-dfsdm: code optimization
  ...
This commit is contained in:
Linus Torvalds 2018-01-29 09:41:47 -08:00
parent 49f9c3552c 1c9609e3a8
commit 1c1f395b28
231 changed files with 15787 additions and 5297 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 Normal file
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@ -0,0 +1,16 @@
What: /sys/bus/iio/devices/iio:deviceX/in_voltage_spi_clk_freq
KernelVersion: 4.14
Contact: arnaud.pouliquen@st.com
Description:
For audio purpose only.
Used by audio driver to set/get the spi input frequency.
This is mandatory if DFSDM is slave on SPI bus, to
provide information on the SPI clock frequency during runtime
Notice that the SPI frequency should be a multiple of sample
frequency to ensure the precision.
if DFSDM input is SPI master
Reading SPI clkout frequency,
error on writing
If DFSDM input is SPI Slave:
Reading returns value previously set.
Writing value before starting conversions.

13
Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt Normal file
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@ -0,0 +1,13 @@
Device-Tree bindings for sigma delta modulator
Required properties:
- compatible: should be "ads1201", "sd-modulator". "sd-modulator" can be use
as a generic SD modulator if modulator not specified in compatible list.
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
Example node:
ads1202: adc@0 {
compatible = "sd-modulator";
#io-channel-cells = <1>;
};

128
Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt Normal file
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@ -0,0 +1,128 @@
STMicroelectronics STM32 DFSDM ADC device driver
STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
interface external sigma delta modulators to STM32 micro controllers.
It is mainly targeted for:
- Sigma delta modulators (motor control, metering...)
- PDM microphones (audio digital microphone)
It features up to 8 serial digital interfaces (SPI or Manchester) and
up to 4 filters on stm32h7.
Each child node match with a filter instance.
Contents of a STM32 DFSDM root node:
------------------------------------
Required properties:
- compatible: Should be "st,stm32h7-dfsdm".
- reg: Offset and length of the DFSDM block register set.
- clocks: IP and serial interfaces clocking. Should be set according
to rcc clock ID and "clock-names".
- clock-names: Input clock name "dfsdm" must be defined,
"audio" is optional. If defined CLKOUT is based on the audio
clock, else "dfsdm" is used.
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties:
- spi-max-frequency: Requested only for SPI master mode.
SPI clock OUT frequency (Hz). This clock must be set according
to "clock" property. Frequency must be a multiple of the rcc
clock frequency. If not, SPI CLKOUT frequency will not be
accurate.
Contents of a STM32 DFSDM child nodes:
--------------------------------------
Required properties:
- compatible: Must be:
"st,stm32-dfsdm-adc" for sigma delta ADCs
"st,stm32-dfsdm-dmic" for audio digital microphone.
- reg: Specifies the DFSDM filter instance used.
- interrupts: IRQ lines connected to each DFSDM filter instance.
- st,adc-channels: List of single-ended channels muxed for this ADC.
valid values:
"st,stm32h7-dfsdm" compatibility: 0 to 7.
- st,adc-channel-names: List of single-ended channel names.
- st,filter-order: SinC filter order from 0 to 5.
0: FastSinC
[1-5]: order 1 to 5.
For audio purpose it is recommended to use order 3 to 5.
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
Required properties for "st,stm32-dfsdm-adc" compatibility:
- io-channels: From common IIO binding. Used to pipe external sigma delta
modulator or internal ADC output to DFSDM channel.
This is not required for "st,stm32-dfsdm-pdm" compatibility as
PDM microphone is binded in Audio DT node.
Required properties for "st,stm32-dfsdm-pdm" compatibility:
- #sound-dai-cells: Must be set to 0.
- dma: DMA controller phandle and DMA request line associated to the
filter instance (specified by the field "reg")
- dma-names: Must be "rx"
Optional properties:
- st,adc-channel-types: Single-ended channel input type.
- "SPI_R": SPI with data on rising edge (default)
- "SPI_F": SPI with data on falling edge
- "MANCH_R": manchester codec, rising edge = logic 0
- "MANCH_F": manchester codec, falling edge = logic 1
- st,adc-channel-clk-src: Conversion clock source.
- "CLKIN": external SPI clock (CLKIN x)
- "CLKOUT": internal SPI clock (CLKOUT) (default)
- "CLKOUT_F": internal SPI clock divided by 2 (falling edge).
- "CLKOUT_R": internal SPI clock divided by 2 (rising edge).
- st,adc-alt-channel: Must be defined if two sigma delta modulator are
connected on same SPI input.
If not set, channel n is connected to SPI input n.
If set, channel n is connected to SPI input n + 1.
- st,filter0-sync: Set to 1 to synchronize with DFSDM filter instance 0.
Used for multi microphones synchronization.
Example of a sigma delta adc connected on DFSDM SPI port 0
and a pdm microphone connected on DFSDM SPI port 1:
ads1202: simple_sd_adc@0 {
compatible = "ads1202";
#io-channel-cells = <1>;
};
dfsdm: dfsdm@40017000 {
compatible = "st,stm32h7-dfsdm";
reg = <0x40017000 0x400>;
clocks = <&rcc DFSDM1_CK>;
clock-names = "dfsdm";
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
dfsdm_adc0: filter@0 {
compatible = "st,stm32-dfsdm-adc";
#io-channel-cells = <1>;
reg = <0>;
interrupts = <110>;
st,adc-channels = <0>;
st,adc-channel-names = "sd_adc0";
st,adc-channel-types = "SPI_F";
st,adc-channel-clk-src = "CLKOUT";
io-channels = <&ads1202 0>;
st,filter-order = <3>;
};
dfsdm_pdm1: filter@1 {
compatible = "st,stm32-dfsdm-dmic";
reg = <1>;
interrupts = <111>;
dmas = <&dmamux1 102 0x400 0x00>;
dma-names = "rx";
st,adc-channels = <1>;
st,adc-channel-names = "dmic1";
st,adc-channel-types = "SPI_R";
st,adc-channel-clk-src = "CLKOUT";
st,filter-order = <5>;
};
}

2
Documentation/devicetree/bindings/sound/dmic.txt
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@ -7,10 +7,12 @@ Required properties:
Optional properties:
- dmicen-gpios: GPIO specifier for dmic to control start and stop
- num-channels: Number of microphones on this DAI
Example node:
dmic_codec: dmic@0 {
compatible = "dmic-codec";
dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
num-channels = <1>;
};

40
Documentation/devicetree/bindings/sound/max98373.txt Normal file
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@ -0,0 +1,40 @@
Maxim Integrated MAX98373 Speaker Amplifier
This device supports I2C.
Required properties:
- compatible : "maxim,max98373"
- reg : the I2C address of the device.
Optional properties:
- maxim,vmon-slot-no : slot number used to send voltage information
or in inteleave mode this will be used as
interleave slot.
slot range : 0 ~ 15, Default : 0
- maxim,imon-slot-no : slot number used to send current information
slot range : 0 ~ 15, Default : 0
- maxim,spkfb-slot-no : slot number used to send speaker feedback information
slot range : 0 ~ 15, Default : 0
- maxim,interleave-mode : For cases where a single combined channel
for the I/V sense data is not sufficient, the device can also be configured
to share a single data output channel on alternating frames.
In this configuration, the current and voltage data will be frame interleaved
on a single output channel.
Boolean, define to enable the interleave mode, Default : false
Example:
codec: max98373@31 {
compatible = "maxim,max98373";
reg = <0x31>;
maxim,vmon-slot-no = <0>;
maxim,imon-slot-no = <1>;
maxim,spkfb-slot-no = <2>;
maxim,interleave-mode;
};

266
Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
View File

@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701
Required properties:
- compatible = "mediatek,mt2701-audio";
- reg: register location and size
- interrupts: should contain AFE and ASYS interrupts
- interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain
- clocks: Must contain an entry for each entry in clock-names
See ../clocks/clock-bindings.txt for details
- clock-names: should have these clock names:
"infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_mux1_div",
"top_audio_mux2_div",
"top_audio_48k_timing",
"top_audio_44k_timing",
"top_audpll_mux_sel",
"top_apll_sel",
"top_aud1_pll_98M",
"top_aud2_pll_90M",
"top_hadds2_pll_98M",
"top_hadds2_pll_294M",
"top_audpll",
"top_audpll_d4",
"top_audpll_d8",
"top_audpll_d16",
"top_audpll_d24",
"top_audintbus_sel",
"clk_26m",
"top_syspll1_d4",
"top_aud_k1_src_sel",
"top_aud_k2_src_sel",
"top_aud_k3_src_sel",
"top_aud_k4_src_sel",
"top_aud_k5_src_sel",
"top_aud_k6_src_sel",
"top_aud_k1_src_div",
"top_aud_k2_src_div",
"top_aud_k3_src_div",
"top_aud_k4_src_div",
"top_aud_k5_src_div",
"top_aud_k6_src_div",
"top_aud_i2s1_mclk",
"top_aud_i2s2_mclk",
"top_aud_i2s3_mclk",
"top_aud_i2s4_mclk",
"top_aud_i2s5_mclk",
"top_aud_i2s6_mclk",
"top_asm_m_sel",
"top_asm_h_sel",
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
- assigned-clocks: list of input clocks and dividers for the audio system.
See ../clocks/clock-bindings.txt for details.
- assigned-clocks-parents: parent of input clocks of assigned clocks.
- assigned-clock-rates: list of clock frequencies of assigned clocks.
Must be a subnode of MediaTek audsys device tree node.
See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
Example:
afe: mt2701-afe-pcm@11220000 {
compatible = "mediatek,mt2701-audio";
reg = <0 0x11220000 0 0x2000>,
<0 0x112A0000 0 0x20000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
<&topckgen CLK_TOP_APLL_SEL>,
<&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>,
<&topckgen CLK_TOP_HADDS2PLL_98M>,
<&topckgen CLK_TOP_HADDS2PLL_294M>,
<&topckgen CLK_TOP_AUDPLL>,
<&topckgen CLK_TOP_AUDPLL_D4>,
<&topckgen CLK_TOP_AUDPLL_D8>,
<&topckgen CLK_TOP_AUDPLL_D16>,
<&topckgen CLK_TOP_AUDPLL_D24>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_SYSPLL1_D4>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
<&topckgen CLK_TOP_ASM_M_SEL>,
<&topckgen CLK_TOP_ASM_H_SEL>,
<&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_UNIVPLL2_D2>,
<&topckgen CLK_TOP_SYSPLL_D5>;
audsys: audio-subsystem@11220000 {
compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
...
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_mux1_div",
"top_audio_mux2_div",
"top_audio_48k_timing",
"top_audio_44k_timing",
"top_audpll_mux_sel",
"top_apll_sel",
"top_aud1_pll_98M",
"top_aud2_pll_90M",
"top_hadds2_pll_98M",
"top_hadds2_pll_294M",
"top_audpll",
"top_audpll_d4",
"top_audpll_d8",
"top_audpll_d16",
"top_audpll_d24",
"top_audintbus_sel",
"clk_26m",
"top_syspll1_d4",
"top_aud_k1_src_sel",
"top_aud_k2_src_sel",
"top_aud_k3_src_sel",
"top_aud_k4_src_sel",
"top_aud_k5_src_sel",
"top_aud_k6_src_sel",
"top_aud_k1_src_div",
"top_aud_k2_src_div",
"top_aud_k3_src_div",
"top_aud_k4_src_div",
"top_aud_k5_src_div",
"top_aud_k6_src_div",
"top_aud_i2s1_mclk",
"top_aud_i2s2_mclk",
"top_aud_i2s3_mclk",
"top_aud_i2s4_mclk",
"top_aud_i2s5_mclk",
"top_aud_i2s6_mclk",
"top_asm_m_sel",
"top_asm_h_sel",
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
afe: audio-controller {
compatible = "mediatek,mt2701-audio";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&audsys CLK_AUD_I2SO1>,
<&audsys CLK_AUD_I2SO2>,
<&audsys CLK_AUD_I2SO3>,
<&audsys CLK_AUD_I2SO4>,
<&audsys CLK_AUD_I2SIN1>,
<&audsys CLK_AUD_I2SIN2>,
<&audsys CLK_AUD_I2SIN3>,
<&audsys CLK_AUD_I2SIN4>,
<&audsys CLK_AUD_ASRCO1>,
<&audsys CLK_AUD_ASRCO2>,
<&audsys CLK_AUD_ASRCO3>,
<&audsys CLK_AUD_ASRCO4>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_AFE_CONN>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_AFE_MRGIF>;
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>;
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
};
};

33
Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt
View File

@ -1,10 +1,31 @@
* Freescale MXS audio complex with SGTL5000 codec
Required properties:
- compatible: "fsl,mxs-audio-sgtl5000"
- model: The user-visible name of this sound complex
- saif-controllers: The phandle list of the MXS SAIF controller
- audio-codec: The phandle of the SGTL5000 audio codec
- compatible : "fsl,mxs-audio-sgtl5000"
- model : The user-visible name of this sound complex
- saif-controllers : The phandle list of the MXS SAIF controller
- audio-codec : The phandle of the SGTL5000 audio codec
- audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the
connection's sink, the second being the connection's
source. Valid names could be power supplies, SGTL5000
pins, and the jacks on the board:
Power supplies:
* Mic Bias
SGTL5000 pins:
* MIC_IN
* LINE_IN
* HP_OUT
* LINE_OUT
Board connectors:
* Mic Jack
* Line In Jack
* Headphone Jack
* Line Out Jack
* Ext Spk
Example:
@ -14,4 +35,8 @@ sound {
model = "imx28-evk-sgtl5000";
saif-controllers = <&saif0 &saif1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
};

4
Documentation/devicetree/bindings/sound/nau8825.txt
View File

@ -69,7 +69,7 @@ Optional properties:
- nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
- nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
- nuvoton,crosstalk-bypass: make crosstalk function bypass if set.
- nuvoton,crosstalk-enable: make crosstalk function enable if set.
- clocks: list of phandle and clock specifier pairs according to common clock bindings for the
clocks described in clock-names
@ -98,7 +98,7 @@ Example:
nuvoton,short-key-debounce = <2>;
nuvoton,jack-insert-debounce = <7>;
nuvoton,jack-eject-debounce = <7>;
nuvoton,crosstalk-bypass;
nuvoton,crosstalk-enable;
clock-names = "mclk";
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;

42
Documentation/devicetree/bindings/sound/pcm186x.txt Normal file
View File

@ -0,0 +1,42 @@
Texas Instruments PCM186x Universal Audio ADC
These devices support both I2C and SPI (configured with pin strapping
on the board).
Required properties:
- compatible : "ti,pcm1862",
"ti,pcm1863",
"ti,pcm1864",
"ti,pcm1865"
- reg : The I2C address of the device for I2C, the chip select
number for SPI.
- avdd-supply: Analog core power supply (3.3v)
- dvdd-supply: Digital core power supply
- iovdd-supply: Digital IO power supply
See regulator/regulator.txt for more information
CODEC input pins:
* VINL1
* VINR1
* VINL2
* VINR2
* VINL3
* VINR3
* VINL4
* VINR4
The pins can be used in referring sound node's audio-routing property.
Example:
pcm186x: audio-codec@4a {
compatible = "ti,pcm1865";
reg = <0x4a>;
avdd-supply = <&reg_3v3_analog>;
dvdd-supply = <&reg_3v3>;
iovdd-supply = <&reg_1v8>;
};

15
Documentation/devicetree/bindings/sound/renesas,rsnd.txt
View File

@ -4,7 +4,7 @@ Renesas R-Car sound
* Modules
=============================================
Renesas R-Car sound is constructed from below modules
Renesas R-Car and RZ/G sound is constructed from below modules
(for Gen2 or later)
SCU : Sampling Rate Converter Unit
@ -197,12 +197,17 @@ Ex)
[MEM] -> [SRC2] -> [CTU03] -+
sound {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-scu-audio-card";
...
simple-audio-card,cpu-0 {
simple-audio-card,cpu@0 {
reg = <0>;
sound-dai = <&rcar_sound 0>;
};
simple-audio-card,cpu-1 {
simple-audio-card,cpu@1 {
reg = <1>;
sound-dai = <&rcar_sound 1>;
};
simple-audio-card,codec {
@ -334,9 +339,11 @@ Required properties:
- compatible : "renesas,rcar_sound-<soctype>", fallbacks
"renesas,rcar_sound-gen1" if generation1, and
"renesas,rcar_sound-gen2" if generation2
"renesas,rcar_sound-gen2" if generation2 (or RZ/G1)
"renesas,rcar_sound-gen3" if generation3
Examples with soctypes are:
- "renesas,rcar_sound-r8a7743" (RZ/G1M)
- "renesas,rcar_sound-r8a7745" (RZ/G1E)
- "renesas,rcar_sound-r8a7778" (R-Car M1A)
- "renesas,rcar_sound-r8a7779" (R-Car H1)
- "renesas,rcar_sound-r8a7790" (R-Car H2)

3
Documentation/devicetree/bindings/sound/simple-card.txt
View File

@ -140,6 +140,7 @@ sound {
simple-audio-card,name = "Cubox Audio";
simple-audio-card,dai-link@0 { /* I2S - HDMI */
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&audio1 0>;
@ -150,6 +151,7 @@ sound {
};
simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */
reg = <1>;
cpu {
sound-dai = <&audio1 1>;
};
@ -159,6 +161,7 @@ sound {
};
simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */
reg = <2>;
cpu {
sound-dai = <&audio1 1>;
};

63
Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt Normal file
View File

@ -0,0 +1,63 @@
STMicroelectronics Audio Digital Filter Sigma Delta modulators(DFSDM)
The DFSDM allows PDM microphones capture through SPI interface. The Audio
interface is seems as a sub block of the DFSDM device.
For details on DFSDM bindings refer to ../iio/adc/st,stm32-dfsdm-adc.txt
Required properties:
- compatible: "st,stm32h7-dfsdm-dai".
- #sound-dai-cells : Must be equal to 0
- io-channels : phandle to iio dfsdm instance node.
Example of a sound card using audio DFSDM node.
sound_card {
compatible = "audio-graph-card";
dais = <&cpu_port>;
};
dfsdm: dfsdm@40017000 {
compatible = "st,stm32h7-dfsdm";
reg = <0x40017000 0x400>;
clocks = <&rcc DFSDM1_CK>;
clock-names = "dfsdm";
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
dfsdm_adc0: filter@0 {
compatible = "st,stm32-dfsdm-dmic";
reg = <0>;
interrupts = <110>;
dmas = <&dmamux1 101 0x400 0x00>;
dma-names = "rx";
st,adc-channels = <1>;
st,adc-channel-names = "dmic0";
st,adc-channel-types = "SPI_R";
st,adc-channel-clk-src = "CLKOUT";
st,filter-order = <5>;
dfsdm_dai0: dfsdm-dai {
compatible = "st,stm32h7-dfsdm-dai";
#sound-dai-cells = <0>;
io-channels = <&dfsdm_adc0 0>;
cpu_port: port {
dfsdm_endpoint: endpoint {
remote-endpoint = <&dmic0_endpoint>;
};
};
};
};
dmic0: dmic@0 {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
port {
dmic0_endpoint: endpoint {
remote-endpoint = <&dfsdm_endpoint>;
};
};
};

12
Documentation/devicetree/bindings/sound/st,stm32-sai.txt
View File

@ -20,11 +20,6 @@ Required properties:
Optional properties:
- resets: Reference to a reset controller asserting the SAI
- st,sync: specify synchronization mode.
By default SAI sub-block is in asynchronous mode.
This property sets SAI sub-block as slave of another SAI sub-block.
Must contain the phandle and index of the sai sub-block providing
the synchronization.
SAI subnodes:
Two subnodes corresponding to SAI sub-block instances A et B can be defined.
@ -44,6 +39,13 @@ SAI subnodes required properties:
- pinctrl-names: should contain only value "default"
- pinctrl-0: see Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt
SAI subnodes Optional properties:
- st,sync: specify synchronization mode.
By default SAI sub-block is in asynchronous mode.
This property sets SAI sub-block as slave of another SAI sub-block.
Must contain the phandle and index of the sai sub-block providing
the synchronization.
The device node should contain one 'port' child node with one child 'endpoint'
node, according to the bindings defined in Documentation/devicetree/bindings/
graph.txt.

2
Documentation/devicetree/bindings/sound/sun4i-i2s.txt
View File

@ -8,6 +8,7 @@ Required properties:
- compatible: should be one of the following:
- "allwinner,sun4i-a10-i2s"
- "allwinner,sun6i-a31-i2s"
- "allwinner,sun8i-a83t-i2s"
- "allwinner,sun8i-h3-i2s"
- reg: physical base address of the controller and length of memory mapped
region.
@ -23,6 +24,7 @@ Required properties:
Required properties for the following compatibles:
- "allwinner,sun6i-a31-i2s"
- "allwinner,sun8i-a83t-i2s"
- "allwinner,sun8i-h3-i2s"
- resets: phandle to the reset line for this codec

4
Documentation/devicetree/bindings/sound/tas5720.txt
View File

@ -6,10 +6,12 @@ audio playback. For more product information please see the links below:
http://www.ti.com/product/TAS5720L
http://www.ti.com/product/TAS5720M
http://www.ti.com/product/TAS5722L
Required properties:
- compatible : "ti,tas5720"
- compatible : "ti,tas5720",
"ti,tas5722"
- reg : I2C slave address
- dvdd-supply : phandle to a 3.3-V supply for the digital circuitry
- pvdd-supply : phandle to a supply used for the Class-D amp and the analog

8
Documentation/devicetree/bindings/sound/tfa9879.txt
View File

@ -6,18 +6,18 @@ Required properties:
- reg : the I2C address of the device
- #sound-dai-cells : must be 0.
Example:
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: tfa9879@6c {
amp: amp@6c {
#sound-dai-cells = <0>;
compatible = "nxp,tfa9879";
reg = <0x6c>;
};
};
};

20
Documentation/devicetree/bindings/sound/ti,tas6424.txt Normal file
View File

@ -0,0 +1,20 @@
Texas Instruments TAS6424 Quad-Channel Audio amplifier
The TAS6424 serial control bus communicates through I2C protocols.
Required properties:
- compatible: "ti,tas6424" - TAS6424
- reg: I2C slave address
- sound-dai-cells: must be equal to 0
Example:
tas6424: tas6424@6a {
compatible = "ti,tas6424";
reg = <0x6a>;
#sound-dai-cells = <0>;
};
For more product information please see the link below:
http://www.ti.com/product/TAS6424-Q1

9
Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
View File

@ -22,7 +22,7 @@ Required properties:
Optional properties:
- gpio-reset - gpio pin number used for codec reset
- reset-gpios - GPIO specification for the active low RESET input.
- ai31xx-micbias-vg - MicBias Voltage setting
1 or MICBIAS_2_0V - MICBIAS output is powered to 2.0V
2 or MICBIAS_2_5V - MICBIAS output is powered to 2.5V
@ -30,6 +30,10 @@ Optional properties:
If this node is not mentioned or if the value is unknown, then
micbias is set to 2.0V.
Deprecated properties:
- gpio-reset - gpio pin number used for codec reset
CODEC output pins:
* HPL
* HPR
@ -48,6 +52,7 @@ CODEC input pins:
The pins can be used in referring sound node's audio-routing property.
Example:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
tlv320aic31xx: tlv320aic31xx@18 {
@ -56,6 +61,8 @@ tlv320aic31xx: tlv320aic31xx@18 {
ai31xx-micbias-vg = <MICBIAS_OFF>;
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
HPVDD-supply = <&regulator>;
SPRVDD-supply = <&regulator>;
SPLVDD-supply = <&regulator>;

10
Documentation/devicetree/bindings/sound/tlv320aic3x.txt
View File

@ -17,7 +17,7 @@ Required properties:
Optional properties:
- gpio-reset - gpio pin number used for codec reset
- reset-gpios - GPIO specification for the active low RESET input.
- ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality
- Not supported on tlv320aic3104
- ai3x-micbias-vg - MicBias Voltage required.
@ -34,6 +34,10 @@ Optional properties:
- AVDD-supply, IOVDD-supply, DRVDD-supply, DVDD-supply : power supplies for the
device as covered in Documentation/devicetree/bindings/regulator/regulator.txt
Deprecated properties:
- gpio-reset - gpio pin number used for codec reset
CODEC output pins:
* LLOUT
* RLOUT
@ -61,10 +65,14 @@ The pins can be used in referring sound node's audio-routing property.
Example:
#include <dt-bindings/gpio/gpio.h>
tlv320aic3x: tlv320aic3x@1b {
compatible = "ti,tlv320aic3x";
reg = <0x1b>;
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
AVDD-supply = <&regulator>;
IOVDD-supply = <&regulator>;
DRVDD-supply = <&regulator>;

16
Documentation/devicetree/bindings/sound/tscs42xx.txt Normal file
View File

@ -0,0 +1,16 @@
TSCS42XX Audio CODEC
Required Properties:
- compatible : "tempo,tscs42A1" for analog mic
"tempo,tscs42A2" for digital mic
- reg : <0x71> for analog mic
<0x69> for digital mic
Example:
wookie: codec@69 {
compatible = "tempo,tscs42A2";
reg = <0x69>;
};

26
Documentation/devicetree/bindings/sound/uniphier,evea.txt Normal file
View File

@ -0,0 +1,26 @@
Socionext EVEA - UniPhier SoC internal codec driver
Required properties:
- compatible : should be "socionext,uniphier-evea".
- reg : offset and length of the register set for the device.
- clock-names : should include following entries:
"evea", "exiv"
- clocks : a list of phandle, should contain an entry for each
entries in clock-names.
- reset-names : should include following entries:
"evea", "exiv", "adamv"
- resets : a list of phandle, should contain reset entries of
reset-names.
- #sound-dai-cells: should be 1.
Example:
codec {
compatible = "socionext,uniphier-evea";
reg = <0x57900000 0x1000>;
clock-names = "evea", "exiv";
clocks = <&sys_clk 41>, <&sys_clk 42>;
reset-names = "evea", "exiv", "adamv";
resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
#sound-dai-cells = <1>;
};

1
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -347,6 +347,7 @@ tcg Trusted Computing Group
tcl Toby Churchill Ltd.
technexion TechNexion
technologic Technologic Systems
tempo Tempo Semiconductor
terasic Terasic Inc.
thine THine Electronics, Inc.
ti Texas Instruments

51
Documentation/driver-api/iio/hw-consumer.rst Normal file
View File

@ -0,0 +1,51 @@
===========
HW consumer
===========
An IIO device can be directly connected to another device in hardware. in this
case the buffers between IIO provider and IIO consumer are handled by hardware.
The Industrial I/O HW consumer offers a way to bond these IIO devices without
software buffer for data. The implementation can be found under
:file:`drivers/iio/buffer/hw-consumer.c`
* struct :c:type:`iio_hw_consumer` — Hardware consumer structure
* :c:func:`iio_hw_consumer_alloc` — Allocate IIO hardware consumer
* :c:func:`iio_hw_consumer_free` — Free IIO hardware consumer
* :c:func:`iio_hw_consumer_enable` — Enable IIO hardware consumer
* :c:func:`iio_hw_consumer_disable` — Disable IIO hardware consumer
HW consumer setup
=================
As standard IIO device the implementation is based on IIO provider/consumer.
A typical IIO HW consumer setup looks like this::
static struct iio_hw_consumer *hwc;
static const struct iio_info adc_info = {
.read_raw = adc_read_raw,
};
static int adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
ret = iio_hw_consumer_enable(hwc);
/* Acquire data */
ret = iio_hw_consumer_disable(hwc);
}
static int adc_probe(struct platform_device *pdev)
{
hwc = devm_iio_hw_consumer_alloc(&iio->dev);
}
More details
============
.. kernel-doc:: include/linux/iio/hw-consumer.h
.. kernel-doc:: drivers/iio/buffer/industrialio-hw-consumer.c
:export:

1
Documentation/driver-api/iio/index.rst
View File

@ -15,3 +15,4 @@ Contents:
buffers
triggers
triggered-buffers
hw-consumer

14
MAINTAINERS
View File

@ -9802,6 +9802,7 @@ NXP TFA9879 DRIVER
M: Peter Rosin <peda@axentia.se>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/sound/tfa9879.txt
F: sound/soc/codecs/tfa9879*
NXP-NCI NFC DRIVER
@ -12590,6 +12591,12 @@ F: include/media/soc*
F: drivers/media/i2c/soc_camera/
F: drivers/media/platform/soc_camera/
SOCIONEXT UNIPHIER SOUND DRIVER
M: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Maintained
F: sound/soc/uniphier/
SOEKRIS NET48XX LED SUPPORT
M: Chris Boot <bootc@bootc.net>
S: Maintained
@ -13848,6 +13855,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial.git
S: Maintained
K: ^Subject:.*(?i)trivial
TEMPO SEMICONDUCTOR DRIVERS
M: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
S: Maintained
F: sound/soc/codecs/tscs*.c
F: sound/soc/codecs/tscs*.h
F: Documentation/devicetree/bindings/sound/tscs*.txt
TTY LAYER
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: Jiri Slaby <jslaby@suse.com>

41
drivers/acpi/utils.c
View File

@ -737,16 +737,17 @@ bool acpi_dev_found(const char *hid)
}
EXPORT_SYMBOL(acpi_dev_found);
struct acpi_dev_present_info {
struct acpi_dev_match_info {
const char *dev_name;
struct acpi_device_id hid[2];
const char *uid;
s64 hrv;
};
static int acpi_dev_present_cb(struct device *dev, void *data)
static int acpi_dev_match_cb(struct device *dev, void *data)
{
struct acpi_device *adev = to_acpi_device(dev);
struct acpi_dev_present_info *match = data;
struct acpi_dev_match_info *match = data;
unsigned long long hrv;
acpi_status status;
@ -757,6 +758,8 @@ static int acpi_dev_present_cb(struct device *dev, void *data)
strcmp(adev->pnp.unique_id, match->uid)))
return 0;
match->dev_name = acpi_dev_name(adev);
if (match->hrv == -1)
return 1;
@ -789,20 +792,44 @@ static int acpi_dev_present_cb(struct device *dev, void *data)
*/
bool acpi_dev_present(const char *hid, const char *uid, s64 hrv)
{
struct acpi_dev_present_info match = {};
struct acpi_dev_match_info match = {};
struct device *dev;
strlcpy(match.hid[0].id, hid, sizeof(match.hid[0].id));
match.uid = uid;
match.hrv = hrv;
dev = bus_find_device(&acpi_bus_type, NULL, &match,
acpi_dev_present_cb);
dev = bus_find_device(&acpi_bus_type, NULL, &match, acpi_dev_match_cb);
return !!dev;
}
EXPORT_SYMBOL(acpi_dev_present);
/**
* acpi_dev_get_first_match_name - Return name of first match of ACPI device
* @hid: Hardware ID of the device.
* @uid: Unique ID of the device, pass NULL to not check _UID
* @hrv: Hardware Revision of the device, pass -1 to not check _HRV
*
* Return device name if a matching device was present
* at the moment of invocation, or NULL otherwise.
*
* See additional information in acpi_dev_present() as well.
*/
const char *
acpi_dev_get_first_match_name(const char *hid, const char *uid, s64 hrv)
{
struct acpi_dev_match_info match = {};
struct device *dev;
strlcpy(match.hid[0].id, hid, sizeof(match.hid[0].id));
match.uid = uid;
match.hrv = hrv;
dev = bus_find_device(&acpi_bus_type, NULL, &match, acpi_dev_match_cb);
return dev ? match.dev_name : NULL;
}
EXPORT_SYMBOL(acpi_dev_get_first_match_name);
/*
* acpi_backlight= handling, this is done here rather then in video_detect.c
* because __setup cannot be used in modules.

11
drivers/gpio/gpio-merrifield.c
View File

@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
@ -380,9 +381,16 @@ static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
}
}
static const char *mrfld_gpio_get_pinctrl_dev_name(void)
{
const char *dev_name = acpi_dev_get_first_match_name("INTC1002", NULL, -1);
return dev_name ? dev_name : "pinctrl-merrifield";
}
static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
const struct mrfld_gpio_pinrange *range;
const char *pinctrl_dev_name;
struct mrfld_gpio *priv;
u32 gpio_base, irq_base;
void __iomem *base;
@ -439,10 +447,11 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
return retval;
}
pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name();
for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
range = &mrfld_gpio_ranges[i];
retval = gpiochip_add_pin_range(&priv->chip,
"pinctrl-merrifield",
pinctrl_dev_name,
range->gpio_base,
range->pin_base,
range->npins);

37
drivers/iio/adc/Kconfig
View File

@ -629,6 +629,18 @@ config SPEAR_ADC
To compile this driver as a module, choose M here: the
module will be called spear_adc.
config SD_ADC_MODULATOR
tristate "Generic sigma delta modulator"
depends on OF
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Select this option to enables sigma delta modulator. This driver can
support generic sigma delta modulators.
This driver can also be built as a module. If so, the module
will be called sd_adc_modulator.
config STM32_ADC_CORE
tristate "STMicroelectronics STM32 adc core"
depends on ARCH_STM32 || COMPILE_TEST
@ -656,6 +668,31 @@ config STM32_ADC
This driver can also be built as a module. If so, the module
will be called stm32-adc.
config STM32_DFSDM_CORE
tristate "STMicroelectronics STM32 DFSDM core"
depends on (ARCH_STM32 && OF) || COMPILE_TEST
select REGMAP
select REGMAP_MMIO
help
Select this option to enable the driver for STMicroelectronics
STM32 digital filter for sigma delta converter.
This driver can also be built as a module. If so, the module
will be called stm32-dfsdm-core.
config STM32_DFSDM_ADC
tristate "STMicroelectronics STM32 dfsdm adc"
depends on (ARCH_STM32 && OF) || COMPILE_TEST
select STM32_DFSDM_CORE
select REGMAP_MMIO
select IIO_BUFFER_HW_CONSUMER
help
Select this option to support ADCSigma delta modulator for
STMicroelectronics STM32 digital filter for sigma delta converter.
This driver can also be built as a module. If so, the module
will be called stm32-dfsdm-adc.
config STX104
tristate "Apex Embedded Systems STX104 driver"
depends on PC104 && X86 && ISA_BUS_API

3
drivers/iio/adc/Makefile
View File

@ -64,6 +64,8 @@ obj-$(CONFIG_STX104) += stx104.o
obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o
obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
obj-$(CONFIG_STM32_ADC) += stm32-adc.o
obj-$(CONFIG_STM32_DFSDM_CORE) += stm32-dfsdm-core.o
obj-$(CONFIG_STM32_DFSDM_ADC) += stm32-dfsdm-adc.o
obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o
@ -82,3 +84,4 @@ obj-$(CONFIG_VF610_ADC) += vf610_adc.o
obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o
xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o
obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o
obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o

68
drivers/iio/adc/sd_adc_modulator.c Normal file
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@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Generic sigma delta modulator driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
*/
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/module.h>
#include <linux/of_device.h>
static const struct iio_info iio_sd_mod_iio_info;
static const struct iio_chan_spec iio_sd_mod_ch = {
.type = IIO_VOLTAGE,
.indexed = 1,
.scan_type = {
.sign = 'u',
.realbits = 1,
.shift = 0,
},
};
static int iio_sd_mod_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *iio;
iio = devm_iio_device_alloc(dev, 0);
if (!iio)
return -ENOMEM;
iio->dev.parent = dev;
iio->dev.of_node = dev->of_node;
iio->name = dev_name(dev);
iio->info = &iio_sd_mod_iio_info;
iio->modes = INDIO_BUFFER_HARDWARE;
iio->num_channels = 1;
iio->channels = &iio_sd_mod_ch;
platform_set_drvdata(pdev, iio);
return devm_iio_device_register(&pdev->dev, iio);
}
static const struct of_device_id sd_adc_of_match[] = {
{ .compatible = "sd-modulator" },
{ .compatible = "ads1201" },
{ }
};
MODULE_DEVICE_TABLE(of, sd_adc_of_match);
static struct platform_driver iio_sd_mod_adc = {
.driver = {
.name = "iio_sd_adc_mod",
.of_match_table = of_match_ptr(sd_adc_of_match),
},
.probe = iio_sd_mod_probe,
};
module_platform_driver(iio_sd_mod_adc);
MODULE_DESCRIPTION("Basic sigma delta modulator");
MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
MODULE_LICENSE("GPL v2");

1205
drivers/iio/adc/stm32-dfsdm-adc.c Normal file
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File diff suppressed because it is too large Load Diff

302
drivers/iio/adc/stm32-dfsdm-core.c Normal file
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@ -0,0 +1,302 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file is part the core part STM32 DFSDM driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
*/
#include <linux/clk.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "stm32-dfsdm.h"
struct stm32_dfsdm_dev_data {
unsigned int num_filters;
unsigned int num_channels;
const struct regmap_config *regmap_cfg;
};
#define STM32H7_DFSDM_NUM_FILTERS 4
#define STM32H7_DFSDM_NUM_CHANNELS 8
static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg < DFSDM_FILTER_BASE_ADR)
return false;
/*
* Mask is done on register to avoid to list registers of all
* filter instances.
*/
switch (reg & DFSDM_FILTER_REG_MASK) {
case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
return true;
}
return false;
}
static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = sizeof(u32),
.max_register = 0x2B8,
.volatile_reg = stm32_dfsdm_volatile_reg,
.fast_io = true,
};
static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
.num_filters = STM32H7_DFSDM_NUM_FILTERS,
.num_channels = STM32H7_DFSDM_NUM_CHANNELS,
.regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
};
struct dfsdm_priv {
struct platform_device *pdev; /* platform device */
struct stm32_dfsdm dfsdm; /* common data exported for all instances */
unsigned int spi_clk_out_div; /* SPI clkout divider value */
atomic_t n_active_ch; /* number of current active channels */
struct clk *clk; /* DFSDM clock */
struct clk *aclk; /* audio clock */
};
/**
* stm32_dfsdm_start_dfsdm - start global dfsdm interface.
*
* Enable interface if n_active_ch is not null.
* @dfsdm: Handle used to retrieve dfsdm context.
*/
int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
struct device *dev = &priv->pdev->dev;
unsigned int clk_div = priv->spi_clk_out_div;
int ret;
if (atomic_inc_return(&priv->n_active_ch) == 1) {
ret = clk_prepare_enable(priv->clk);
if (ret < 0) {
dev_err(dev, "Failed to start clock\n");
goto error_ret;
}
if (priv->aclk) {
ret = clk_prepare_enable(priv->aclk);
if (ret < 0) {
dev_err(dev, "Failed to start audio clock\n");
goto disable_clk;
}
}
/* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_CKOUTDIV_MASK,
DFSDM_CHCFGR1_CKOUTDIV(clk_div));
if (ret < 0)
goto disable_aclk;
/* Global enable of DFSDM interface */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_DFSDMEN_MASK,
DFSDM_CHCFGR1_DFSDMEN(1));
if (ret < 0)
goto disable_aclk;
}
dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
atomic_read(&priv->n_active_ch));
return 0;
disable_aclk:
clk_disable_unprepare(priv->aclk);
disable_clk:
clk_disable_unprepare(priv->clk);
error_ret:
atomic_dec(&priv->n_active_ch);
return ret;
}
EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
/**
* stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
*
* Disable interface if n_active_ch is null
* @dfsdm: Handle used to retrieve dfsdm context.
*/
int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
int ret;
if (atomic_dec_and_test(&priv->n_active_ch)) {
/* Global disable of DFSDM interface */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_DFSDMEN_MASK,
DFSDM_CHCFGR1_DFSDMEN(0));
if (ret < 0)
return ret;
/* Stop SPI CLKOUT */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_CKOUTDIV_MASK,
DFSDM_CHCFGR1_CKOUTDIV(0));
if (ret < 0)
return ret;
clk_disable_unprepare(priv->clk);
if (priv->aclk)
clk_disable_unprepare(priv->aclk);
}
dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
atomic_read(&priv->n_active_ch));
return 0;
}
EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
static int stm32_dfsdm_parse_of(struct platform_device *pdev,
struct dfsdm_priv *priv)
{
struct device_node *node = pdev->dev.of_node;
struct resource *res;
unsigned long clk_freq;
unsigned int spi_freq, rem;
int ret;
if (!node)
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Failed to get memory resource\n");
return -ENODEV;
}
priv->dfsdm.phys_base = res->start;
priv->dfsdm.base = devm_ioremap_resource(&pdev->dev, res);
/*
* "dfsdm" clock is mandatory for DFSDM peripheral clocking.
* "dfsdm" or "audio" clocks can be used as source clock for
* the SPI clock out signal and internal processing, depending
* on use case.
*/
priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "No stm32_dfsdm_clk clock found\n");
return -EINVAL;
}
priv->aclk = devm_clk_get(&pdev->dev, "audio");
if (IS_ERR(priv->aclk))
priv->aclk = NULL;
if (priv->aclk)
clk_freq = clk_get_rate(priv->aclk);
else
clk_freq = clk_get_rate(priv->clk);
/* SPI clock out frequency */
ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
&spi_freq);
if (ret < 0) {
/* No SPI master mode */
return 0;
}
priv->spi_clk_out_div = div_u64_rem(clk_freq, spi_freq, &rem) - 1;
priv->dfsdm.spi_master_freq = spi_freq;
if (rem) {
dev_warn(&pdev->dev, "SPI clock not accurate\n");
dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
}
return 0;
};
static const struct of_device_id stm32_dfsdm_of_match[] = {
{
.compatible = "st,stm32h7-dfsdm",
.data = &stm32h7_dfsdm_data,
},
{}
};
MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
static int stm32_dfsdm_probe(struct platform_device *pdev)
{
struct dfsdm_priv *priv;
const struct stm32_dfsdm_dev_data *dev_data;
struct stm32_dfsdm *dfsdm;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->pdev = pdev;
dev_data = of_device_get_match_data(&pdev->dev);
dfsdm = &priv->dfsdm;
dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
sizeof(*dfsdm->fl_list), GFP_KERNEL);
if (!dfsdm->fl_list)
return -ENOMEM;
dfsdm->num_fls = dev_data->num_filters;
dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
sizeof(*dfsdm->ch_list),
GFP_KERNEL);
if (!dfsdm->ch_list)
return -ENOMEM;
dfsdm->num_chs = dev_data->num_channels;
ret = stm32_dfsdm_parse_of(pdev, priv);
if (ret < 0)
return ret;
dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
dfsdm->base,
&stm32h7_dfsdm_regmap_cfg);
if (IS_ERR(dfsdm->regmap)) {
ret = PTR_ERR(dfsdm->regmap);
dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
__func__, ret);
return ret;
}
platform_set_drvdata(pdev, dfsdm);
return devm_of_platform_populate(&pdev->dev);
}
static struct platform_driver stm32_dfsdm_driver = {
.probe = stm32_dfsdm_probe,
.driver = {
.name = "stm32-dfsdm",
.of_match_table = stm32_dfsdm_of_match,
},
};
module_platform_driver(stm32_dfsdm_driver);
MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
MODULE_LICENSE("GPL v2");

310
drivers/iio/adc/stm32-dfsdm.h Normal file
View File

@ -0,0 +1,310 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This file is part of STM32 DFSDM driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.
*/
#ifndef MDF_STM32_DFSDM__H
#define MDF_STM32_DFSDM__H
#include <linux/bitfield.h>
/*
* STM32 DFSDM - global register map
* ________________________________________________________
* | Offset | Registers block |
* --------------------------------------------------------
* | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
* --------------------------------------------------------
* | 0x020 | CHANNEL 1 |
* --------------------------------------------------------
* | ... | ..... |
* --------------------------------------------------------
* | 0x0E0 | CHANNEL 7 |
* --------------------------------------------------------
* | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
* --------------------------------------------------------
* | 0x200 | FILTER 1 |
* --------------------------------------------------------
* | 0x300 | FILTER 2 |
* --------------------------------------------------------
* | 0x400 | FILTER 3 |
* --------------------------------------------------------
*/
/*
* Channels register definitions
*/
#define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
#define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
#define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
#define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C)
#define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)
/* CHCFGR1: Channel configuration register 1 */
#define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)
#define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
#define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
#define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
#define DFSDM_CHCFGR1_SCDEN_MASK BIT(5)
#define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
#define DFSDM_CHCFGR1_CKABEN_MASK BIT(6)
#define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
#define DFSDM_CHCFGR1_CHEN_MASK BIT(7)
#define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
#define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8)
#define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
#define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)
#define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
#define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
#define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
#define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
#define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
#define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)
#define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
#define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31)
#define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
/* CHCFGR2: Channel configuration register 2 */
#define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)
#define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
#define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)
#define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
/* AWSCDR: Channel analog watchdog and short circuit detector */
#define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)
#define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
#define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)
#define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
#define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)
#define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
#define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)
#define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
/*
* Filters register definitions
*/
#define DFSDM_FILTER_BASE_ADR 0x100
#define DFSDM_FILTER_REG_MASK 0x7F
#define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)
#define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00)
#define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04)
#define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08)
#define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C)
#define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10)
#define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14)
#define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18)
#define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C)
#define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20)
#define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24)
#define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28)
#define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C)
#define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30)
#define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34)
#define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38)
/* CR1 Control register 1 */
#define DFSDM_CR1_DFEN_MASK BIT(0)
#define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
#define DFSDM_CR1_JSWSTART_MASK BIT(1)
#define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
#define DFSDM_CR1_JSYNC_MASK BIT(3)
#define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
#define DFSDM_CR1_JSCAN_MASK BIT(4)
#define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
#define DFSDM_CR1_JDMAEN_MASK BIT(5)
#define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
#define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)
#define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
#define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)
#define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
#define DFSDM_CR1_RSWSTART_MASK BIT(17)
#define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
#define DFSDM_CR1_RCONT_MASK BIT(18)
#define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
#define DFSDM_CR1_RSYNC_MASK BIT(19)
#define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
#define DFSDM_CR1_RDMAEN_MASK BIT(21)
#define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
#define DFSDM_CR1_RCH_MASK GENMASK(26, 24)
#define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
#define DFSDM_CR1_FAST_MASK BIT(29)
#define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
#define DFSDM_CR1_AWFSEL_MASK BIT(30)
#define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
/* CR2: Control register 2 */
#define DFSDM_CR2_IE_MASK GENMASK(6, 0)
#define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
#define DFSDM_CR2_JEOCIE_MASK BIT(0)
#define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
#define DFSDM_CR2_REOCIE_MASK BIT(1)
#define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
#define DFSDM_CR2_JOVRIE_MASK BIT(2)
#define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
#define DFSDM_CR2_ROVRIE_MASK BIT(3)
#define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
#define DFSDM_CR2_AWDIE_MASK BIT(4)
#define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
#define DFSDM_CR2_SCDIE_MASK BIT(5)
#define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
#define DFSDM_CR2_CKABIE_MASK BIT(6)
#define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
#define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)
#define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
#define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)
#define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
/* ISR: Interrupt status register */
#define DFSDM_ISR_JEOCF_MASK BIT(0)
#define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
#define DFSDM_ISR_REOCF_MASK BIT(1)
#define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
#define DFSDM_ISR_JOVRF_MASK BIT(2)
#define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
#define DFSDM_ISR_ROVRF_MASK BIT(3)
#define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
#define DFSDM_ISR_AWDF_MASK BIT(4)
#define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
#define DFSDM_ISR_JCIP_MASK BIT(13)
#define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
#define DFSDM_ISR_RCIP_MASK BIT(14)
#define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
#define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)
#define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
#define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)
#define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
/* ICR: Interrupt flag clear register */
#define DFSDM_ICR_CLRJOVRF_MASK BIT(2)
#define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
#define DFSDM_ICR_CLRROVRF_MASK BIT(3)
#define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
#define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)
#define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
#define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))
#define DFSDM_ICR_CLRCKABF_CH(v, y) \
(((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
#define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)
#define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
#define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y))
#define DFSDM_ICR_CLRSCDF_CH(v, y) \
(((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
/* FCR: Filter control register */
#define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)
#define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
#define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)
#define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
#define DFSDM_FCR_FORD_MASK GENMASK(31, 29)
#define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
/* RDATAR: Filter data register for regular channel */
#define DFSDM_DATAR_CH_MASK GENMASK(2, 0)
#define DFSDM_DATAR_DATA_OFFSET 8
#define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
/* AWLTR: Filter analog watchdog low threshold register */
#define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)
#define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
#define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)
#define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
/* AWHTR: Filter analog watchdog low threshold register */
#define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)
#define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
#define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)
#define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
/* AWSR: Filter watchdog status register */
#define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)
#define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
#define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)
#define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
/* AWCFR: Filter watchdog status register */
#define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)
#define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
#define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)
#define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
/* DFSDM filter order */
enum stm32_dfsdm_sinc_order {
DFSDM_FASTSINC_ORDER, /* FastSinc filter type */
DFSDM_SINC1_ORDER, /* Sinc 1 filter type */
DFSDM_SINC2_ORDER, /* Sinc 2 filter type */
DFSDM_SINC3_ORDER, /* Sinc 3 filter type */
DFSDM_SINC4_ORDER, /* Sinc 4 filter type (N.A. for watchdog) */
DFSDM_SINC5_ORDER, /* Sinc 5 filter type (N.A. for watchdog) */
DFSDM_NB_SINC_ORDER,
};
/**
* struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter
* @iosr: integrator oversampling
* @fosr: filter oversampling
* @ford: filter order
* @res: output sample resolution
* @sync_mode: filter synchronized with filter 0
* @fast: filter fast mode
*/
struct stm32_dfsdm_filter {
unsigned int iosr;
unsigned int fosr;
enum stm32_dfsdm_sinc_order ford;
u64 res;
unsigned int sync_mode;
unsigned int fast;
};
/**
* struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel
* @id: id of the channel
* @type: interface type linked to stm32_dfsdm_chan_type
* @src: interface type linked to stm32_dfsdm_chan_src
* @alt_si: alternative serial input interface
*/
struct stm32_dfsdm_channel {
unsigned int id;
unsigned int type;
unsigned int src;
unsigned int alt_si;
};
/**
* struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances)
* @base: control registers base cpu addr
* @phys_base: DFSDM IP register physical address
* @regmap: regmap for register read/write
* @fl_list: filter resources list
* @num_fls: number of filter resources available
* @ch_list: channel resources list
* @num_chs: number of channel resources available
* @spi_master_freq: SPI clock out frequency
*/
struct stm32_dfsdm {
void __iomem *base;
phys_addr_t phys_base;
struct regmap *regmap;
struct stm32_dfsdm_filter *fl_list;
unsigned int num_fls;
struct stm32_dfsdm_channel *ch_list;
unsigned int num_chs;
unsigned int spi_master_freq;
};
/* DFSDM channel serial spi clock source */
enum stm32_dfsdm_spi_clk_src {
DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,
DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,
DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,
DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
};
int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);
int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);
#endif

10
drivers/iio/buffer/Kconfig
View File

@ -29,6 +29,16 @@ config IIO_BUFFER_DMAENGINE
Should be selected by drivers that want to use this functionality.
config IIO_BUFFER_HW_CONSUMER
tristate "Industrial I/O HW buffering"
help
Provides a way to bonding when an IIO device has a direct connection
to another device in hardware. In this case buffers for data transfers
are handled by hardware.
Should be selected by drivers that want to use the generic Hw consumer
interface.
config IIO_KFIFO_BUF
tristate "Industrial I/O buffering based on kfifo"
help

1
drivers/iio/buffer/Makefile
View File

@ -7,5 +7,6 @@
obj-$(CONFIG_IIO_BUFFER_CB) += industrialio-buffer-cb.o
obj-$(CONFIG_IIO_BUFFER_DMA) += industrialio-buffer-dma.o
obj-$(CONFIG_IIO_BUFFER_DMAENGINE) += industrialio-buffer-dmaengine.o
obj-$(CONFIG_IIO_BUFFER_HW_CONSUMER) += industrialio-hw-consumer.o
obj-$(CONFIG_IIO_TRIGGERED_BUFFER) += industrialio-triggered-buffer.o
obj-$(CONFIG_IIO_KFIFO_BUF) += kfifo_buf.o

11
drivers/iio/buffer/industrialio-buffer-cb.c
View File

@ -104,6 +104,17 @@ error_free_cb_buff:
}
EXPORT_SYMBOL_GPL(iio_channel_get_all_cb);
int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buff,
size_t watermark)
{
if (!watermark)
return -EINVAL;
cb_buff->buffer.watermark = watermark;
return 0;
}
EXPORT_SYMBOL_GPL(iio_channel_cb_set_buffer_watermark);
int iio_channel_start_all_cb(struct iio_cb_buffer *cb_buff)
{
return iio_update_buffers(cb_buff->indio_dev, &cb_buff->buffer,

247
drivers/iio/buffer/industrialio-hw-consumer.c Normal file
View File

@ -0,0 +1,247 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2017 Analog Devices Inc.
* Author: Lars-Peter Clausen <lars@metafoo.de>
*/
#include <linux/err.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/consumer.h>
#include <linux/iio/hw-consumer.h>
#include <linux/iio/buffer_impl.h>
/**
* struct iio_hw_consumer - IIO hw consumer block
* @buffers: hardware buffers list head.
* @channels: IIO provider channels.
*/
struct iio_hw_consumer {
struct list_head buffers;
struct iio_channel *channels;
};
struct hw_consumer_buffer {
struct list_head head;
struct iio_dev *indio_dev;
struct iio_buffer buffer;
long scan_mask[];
};
static struct hw_consumer_buffer *iio_buffer_to_hw_consumer_buffer(
struct iio_buffer *buffer)
{
return container_of(buffer, struct hw_consumer_buffer, buffer);
}
static void iio_hw_buf_release(struct iio_buffer *buffer)
{
struct hw_consumer_buffer *hw_buf =
iio_buffer_to_hw_consumer_buffer(buffer);
kfree(hw_buf);
}
static const struct iio_buffer_access_funcs iio_hw_buf_access = {
.release = &iio_hw_buf_release,
.modes = INDIO_BUFFER_HARDWARE,
};
static struct hw_consumer_buffer *iio_hw_consumer_get_buffer(
struct iio_hw_consumer *hwc, struct iio_dev *indio_dev)
{
size_t mask_size = BITS_TO_LONGS(indio_dev->masklength) * sizeof(long);
struct hw_consumer_buffer *buf;
list_for_each_entry(buf, &hwc->buffers, head) {
if (buf->indio_dev == indio_dev)
return buf;
}
buf = kzalloc(sizeof(*buf) + mask_size, GFP_KERNEL);
if (!buf)
return NULL;
buf->buffer.access = &iio_hw_buf_access;
buf->indio_dev = indio_dev;
buf->buffer.scan_mask = buf->scan_mask;
iio_buffer_init(&buf->buffer);
list_add_tail(&buf->head, &hwc->buffers);
return buf;
}
/**
* iio_hw_consumer_alloc() - Allocate IIO hardware consumer
* @dev: Pointer to consumer device.
*
* Returns a valid iio_hw_consumer on success or a ERR_PTR() on failure.
*/
struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev)
{
struct hw_consumer_buffer *buf;
struct iio_hw_consumer *hwc;
struct iio_channel *chan;
int ret;
hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
if (!hwc)
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(&hwc->buffers);
hwc->channels = iio_channel_get_all(dev);
if (IS_ERR(hwc->channels)) {
ret = PTR_ERR(hwc->channels);
goto err_free_hwc;
}
chan = &hwc->channels[0];
while (chan->indio_dev) {
buf = iio_hw_consumer_get_buffer(hwc, chan->indio_dev);
if (!buf) {
ret = -ENOMEM;
goto err_put_buffers;
}
set_bit(chan->channel->scan_index, buf->buffer.scan_mask);
chan++;
}
return hwc;
err_put_buffers:
list_for_each_entry(buf, &hwc->buffers, head)
iio_buffer_put(&buf->buffer);
iio_channel_release_all(hwc->channels);
err_free_hwc:
kfree(hwc);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_alloc);
/**
* iio_hw_consumer_free() - Free IIO hardware consumer
* @hwc: hw consumer to free.
*/
void iio_hw_consumer_free(struct iio_hw_consumer *hwc)
{
struct hw_consumer_buffer *buf, *n;
iio_channel_release_all(hwc->channels);
list_for_each_entry_safe(buf, n, &hwc->buffers, head)
iio_buffer_put(&buf->buffer);
kfree(hwc);
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_free);
static void devm_iio_hw_consumer_release(struct device *dev, void *res)
{
iio_hw_consumer_free(*(struct iio_hw_consumer **)res);
}
static int devm_iio_hw_consumer_match(struct device *dev, void *res, void *data)
{
struct iio_hw_consumer **r = res;
if (!r || !*r) {
WARN_ON(!r || !*r);
return 0;
}
return *r == data;
}
/**
* devm_iio_hw_consumer_alloc - Resource-managed iio_hw_consumer_alloc()
* @dev: Pointer to consumer device.
*
* Managed iio_hw_consumer_alloc. iio_hw_consumer allocated with this function
* is automatically freed on driver detach.
*
* If an iio_hw_consumer allocated with this function needs to be freed
* separately, devm_iio_hw_consumer_free() must be used.
*
* returns pointer to allocated iio_hw_consumer on success, NULL on failure.
*/
struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev)
{
struct iio_hw_consumer **ptr, *iio_hwc;
ptr = devres_alloc(devm_iio_hw_consumer_release, sizeof(*ptr),
GFP_KERNEL);
if (!ptr)
return NULL;
iio_hwc = iio_hw_consumer_alloc(dev);
if (IS_ERR(iio_hwc)) {
devres_free(ptr);
} else {
*ptr = iio_hwc;
devres_add(dev, ptr);
}
return iio_hwc;
}
EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_alloc);
/**
* devm_iio_hw_consumer_free - Resource-managed iio_hw_consumer_free()
* @dev: Pointer to consumer device.
* @hwc: iio_hw_consumer to free.
*
* Free iio_hw_consumer allocated with devm_iio_hw_consumer_alloc().
*/
void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc)
{
int rc;
rc = devres_release(dev, devm_iio_hw_consumer_release,
devm_iio_hw_consumer_match, hwc);
WARN_ON(rc);
}
EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_free);
/**
* iio_hw_consumer_enable() - Enable IIO hardware consumer
* @hwc: iio_hw_consumer to enable.
*
* Returns 0 on success.
*/
int iio_hw_consumer_enable(struct iio_hw_consumer *hwc)
{
struct hw_consumer_buffer *buf;
int ret;
list_for_each_entry(buf, &hwc->buffers, head) {
ret = iio_update_buffers(buf->indio_dev, &buf->buffer, NULL);
if (ret)
goto err_disable_buffers;
}
return 0;
err_disable_buffers:
list_for_each_entry_continue_reverse(buf, &hwc->buffers, head)
iio_update_buffers(buf->indio_dev, NULL, &buf->buffer);
return ret;
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_enable);
/**
* iio_hw_consumer_disable() - Disable IIO hardware consumer
* @hwc: iio_hw_consumer to disable.
*/
void iio_hw_consumer_disable(struct iio_hw_consumer *hwc)
{
struct hw_consumer_buffer *buf;
list_for_each_entry(buf, &hwc->buffers, head)
iio_update_buffers(buf->indio_dev, NULL, &buf->buffer);
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_disable);
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Hardware consumer buffer the IIO framework");
MODULE_LICENSE("GPL v2");

17
drivers/iio/inkern.c
View File

@ -664,9 +664,8 @@ err_unlock:
}
EXPORT_SYMBOL_GPL(iio_convert_raw_to_processed);
static int iio_read_channel_attribute(struct iio_channel *chan,
int *val, int *val2,
enum iio_chan_info_enum attribute)
int iio_read_channel_attribute(struct iio_channel *chan, int *val, int *val2,
enum iio_chan_info_enum attribute)
{
int ret;
@ -682,6 +681,7 @@ err_unlock:
return ret;
}
EXPORT_SYMBOL_GPL(iio_read_channel_attribute);
int iio_read_channel_offset(struct iio_channel *chan, int *val, int *val2)
{
@ -850,7 +850,8 @@ static int iio_channel_write(struct iio_channel *chan, int val, int val2,
chan->channel, val, val2, info);
}
int iio_write_channel_raw(struct iio_channel *chan, int val)
int iio_write_channel_attribute(struct iio_channel *chan, int val, int val2,
enum iio_chan_info_enum attribute)
{
int ret;
@ -860,12 +861,18 @@ int iio_write_channel_raw(struct iio_channel *chan, int val)
goto err_unlock;
}
ret = iio_channel_write(chan, val, 0, IIO_CHAN_INFO_RAW);
ret = iio_channel_write(chan, val, val2, attribute);
err_unlock:
mutex_unlock(&chan->indio_dev->info_exist_lock);
return ret;
}
EXPORT_SYMBOL_GPL(iio_write_channel_attribute);
int iio_write_channel_raw(struct iio_channel *chan, int val)
{
return iio_write_channel_attribute(chan, val, 0, IIO_CHAN_INFO_RAW);
}
EXPORT_SYMBOL_GPL(iio_write_channel_raw);
unsigned int iio_get_channel_ext_info_count(struct iio_channel *chan)

3
include/acpi/acpi_bus.h
View File

@ -91,6 +91,9 @@ acpi_evaluate_dsm_typed(acpi_handle handle, const guid_t *guid, u64 rev,
bool acpi_dev_found(const char *hid);
bool acpi_dev_present(const char *hid, const char *uid, s64 hrv);
const char *
acpi_dev_get_first_match_name(const char *hid, const char *uid, s64 hrv);
#ifdef CONFIG_ACPI
#include <linux/proc_fs.h>

6
include/linux/acpi.h
View File

@ -640,6 +640,12 @@ static inline bool acpi_dev_present(const char *hid, const char *uid, s64 hrv)
return false;
}
static inline const char *
acpi_dev_get_first_match_name(const char *hid, const char *uid, s64 hrv)
{
return NULL;
}
static inline bool is_acpi_node(struct fwnode_handle *fwnode)
{
return false;

18
include/linux/iio/adc/stm32-dfsdm-adc.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This file discribe the STM32 DFSDM IIO driver API for audio part
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.
*/
#ifndef STM32_DFSDM_ADC_H
#define STM32_DFSDM_ADC_H
int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
int (*cb)(const void *data, size_t size,
void *private),
void *private);
int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev);
#endif

37
include/linux/iio/consumer.h
View File

@ -133,6 +133,17 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
int (*cb)(const void *data,
void *private),
void *private);
/**
* iio_channel_cb_set_buffer_watermark() - set the buffer watermark.
* @cb_buffer: The callback buffer from whom we want the channel
* information.
* @watermark: buffer watermark in bytes.
*
* This function allows to configure the buffer watermark.
*/
int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buffer,
size_t watermark);
/**
* iio_channel_release_all_cb() - release and unregister the callback.
* @cb_buffer: The callback buffer that was allocated.
@ -215,6 +226,32 @@ int iio_read_channel_average_raw(struct iio_channel *chan, int *val);
*/
int iio_read_channel_processed(struct iio_channel *chan, int *val);
/**
* iio_write_channel_attribute() - Write values to the device attribute.
* @chan: The channel being queried.
* @val: Value being written.
* @val2: Value being written.val2 use depends on attribute type.
* @attribute: info attribute to be read.
*
* Returns an error code or 0.
*/
int iio_write_channel_attribute(struct iio_channel *chan, int val,
int val2, enum iio_chan_info_enum attribute);
/**
* iio_read_channel_attribute() - Read values from the device attribute.
* @chan: The channel being queried.
* @val: Value being written.
* @val2: Value being written.Val2 use depends on attribute type.
* @attribute: info attribute to be written.
*
* Returns an error code if failed. Else returns a description of what is in val
* and val2, such as IIO_VAL_INT_PLUS_MICRO telling us we have a value of val
* + val2/1e6
*/
int iio_read_channel_attribute(struct iio_channel *chan, int *val,
int *val2, enum iio_chan_info_enum attribute);
/**
* iio_write_channel_raw() - write to a given channel
* @chan: The channel being queried.

21
include/linux/iio/hw-consumer.h Normal file
View File

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Industrial I/O in kernel hardware consumer interface
*
* Copyright 2017 Analog Devices Inc.
* Author: Lars-Peter Clausen <lars@metafoo.de>
*/
#ifndef LINUX_IIO_HW_CONSUMER_H
#define LINUX_IIO_HW_CONSUMER_H
struct iio_hw_consumer;
struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev);
void iio_hw_consumer_free(struct iio_hw_consumer *hwc);
struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev);
void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc);
int iio_hw_consumer_enable(struct iio_hw_consumer *hwc);
void iio_hw_consumer_disable(struct iio_hw_consumer *hwc);
#endif

28
include/linux/iio/iio.h
View File

@ -20,34 +20,6 @@
* Currently assumes nano seconds.
*/
enum iio_chan_info_enum {
IIO_CHAN_INFO_RAW = 0,
IIO_CHAN_INFO_PROCESSED,
IIO_CHAN_INFO_SCALE,
IIO_CHAN_INFO_OFFSET,
IIO_CHAN_INFO_CALIBSCALE,
IIO_CHAN_INFO_CALIBBIAS,
IIO_CHAN_INFO_PEAK,
IIO_CHAN_INFO_PEAK_SCALE,
IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW,
IIO_CHAN_INFO_AVERAGE_RAW,
IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_SAMP_FREQ,
IIO_CHAN_INFO_FREQUENCY,
IIO_CHAN_INFO_PHASE,
IIO_CHAN_INFO_HARDWAREGAIN,
IIO_CHAN_INFO_HYSTERESIS,
IIO_CHAN_INFO_INT_TIME,
IIO_CHAN_INFO_ENABLE,
IIO_CHAN_INFO_CALIBHEIGHT,
IIO_CHAN_INFO_CALIBWEIGHT,
IIO_CHAN_INFO_DEBOUNCE_COUNT,
IIO_CHAN_INFO_DEBOUNCE_TIME,
IIO_CHAN_INFO_CALIBEMISSIVITY,
IIO_CHAN_INFO_OVERSAMPLING_RATIO,
};
enum iio_shared_by {
IIO_SEPARATE,
IIO_SHARED_BY_TYPE,

28
include/linux/iio/types.h
View File

@ -34,4 +34,32 @@ enum iio_available_type {
IIO_AVAIL_RANGE,
};
enum iio_chan_info_enum {
IIO_CHAN_INFO_RAW = 0,
IIO_CHAN_INFO_PROCESSED,
IIO_CHAN_INFO_SCALE,
IIO_CHAN_INFO_OFFSET,
IIO_CHAN_INFO_CALIBSCALE,
IIO_CHAN_INFO_CALIBBIAS,
IIO_CHAN_INFO_PEAK,
IIO_CHAN_INFO_PEAK_SCALE,
IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW,
IIO_CHAN_INFO_AVERAGE_RAW,
IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_SAMP_FREQ,
IIO_CHAN_INFO_FREQUENCY,
IIO_CHAN_INFO_PHASE,
IIO_CHAN_INFO_HARDWAREGAIN,
IIO_CHAN_INFO_HYSTERESIS,
IIO_CHAN_INFO_INT_TIME,
IIO_CHAN_INFO_ENABLE,
IIO_CHAN_INFO_CALIBHEIGHT,
IIO_CHAN_INFO_CALIBWEIGHT,
IIO_CHAN_INFO_DEBOUNCE_COUNT,
IIO_CHAN_INFO_DEBOUNCE_TIME,
IIO_CHAN_INFO_CALIBEMISSIVITY,
IIO_CHAN_INFO_OVERSAMPLING_RATIO,
};
#endif /* _IIO_TYPES_H_ */

2
include/linux/sound.h
View File

@ -12,11 +12,9 @@ struct device;
extern int register_sound_special(const struct file_operations *fops, int unit);
extern int register_sound_special_device(const struct file_operations *fops, int unit, struct device *dev);
extern int register_sound_mixer(const struct file_operations *fops, int dev);
extern int register_sound_midi(const struct file_operations *fops, int dev);
extern int register_sound_dsp(const struct file_operations *fops, int dev);
extern void unregister_sound_special(int unit);
extern void unregister_sound_mixer(int unit);
extern void unregister_sound_midi(int unit);
extern void unregister_sound_dsp(int unit);
#endif /* _LINUX_SOUND_H */

4
include/sound/hdaudio_ext.h
View File

@ -193,7 +193,7 @@ struct hda_dai_map {
* @pvt_data - private data, for asoc contains asoc codec object
*/
struct hdac_ext_device {
struct hdac_device hdac;
struct hdac_device hdev;
struct hdac_ext_bus *ebus;
/* soc-dai to nid map */
@ -213,7 +213,7 @@ struct hdac_ext_dma_params {
u8 stream_tag;
};
#define to_ehdac_device(dev) (container_of((dev), \
struct hdac_ext_device, hdac))
struct hdac_ext_device, hdev))
/*
* HD-audio codec base driver
*/

8
include/sound/pcm.h
View File

@ -169,6 +169,10 @@ struct snd_pcm_ops {
#define SNDRV_PCM_FMTBIT_IMA_ADPCM _SNDRV_PCM_FMTBIT(IMA_ADPCM)
#define SNDRV_PCM_FMTBIT_MPEG _SNDRV_PCM_FMTBIT(MPEG)
#define SNDRV_PCM_FMTBIT_GSM _SNDRV_PCM_FMTBIT(GSM)
#define SNDRV_PCM_FMTBIT_S20_LE _SNDRV_PCM_FMTBIT(S20_LE)
#define SNDRV_PCM_FMTBIT_U20_LE _SNDRV_PCM_FMTBIT(U20_LE)
#define SNDRV_PCM_FMTBIT_S20_BE _SNDRV_PCM_FMTBIT(S20_BE)
#define SNDRV_PCM_FMTBIT_U20_BE _SNDRV_PCM_FMTBIT(U20_BE)
#define SNDRV_PCM_FMTBIT_SPECIAL _SNDRV_PCM_FMTBIT(SPECIAL)
#define SNDRV_PCM_FMTBIT_S24_3LE _SNDRV_PCM_FMTBIT(S24_3LE)
#define SNDRV_PCM_FMTBIT_U24_3LE _SNDRV_PCM_FMTBIT(U24_3LE)
@ -202,6 +206,8 @@ struct snd_pcm_ops {
#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_LE
#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_LE
#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_LE
#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_LE
#endif
#ifdef SNDRV_BIG_ENDIAN
#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_BE
@ -213,6 +219,8 @@ struct snd_pcm_ops {
#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_BE
#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_BE
#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE
#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_BE
#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_BE
#endif
struct snd_pcm_file {

2
include/sound/rt5514.h
View File

@ -14,6 +14,8 @@
struct rt5514_platform_data {
unsigned int dmic_init_delay;
const char *dsp_calib_clk_name;
unsigned int dsp_calib_clk_rate;
};
#endif

3
include/sound/rt5645.h
View File

@ -25,6 +25,9 @@ struct rt5645_platform_data {
bool level_trigger_irq;
/* Invert JD1_1 status polarity */
bool inv_jd1_1;
/* Value to asign to snd_soc_card.long_name */
const char *long_name;
};
#endif

1
include/sound/soc-acpi-intel-match.h
View File

@ -16,6 +16,7 @@
#ifndef __LINUX_SND_SOC_ACPI_INTEL_MATCH_H
#define __LINUX_SND_SOC_ACPI_INTEL_MATCH_H
#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/acpi.h>

14
include/sound/soc-acpi.h
View File

@ -17,6 +17,7 @@
#include <linux/stddef.h>
#include <linux/acpi.h>
#include <linux/mod_devicetable.h>
struct snd_soc_acpi_package_context {
char *name; /* package name */
@ -26,17 +27,13 @@ struct snd_soc_acpi_package_context {
bool data_valid;
};
/* codec name is used in DAIs is i2c-<HID>:00 with HID being 8 chars */
#define SND_ACPI_I2C_ID_LEN (4 + ACPI_ID_LEN + 3 + 1)
#if IS_ENABLED(CONFIG_ACPI)
/* translation fron HID to I2C name, needed for DAI codec_name */
const char *snd_soc_acpi_find_name_from_hid(const u8 hid[ACPI_ID_LEN]);
bool snd_soc_acpi_find_package_from_hid(const u8 hid[ACPI_ID_LEN],
struct snd_soc_acpi_package_context *ctx);
#else
static inline const char *
snd_soc_acpi_find_name_from_hid(const u8 hid[ACPI_ID_LEN])
{
return NULL;
}
static inline bool
snd_soc_acpi_find_package_from_hid(const u8 hid[ACPI_ID_LEN],
struct snd_soc_acpi_package_context *ctx)
@ -49,9 +46,6 @@ snd_soc_acpi_find_package_from_hid(const u8 hid[ACPI_ID_LEN],
struct snd_soc_acpi_mach *
snd_soc_acpi_find_machine(struct snd_soc_acpi_mach *machines);
/* acpi check hid */
bool snd_soc_acpi_check_hid(const u8 hid[ACPI_ID_LEN]);
/**
* snd_soc_acpi_mach: ACPI-based machine descriptor. Most of the fields are
* related to the hardware, except for the firmware and topology file names.

5
include/sound/soc-dai.h
View File

@ -102,6 +102,8 @@ struct snd_compr_stream;
SNDRV_PCM_FMTBIT_S16_BE |\
SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S20_3BE |\
SNDRV_PCM_FMTBIT_S20_LE |\
SNDRV_PCM_FMTBIT_S20_BE |\
SNDRV_PCM_FMTBIT_S24_3LE |\
SNDRV_PCM_FMTBIT_S24_3BE |\
SNDRV_PCM_FMTBIT_S32_LE |\
@ -294,9 +296,6 @@ struct snd_soc_dai {
/* DAI runtime info */
unsigned int capture_active:1; /* stream is in use */
unsigned int playback_active:1; /* stream is in use */
unsigned int symmetric_rates:1;
unsigned int symmetric_channels:1;
unsigned int symmetric_samplebits:1;
unsigned int probed:1;
unsigned int active;

9
include/sound/soc.h
View File

@ -494,6 +494,8 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num);
int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num);
#endif
void snd_soc_disconnect_sync(struct device *dev);
struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card,
const char *dai_link, int stream);
struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card,
@ -802,6 +804,9 @@ struct snd_soc_component_driver {
int (*suspend)(struct snd_soc_component *);
int (*resume)(struct snd_soc_component *);
unsigned int (*read)(struct snd_soc_component *, unsigned int);
int (*write)(struct snd_soc_component *, unsigned int, unsigned int);
/* pcm creation and destruction */
int (*pcm_new)(struct snd_soc_pcm_runtime *);
void (*pcm_free)(struct snd_pcm *);
@ -858,12 +863,10 @@ struct snd_soc_component {
struct list_head card_aux_list; /* for auxiliary bound components */
struct list_head card_list;
struct snd_soc_dai_driver *dai_drv;
int num_dai;
const struct snd_soc_component_driver *driver;
struct list_head dai_list;
int num_dai;
int (*read)(struct snd_soc_component *, unsigned int, unsigned int *);
int (*write)(struct snd_soc_component *, unsigned int, unsigned int);

9
include/uapi/sound/asound.h
View File

@ -214,6 +214,11 @@ typedef int __bitwise snd_pcm_format_t;
#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
#define SNDRV_PCM_FORMAT_S20_LE ((__force snd_pcm_format_t) 25) /* in four bytes, LSB justified */
#define SNDRV_PCM_FORMAT_S20_BE ((__force snd_pcm_format_t) 26) /* in four bytes, LSB justified */
#define SNDRV_PCM_FORMAT_U20_LE ((__force snd_pcm_format_t) 27) /* in four bytes, LSB justified */
#define SNDRV_PCM_FORMAT_U20_BE ((__force snd_pcm_format_t) 28) /* in four bytes, LSB justified */
/* gap in the numbering for a future standard linear format */
#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32) /* in three bytes */
#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33) /* in three bytes */
@ -248,6 +253,8 @@ typedef int __bitwise snd_pcm_format_t;
#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_LE
#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_LE
#endif
#ifdef SNDRV_BIG_ENDIAN
#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
@ -259,6 +266,8 @@ typedef int __bitwise snd_pcm_format_t;
#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_BE
#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_BE
#endif
typedef int __bitwise snd_pcm_subformat_t;

17
include/uapi/sound/snd_sst_tokens.h
View File

@ -222,6 +222,17 @@
* %SKL_TKN_MM_U32_NUM_IN_FMT: Number of input formats
* %SKL_TKN_MM_U32_NUM_OUT_FMT: Number of output formats
*
* %SKL_TKN_U32_ASTATE_IDX: Table Index for the A-State entry to be filled
* with kcps and clock source
*
* %SKL_TKN_U32_ASTATE_COUNT: Number of valid entries in A-State table
*
* %SKL_TKN_U32_ASTATE_KCPS: Specifies the core load threshold (in kilo
* cycles per second) below which DSP is clocked
* from source specified by clock source.
*
* %SKL_TKN_U32_ASTATE_CLK_SRC: Clock source for A-State entry
*
* module_id and loadable flags dont have tokens as these values will be
* read from the DSP FW manifest
*
@ -309,7 +320,11 @@ enum SKL_TKNS {
SKL_TKN_MM_U32_NUM_IN_FMT,
SKL_TKN_MM_U32_NUM_OUT_FMT,
SKL_TKN_MAX = SKL_TKN_MM_U32_NUM_OUT_FMT,
SKL_TKN_U32_ASTATE_IDX,
SKL_TKN_U32_ASTATE_COUNT,
SKL_TKN_U32_ASTATE_KCPS,
SKL_TKN_U32_ASTATE_CLK_SRC,
SKL_TKN_MAX = SKL_TKN_U32_ASTATE_CLK_SRC,
};
#endif

12
sound/core/oss/pcm_oss.c
View File

@ -186,7 +186,7 @@ static int _snd_pcm_hw_param_mask(struct snd_pcm_hw_params *params,
{
int changed;
changed = snd_mask_refine(hw_param_mask(params, var), val);
if (changed) {
if (changed > 0) {
params->cmask |= 1 << var;
params->rmask |= 1 << var;
}
@ -233,7 +233,7 @@ static int _snd_pcm_hw_param_min(struct snd_pcm_hw_params *params,
val, open);
else
return -EINVAL;
if (changed) {
if (changed > 0) {
params->cmask |= 1 << var;
params->rmask |= 1 << var;
}
@ -294,7 +294,7 @@ static int _snd_pcm_hw_param_max(struct snd_pcm_hw_params *params,
val, open);
else
return -EINVAL;
if (changed) {
if (changed > 0) {
params->cmask |= 1 << var;
params->rmask |= 1 << var;
}
@ -499,7 +499,7 @@ static int _snd_pcm_hw_param_set(struct snd_pcm_hw_params *params,
}
} else
return -EINVAL;
if (changed) {
if (changed > 0) {
params->cmask |= 1 << var;
params->rmask |= 1 << var;
}
@ -539,7 +539,7 @@ static int _snd_pcm_hw_param_setinteger(struct snd_pcm_hw_params *params,
{
int changed;
changed = snd_interval_setinteger(hw_param_interval(params, var));
if (changed) {
if (changed > 0) {
params->cmask |= 1 << var;
params->rmask |= 1 << var;
}
@ -842,7 +842,7 @@ static int snd_pcm_oss_change_params(struct snd_pcm_substream *substream,
if (!(mutex_trylock(&runtime->oss.params_lock)))
return -EAGAIN;
} else if (mutex_lock_interruptible(&runtime->oss.params_lock))
return -EINTR;
return -ERESTARTSYS;
sw_params = kzalloc(sizeof(*sw_params), GFP_KERNEL);
params = kmalloc(sizeof(*params), GFP_KERNEL);
sparams = kmalloc(sizeof(*sparams), GFP_KERNEL);

4
sound/core/pcm_lib.c
View File

@ -1602,7 +1602,7 @@ static int _snd_pcm_hw_param_first(struct snd_pcm_hw_params *params,
changed = snd_interval_refine_first(hw_param_interval(params, var));
else
return -EINVAL;
if (changed) {
if (changed > 0) {
params->cmask |= 1 << var;
params->rmask |= 1 << var;
}
@ -1648,7 +1648,7 @@ static int _snd_pcm_hw_param_last(struct snd_pcm_hw_params *params,
changed = snd_interval_refine_last(hw_param_interval(params, var));
else
return -EINVAL;
if (changed) {
if (changed > 0) {
params->cmask |= 1 << var;
params->rmask |= 1 << var;
}

19
sound/core/pcm_misc.c
View File

@ -163,13 +163,30 @@ static struct pcm_format_data pcm_formats[(INT)SNDRV_PCM_FORMAT_LAST+1] = {
.width = 32, .phys = 32, .le = 0, .signd = 0,
.silence = { 0x69, 0x69, 0x69, 0x69 },
},
/* FIXME: the following three formats are not defined properly yet */
/* FIXME: the following two formats are not defined properly yet */
[SNDRV_PCM_FORMAT_MPEG] = {
.le = -1, .signd = -1,
},
[SNDRV_PCM_FORMAT_GSM] = {
.le = -1, .signd = -1,
},
[SNDRV_PCM_FORMAT_S20_LE] = {
.width = 20, .phys = 32, .le = 1, .signd = 1,
.silence = {},
},
[SNDRV_PCM_FORMAT_S20_BE] = {
.width = 20, .phys = 32, .le = 0, .signd = 1,
.silence = {},
},
[SNDRV_PCM_FORMAT_U20_LE] = {
.width = 20, .phys = 32, .le = 1, .signd = 0,
.silence = { 0x00, 0x00, 0x08, 0x00 },
},
[SNDRV_PCM_FORMAT_U20_BE] = {
.width = 20, .phys = 32, .le = 0, .signd = 0,
.silence = { 0x00, 0x08, 0x00, 0x00 },
},
/* FIXME: the following format is not defined properly yet */
[SNDRV_PCM_FORMAT_SPECIAL] = {
.le = -1, .signd = -1,
},

2
sound/core/pcm_native.c
View File

@ -3446,7 +3446,7 @@ EXPORT_SYMBOL_GPL(snd_pcm_lib_default_mmap);
int snd_pcm_lib_mmap_iomem(struct snd_pcm_substream *substream,
struct vm_area_struct *area)
{
struct snd_pcm_runtime *runtime = substream->runtime;;
struct snd_pcm_runtime *runtime = substream->runtime;
area->vm_page_prot = pgprot_noncached(area->vm_page_prot);
return vm_iomap_memory(area, runtime->dma_addr, runtime->dma_bytes);

4
sound/core/seq/seq_queue.c
View File

@ -497,9 +497,7 @@ int snd_seq_queue_timer_set_tempo(int queueid, int client,
return -EPERM;
}
result = snd_seq_timer_set_tempo(q->timer, info->tempo);
if (result >= 0)
result = snd_seq_timer_set_ppq(q->timer, info->ppq);
result = snd_seq_timer_set_tempo_ppq(q->timer, info->tempo, info->ppq);
if (result >= 0 && info->skew_base > 0)
result = snd_seq_timer_set_skew(q->timer, info->skew_value,
info->skew_base);

13
sound/core/seq/seq_timer.c
View File

@ -191,14 +191,15 @@ int snd_seq_timer_set_tempo(struct snd_seq_timer * tmr, int tempo)
return 0;
}
/* set current ppq */
int snd_seq_timer_set_ppq(struct snd_seq_timer * tmr, int ppq)
/* set current tempo and ppq in a shot */
int snd_seq_timer_set_tempo_ppq(struct snd_seq_timer *tmr, int tempo, int ppq)
{
int changed;
unsigned long flags;
if (snd_BUG_ON(!tmr))
return -EINVAL;
if (ppq <= 0)
if (tempo <= 0 || ppq <= 0)
return -EINVAL;
spin_lock_irqsave(&tmr->lock, flags);
if (tmr->running && (ppq != tmr->ppq)) {
@ -208,9 +209,11 @@ int snd_seq_timer_set_ppq(struct snd_seq_timer * tmr, int ppq)
pr_debug("ALSA: seq: cannot change ppq of a running timer\n");
return -EBUSY;
}
changed = (tempo != tmr->tempo) || (ppq != tmr->ppq);
tmr->tempo = tempo;
tmr->ppq = ppq;
snd_seq_timer_set_tick_resolution(tmr);
if (changed)
snd_seq_timer_set_tick_resolution(tmr);
spin_unlock_irqrestore(&tmr->lock, flags);
return 0;
}

2
sound/core/seq/seq_timer.h
View File

@ -131,7 +131,7 @@ int snd_seq_timer_stop(struct snd_seq_timer *tmr);
int snd_seq_timer_start(struct snd_seq_timer *tmr);
int snd_seq_timer_continue(struct snd_seq_timer *tmr);
int snd_seq_timer_set_tempo(struct snd_seq_timer *tmr, int tempo);
int snd_seq_timer_set_ppq(struct snd_seq_timer *tmr, int ppq);
int snd_seq_timer_set_tempo_ppq(struct snd_seq_timer *tmr, int tempo, int ppq);
int snd_seq_timer_set_position_tick(struct snd_seq_timer *tmr, snd_seq_tick_time_t position);
int snd_seq_timer_set_position_time(struct snd_seq_timer *tmr, snd_seq_real_time_t position);
int snd_seq_timer_set_skew(struct snd_seq_timer *tmr, unsigned int skew, unsigned int base);

2
sound/drivers/dummy.c
View File

@ -830,7 +830,7 @@ static int snd_dummy_capsrc_put(struct snd_kcontrol *kcontrol, struct snd_ctl_el
static int snd_dummy_iobox_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *info)
{
const char *const names[] = { "None", "CD Player" };
static const char *const names[] = { "None", "CD Player" };
return snd_ctl_enum_info(info, 1, 2, names);
}

2
sound/hda/ext/hdac_ext_bus.c
View File

@ -146,7 +146,7 @@ int snd_hdac_ext_bus_device_init(struct hdac_ext_bus *ebus, int addr)
edev = kzalloc(sizeof(*edev), GFP_KERNEL);
if (!edev)
return -ENOMEM;
hdev = &edev->hdac;
hdev = &edev->hdev;
edev->ebus = ebus;
snprintf(name, sizeof(name), "ehdaudio%dD%d", ebus->idx, addr);

5
sound/isa/gus/gus_dma.c
View File

@ -201,10 +201,9 @@ int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
struct snd_gf1_dma_block *block;
block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
if (block == NULL) {
snd_printk(KERN_ERR "gf1: DMA transfer failure; not enough memory\n");
if (!block)
return -ENOMEM;
}
*block = *__block;
block->next = NULL;

2
sound/mips/hal2.c
View File

@ -814,7 +814,7 @@ static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
struct hpc3_regs *hpc3 = hpc3c0;
int err;
hal2 = kzalloc(sizeof(struct snd_hal2), GFP_KERNEL);
hal2 = kzalloc(sizeof(*hal2), GFP_KERNEL);
if (!hal2)
return -ENOMEM;

2
sound/mips/sgio2audio.c
View File

@ -840,7 +840,7 @@ static int snd_sgio2audio_create(struct snd_card *card,
if (!(readq(&mace->perif.audio.control) & AUDIO_CONTROL_CODEC_PRESENT))
return -ENOENT;
chip = kzalloc(sizeof(struct snd_sgio2audio), GFP_KERNEL);
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;

1
sound/pci/hda/Kconfig
View File

@ -88,7 +88,6 @@ config SND_HDA_PATCH_LOADER
config SND_HDA_CODEC_REALTEK
tristate "Build Realtek HD-audio codec support"
select SND_HDA_GENERIC
select INPUT
help
Say Y or M here to include Realtek HD-audio codec support in
snd-hda-intel driver, such as ALC880.

137
sound/pci/hda/patch_realtek.c
View File

@ -3154,11 +3154,13 @@ static void alc256_shutup(struct hda_codec *codec)
if (hp_pin_sense)
msleep(85);
/* 3k pull low control for Headset jack. */
/* NOTE: call this before clearing the pin, otherwise codec stalls */
alc_update_coef_idx(codec, 0x46, 0, 3 << 12);
snd_hda_codec_write(codec, hp_pin, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);
alc_update_coef_idx(codec, 0x46, 0, 3 << 12); /* 3k pull low control for Headset jack. */
if (hp_pin_sense)
msleep(100);
@ -3166,6 +3168,93 @@ static void alc256_shutup(struct hda_codec *codec)
snd_hda_shutup_pins(codec);
}
static void alc225_init(struct hda_codec *codec)
{
struct alc_spec *spec = codec->spec;
hda_nid_t hp_pin = spec->gen.autocfg.hp_pins[0];
bool hp1_pin_sense, hp2_pin_sense;
if (!hp_pin)
return;
msleep(30);
hp1_pin_sense = snd_hda_jack_detect(codec, hp_pin);
hp2_pin_sense = snd_hda_jack_detect(codec, 0x16);
if (hp1_pin_sense || hp2_pin_sense)
msleep(2);
alc_update_coefex_idx(codec, 0x57, 0x04, 0x0007, 0x1); /* Low power */
if (hp1_pin_sense)
snd_hda_codec_write(codec, hp_pin, 0,
AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);
if (hp2_pin_sense)
snd_hda_codec_write(codec, 0x16, 0,
AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);
if (hp1_pin_sense || hp2_pin_sense)
msleep(85);
if (hp1_pin_sense)
snd_hda_codec_write(codec, hp_pin, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
if (hp2_pin_sense)
snd_hda_codec_write(codec, 0x16, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
if (hp1_pin_sense || hp2_pin_sense)
msleep(100);
alc_update_coef_idx(codec, 0x4a, 3 << 10, 0);
alc_update_coefex_idx(codec, 0x57, 0x04, 0x0007, 0x4); /* Hight power */
}
static void alc225_shutup(struct hda_codec *codec)
{
struct alc_spec *spec = codec->spec;
hda_nid_t hp_pin = spec->gen.autocfg.hp_pins[0];
bool hp1_pin_sense, hp2_pin_sense;
if (!hp_pin) {
alc269_shutup(codec);
return;
}
/* 3k pull low control for Headset jack. */
alc_update_coef_idx(codec, 0x4a, 0, 3 << 10);
hp1_pin_sense = snd_hda_jack_detect(codec, hp_pin);
hp2_pin_sense = snd_hda_jack_detect(codec, 0x16);
if (hp1_pin_sense || hp2_pin_sense)
msleep(2);
if (hp1_pin_sense)
snd_hda_codec_write(codec, hp_pin, 0,
AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);
if (hp2_pin_sense)
snd_hda_codec_write(codec, 0x16, 0,
AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);
if (hp1_pin_sense || hp2_pin_sense)
msleep(85);
if (hp1_pin_sense)
snd_hda_codec_write(codec, hp_pin, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);
if (hp2_pin_sense)
snd_hda_codec_write(codec, 0x16, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);
if (hp1_pin_sense || hp2_pin_sense)
msleep(100);
alc_auto_setup_eapd(codec, false);
snd_hda_shutup_pins(codec);
}
static void alc_default_init(struct hda_codec *codec)
{
struct alc_spec *spec = codec->spec;
@ -3723,6 +3812,7 @@ static void alc280_fixup_hp_gpio4(struct hda_codec *codec,
}
}
#if IS_REACHABLE(INPUT)
static void gpio2_mic_hotkey_event(struct hda_codec *codec,
struct hda_jack_callback *event)
{
@ -3855,6 +3945,10 @@ static void alc233_fixup_lenovo_line2_mic_hotkey(struct hda_codec *codec,
spec->kb_dev = NULL;
}
}
#else /* INPUT */
#define alc280_fixup_hp_gpio2_mic_hotkey NULL
#define alc233_fixup_lenovo_line2_mic_hotkey NULL
#endif /* INPUT */
static void alc269_fixup_hp_line1_mic1_led(struct hda_codec *codec,
const struct hda_fixup *fix, int action)
@ -3994,8 +4088,11 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
case 0x10ec0668:
alc_process_coef_fw(codec, coef0668);
break;
case 0x10ec0215:
case 0x10ec0225:
case 0x10ec0285:
case 0x10ec0295:
case 0x10ec0289:
case 0x10ec0299:
alc_process_coef_fw(codec, coef0225);
break;
@ -4117,8 +4214,11 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
alc_process_coef_fw(codec, coef0688);
snd_hda_set_pin_ctl_cache(codec, mic_pin, PIN_VREF50);
break;
case 0x10ec0215:
case 0x10ec0225:
case 0x10ec0285:
case 0x10ec0295:
case 0x10ec0289:
case 0x10ec0299:
alc_process_coef_fw(codec, alc225_pre_hsmode);
alc_update_coef_idx(codec, 0x45, 0x3f<<10, 0x31<<10);
@ -4189,8 +4289,11 @@ static void alc_headset_mode_default(struct hda_codec *codec)
};
switch (codec->core.vendor_id) {
case 0x10ec0215:
case 0x10ec0225:
case 0x10ec0285:
case 0x10ec0295:
case 0x10ec0289:
case 0x10ec0299:
alc_process_coef_fw(codec, alc225_pre_hsmode);
alc_process_coef_fw(codec, coef0225);
@ -4332,8 +4435,11 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
case 0x10ec0668:
alc_process_coef_fw(codec, coef0688);
break;
case 0x10ec0215:
case 0x10ec0225:
case 0x10ec0285:
case 0x10ec0295:
case 0x10ec0289:
case 0x10ec0299:
val = alc_read_coef_idx(codec, 0x45);
if (val & (1 << 9))
@ -4436,8 +4542,11 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
case 0x10ec0668:
alc_process_coef_fw(codec, coef0688);
break;
case 0x10ec0215:
case 0x10ec0225:
case 0x10ec0285:
case 0x10ec0295:
case 0x10ec0289:
case 0x10ec0299:
alc_process_coef_fw(codec, coef0225);
break;
@ -4566,9 +4675,18 @@ static void alc_determine_headset_type(struct hda_codec *codec)
val = alc_read_coef_idx(codec, 0xbe);
is_ctia = (val & 0x1c02) == 0x1c02;
break;
case 0x10ec0215:
case 0x10ec0225:
case 0x10ec0285:
case 0x10ec0295:
case 0x10ec0289:
case 0x10ec0299:
snd_hda_codec_write(codec, 0x21, 0,
AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);
msleep(80);
snd_hda_codec_write(codec, 0x21, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);
alc_process_coef_fw(codec, alc225_pre_hsmode);
alc_update_coef_idx(codec, 0x67, 0xf000, 0x1000);
val = alc_read_coef_idx(codec, 0x45);
@ -4588,6 +4706,12 @@ static void alc_determine_headset_type(struct hda_codec *codec)
alc_update_coef_idx(codec, 0x4a, 7<<6, 7<<6);
alc_update_coef_idx(codec, 0x4a, 3<<4, 3<<4);
alc_update_coef_idx(codec, 0x67, 0xf000, 0x3000);
snd_hda_codec_write(codec, 0x21, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
msleep(80);
snd_hda_codec_write(codec, 0x21, 0,
AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
break;
case 0x10ec0867:
is_ctia = true;
@ -6920,16 +7044,17 @@ static int patch_alc269(struct hda_codec *codec)
case 0x10ec0285:
case 0x10ec0289:
spec->codec_variant = ALC269_TYPE_ALC215;
spec->shutup = alc225_shutup;
spec->init_hook = alc225_init;
spec->gen.mixer_nid = 0;
break;
case 0x10ec0225:
case 0x10ec0295:
spec->codec_variant = ALC269_TYPE_ALC225;
spec->gen.mixer_nid = 0; /* no loopback on ALC225 ALC295 */
break;
case 0x10ec0299:
spec->codec_variant = ALC269_TYPE_ALC225;
spec->gen.mixer_nid = 0; /* no loopback on ALC299 */
spec->shutup = alc225_shutup;
spec->init_hook = alc225_init;
spec->gen.mixer_nid = 0; /* no loopback on ALC225, ALC295 and ALC299 */
break;
case 0x10ec0234:
case 0x10ec0274:

133
sound/pci/ice1712/prodigy_hifi.c
View File

@ -965,13 +965,32 @@ static int prodigy_hd2_add_controls(struct snd_ice1712 *ice)
return 0;
}
/*
* initialize the chip
*/
static int prodigy_hifi_init(struct snd_ice1712 *ice)
static void wm8766_init(struct snd_ice1712 *ice)
{
static unsigned short wm_inits[] = {
static unsigned short wm8766_inits[] = {
WM8766_RESET, 0x0000,
WM8766_DAC_CTRL, 0x0120,
WM8766_INT_CTRL, 0x0022, /* I2S Normal Mode, 24 bit */
WM8766_DAC_CTRL2, 0x0001,
WM8766_DAC_CTRL3, 0x0080,
WM8766_LDA1, 0x0100,
WM8766_LDA2, 0x0100,
WM8766_LDA3, 0x0100,
WM8766_RDA1, 0x0100,
WM8766_RDA2, 0x0100,
WM8766_RDA3, 0x0100,
WM8766_MUTE1, 0x0000,
WM8766_MUTE2, 0x0000,
};
unsigned int i;
for (i = 0; i < ARRAY_SIZE(wm8766_inits); i += 2)
wm8766_spi_write(ice, wm8766_inits[i], wm8766_inits[i + 1]);
}
static void wm8776_init(struct snd_ice1712 *ice)
{
static unsigned short wm8776_inits[] = {
/* These come first to reduce init pop noise */
WM_ADC_MUX, 0x0003, /* ADC mute */
/* 0x00c0 replaced by 0x0003 */
@ -982,7 +1001,76 @@ static int prodigy_hifi_init(struct snd_ice1712 *ice)
WM_POWERDOWN, 0x0008, /* All power-up except HP */
WM_RESET, 0x0000, /* reset */
};
static unsigned short wm_inits2[] = {
unsigned int i;
for (i = 0; i < ARRAY_SIZE(wm8776_inits); i += 2)
wm_put(ice, wm8776_inits[i], wm8776_inits[i + 1]);
}
#ifdef CONFIG_PM_SLEEP
static int prodigy_hifi_resume(struct snd_ice1712 *ice)
{
static unsigned short wm8776_reinit_registers[] = {
WM_MASTER_CTRL,
WM_DAC_INT,
WM_ADC_INT,
WM_OUT_MUX,
WM_HP_ATTEN_L,
WM_HP_ATTEN_R,
WM_PHASE_SWAP,
WM_DAC_CTRL2,
WM_ADC_ATTEN_L,
WM_ADC_ATTEN_R,
WM_ALC_CTRL1,
WM_ALC_CTRL2,
WM_ALC_CTRL3,
WM_NOISE_GATE,
WM_ADC_MUX,
/* no DAC attenuation here */
};
struct prodigy_hifi_spec *spec = ice->spec;
int i, ch;
mutex_lock(&ice->gpio_mutex);
/* reinitialize WM8776 and re-apply old register values */
wm8776_init(ice);
schedule_timeout_uninterruptible(1);
for (i = 0; i < ARRAY_SIZE(wm8776_reinit_registers); i++)
wm_put(ice, wm8776_reinit_registers[i],
wm_get(ice, wm8776_reinit_registers[i]));
/* reinitialize WM8766 and re-apply volumes for all DACs */
wm8766_init(ice);
for (ch = 0; ch < 2; ch++) {
wm_set_vol(ice, WM_DAC_ATTEN_L + ch,
spec->vol[2 + ch], spec->master[ch]);
wm8766_set_vol(ice, WM8766_LDA1 + ch,
spec->vol[0 + ch], spec->master[ch]);
wm8766_set_vol(ice, WM8766_LDA2 + ch,
spec->vol[4 + ch], spec->master[ch]);
wm8766_set_vol(ice, WM8766_LDA3 + ch,
spec->vol[6 + ch], spec->master[ch]);
}
/* unmute WM8776 DAC */
wm_put(ice, WM_DAC_MUTE, 0x00);
wm_put(ice, WM_DAC_CTRL1, 0x90);
mutex_unlock(&ice->gpio_mutex);
return 0;
}
#endif
/*
* initialize the chip
*/
static int prodigy_hifi_init(struct snd_ice1712 *ice)
{
static unsigned short wm8776_defaults[] = {
WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
@ -1010,22 +1098,6 @@ static int prodigy_hifi_init(struct snd_ice1712 *ice)
WM_DAC_MUTE, 0x0000, /* DAC unmute */
WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
};
static unsigned short wm8766_inits[] = {
WM8766_RESET, 0x0000,
WM8766_DAC_CTRL, 0x0120,
WM8766_INT_CTRL, 0x0022, /* I2S Normal Mode, 24 bit */
WM8766_DAC_CTRL2, 0x0001,
WM8766_DAC_CTRL3, 0x0080,
WM8766_LDA1, 0x0100,
WM8766_LDA2, 0x0100,
WM8766_LDA3, 0x0100,
WM8766_RDA1, 0x0100,
WM8766_RDA2, 0x0100,
WM8766_RDA3, 0x0100,
WM8766_MUTE1, 0x0000,
WM8766_MUTE2, 0x0000,
};
struct prodigy_hifi_spec *spec;
unsigned int i;
@ -1052,16 +1124,17 @@ static int prodigy_hifi_init(struct snd_ice1712 *ice)
ice->spec = spec;
/* initialize WM8776 codec */
for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
wm_put(ice, wm_inits[i], wm_inits[i+1]);
wm8776_init(ice);
schedule_timeout_uninterruptible(1);
for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
for (i = 0; i < ARRAY_SIZE(wm8776_defaults); i += 2)
wm_put(ice, wm8776_defaults[i], wm8776_defaults[i + 1]);
/* initialize WM8766 codec */
for (i = 0; i < ARRAY_SIZE(wm8766_inits); i += 2)
wm8766_spi_write(ice, wm8766_inits[i], wm8766_inits[i+1]);
wm8766_init(ice);
#ifdef CONFIG_PM_SLEEP
ice->pm_resume = &prodigy_hifi_resume;
ice->pm_suspend_enabled = 1;
#endif
return 0;
}

1
sound/pci/korg1212/korg1212.c
View File

@ -2348,7 +2348,6 @@ static int snd_korg1212_create(struct snd_card *card, struct pci_dev *pci,
err = request_firmware(&dsp_code, "korg/k1212.dsp", &pci->dev);
if (err < 0) {
release_firmware(dsp_code);
snd_printk(KERN_ERR "firmware not available\n");
snd_korg1212_free(korg1212);
return err;

1
sound/soc/Kconfig
View File

@ -71,6 +71,7 @@ source "sound/soc/stm/Kconfig"
source "sound/soc/sunxi/Kconfig"
source "sound/soc/tegra/Kconfig"
source "sound/soc/txx9/Kconfig"
source "sound/soc/uniphier/Kconfig"
source "sound/soc/ux500/Kconfig"
source "sound/soc/xtensa/Kconfig"
source "sound/soc/zte/Kconfig"

1
sound/soc/Makefile
View File

@ -55,6 +55,7 @@ obj-$(CONFIG_SND_SOC) += stm/
obj-$(CONFIG_SND_SOC) += sunxi/
obj-$(CONFIG_SND_SOC) += tegra/
obj-$(CONFIG_SND_SOC) += txx9/
obj-$(CONFIG_SND_SOC) += uniphier/
obj-$(CONFIG_SND_SOC) += ux500/
obj-$(CONFIG_SND_SOC) += xtensa/
obj-$(CONFIG_SND_SOC) += zte/

35
sound/soc/amd/acp-pcm-dma.c
View File

@ -850,6 +850,9 @@ static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
if (!rtd)
return -EINVAL;
buffersize = frames_to_bytes(runtime, runtime->buffer_size);
bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream);
@ -875,6 +878,8 @@ static int acp_dma_prepare(struct snd_pcm_substream *substream)
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
if (!rtd)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
PLAYBACK_START_DMA_DESCR_CH12,
@ -1091,7 +1096,11 @@ static int acp_audio_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, audio_drv_data);
/* Initialize the ACP */
acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
if (status) {
dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
return status;
}
status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform);
if (status != 0) {
@ -1108,9 +1117,12 @@ static int acp_audio_probe(struct platform_device *pdev)
static int acp_audio_remove(struct platform_device *pdev)
{
int status;
struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
acp_deinit(adata->acp_mmio);
status = acp_deinit(adata->acp_mmio);
if (status)
dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
snd_soc_unregister_platform(&pdev->dev);
pm_runtime_disable(&pdev->dev);
@ -1120,9 +1132,14 @@ static int acp_audio_remove(struct platform_device *pdev)
static int acp_pcm_resume(struct device *dev)
{
u16 bank;
int status;
struct audio_drv_data *adata = dev_get_drvdata(dev);
acp_init(adata->acp_mmio, adata->asic_type);
status = acp_init(adata->acp_mmio, adata->asic_type);
if (status) {
dev_err(dev, "ACP Init failed status:%d\n", status);
return status;
}
if (adata->play_stream && adata->play_stream->runtime) {
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
@ -1154,18 +1171,26 @@ static int acp_pcm_resume(struct device *dev)
static int acp_pcm_runtime_suspend(struct device *dev)
{
int status;
struct audio_drv_data *adata = dev_get_drvdata(dev);
acp_deinit(adata->acp_mmio);
status = acp_deinit(adata->acp_mmio);
if (status)
dev_err(dev, "ACP Deinit failed status:%d\n", status);
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static int acp_pcm_runtime_resume(struct device *dev)
{
int status;
struct audio_drv_data *adata = dev_get_drvdata(dev);
acp_init(adata->acp_mmio, adata->asic_type);
status = acp_init(adata->acp_mmio, adata->asic_type);
if (status) {
dev_err(dev, "ACP Init failed status:%d\n", status);
return status;
}
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}

6
sound/soc/atmel/atmel-classd.c
View File

@ -308,15 +308,9 @@ static int atmel_classd_codec_resume(struct snd_soc_codec *codec)
return regcache_sync(dd->regmap);
}
static struct regmap *atmel_classd_codec_get_remap(struct device *dev)
{
return dev_get_regmap(dev, NULL);
}
static struct snd_soc_codec_driver soc_codec_dev_classd = {
.probe = atmel_classd_codec_probe,
.resume = atmel_classd_codec_resume,
.get_regmap = atmel_classd_codec_get_remap,
.component_driver = {
.controls = atmel_classd_snd_controls,
.num_controls = ARRAY_SIZE(atmel_classd_snd_controls),

6
sound/soc/au1x/ac97c.c
View File

@ -91,8 +91,8 @@ static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
do {
mutex_lock(&ctx->lock);
tmo = 5;
while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
tmo = 6;
while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
udelay(21); /* wait an ac97 frame time */
if (!tmo) {
pr_debug("ac97rd timeout #1\n");
@ -105,7 +105,7 @@ static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
* poll, Forrest, poll...
*/
tmo = 0x10000;
while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
asm volatile ("nop");
data = RD(ctx, AC97_CMDRESP);

20
sound/soc/bcm/bcm2835-i2s.c
View File

@ -130,6 +130,7 @@ struct bcm2835_i2s_dev {
struct regmap *i2s_regmap;
struct clk *clk;
bool clk_prepared;
int clk_rate;
};
static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
@ -419,10 +420,19 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
}
/* Clock should only be set up here if CPU is clock master */
if (bit_clock_master) {
ret = clk_set_rate(dev->clk, bclk_rate);
if (ret)
return ret;
if (bit_clock_master &&
(!dev->clk_prepared || dev->clk_rate != bclk_rate)) {
if (dev->clk_prepared)
bcm2835_i2s_stop_clock(dev);
if (dev->clk_rate != bclk_rate) {
ret = clk_set_rate(dev->clk, bclk_rate);
if (ret)
return ret;
dev->clk_rate = bclk_rate;
}
bcm2835_i2s_start_clock(dev);
}
/* Setup the frame format */
@ -618,8 +628,6 @@ static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
uint32_t cs_reg;
bcm2835_i2s_start_clock(dev);
/*
* Clear both FIFOs if the one that should be started
* is not empty at the moment. This should only happen

6
sound/soc/cirrus/ep93xx-ac97.c
View File

@ -365,7 +365,7 @@ static int ep93xx_ac97_probe(struct platform_device *pdev)
{
struct ep93xx_ac97_info *info;
struct resource *res;
unsigned int irq;
int irq;
int ret;
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
@ -378,8 +378,8 @@ static int ep93xx_ac97_probe(struct platform_device *pdev)
return PTR_ERR(info->regs);
irq = platform_get_irq(pdev, 0);
if (!irq)
return -ENODEV;
if (irq <= 0)
return irq < 0 ? irq : -ENODEV;
ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
IRQF_TRIGGER_HIGH, pdev->name, info);

9
sound/soc/codecs/88pm860x-codec.c
View File

@ -1319,6 +1319,7 @@ static int pm860x_probe(struct snd_soc_codec *codec)
int i, ret;
pm860x->codec = codec;
snd_soc_codec_init_regmap(codec, pm860x->regmap);
for (i = 0; i < 4; i++) {
ret = request_threaded_irq(pm860x->irq[i], NULL,
@ -1348,18 +1349,10 @@ static int pm860x_remove(struct snd_soc_codec *codec)
return 0;
}
static struct regmap *pm860x_get_regmap(struct device *dev)
{
struct pm860x_priv *pm860x = dev_get_drvdata(dev);
return pm860x->regmap;
}
static const struct snd_soc_codec_driver soc_codec_dev_pm860x = {
.probe = pm860x_probe,
.remove = pm860x_remove,
.set_bias_level = pm860x_set_bias_level,
.get_regmap = pm860x_get_regmap,
.component_driver = {
.controls = pm860x_snd_controls,

46
sound/soc/codecs/Kconfig
View File

@ -95,6 +95,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_MAX98925 if I2C
select SND_SOC_MAX98926 if I2C
select SND_SOC_MAX98927 if I2C
select SND_SOC_MAX98373 if I2C
select SND_SOC_MAX9850 if I2C
select SND_SOC_MAX9860 if I2C
select SND_SOC_MAX9768 if I2C
@ -109,6 +110,8 @@ config SND_SOC_ALL_CODECS
select SND_SOC_PCM1681 if I2C
select SND_SOC_PCM179X_I2C if I2C
select SND_SOC_PCM179X_SPI if SPI_MASTER
select SND_SOC_PCM186X_I2C if I2C
select SND_SOC_PCM186X_SPI if SPI_MASTER
select SND_SOC_PCM3008
select SND_SOC_PCM3168A_I2C if I2C
select SND_SOC_PCM3168A_SPI if SPI_MASTER
@ -133,7 +136,6 @@ config SND_SOC_ALL_CODECS
select SND_SOC_SGTL5000 if I2C
select SND_SOC_SI476X if MFD_SI476X_CORE
select SND_SOC_SIRF_AUDIO_CODEC
select SND_SOC_SN95031 if INTEL_SCU_IPC
select SND_SOC_SPDIF
select SND_SOC_SSM2518 if I2C
select SND_SOC_SSM2602_SPI if SPI_MASTER
@ -148,6 +150,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_TAS5086 if I2C
select SND_SOC_TAS571X if I2C
select SND_SOC_TAS5720 if I2C
select SND_SOC_TAS6424 if I2C
select SND_SOC_TFA9879 if I2C
select SND_SOC_TLV320AIC23_I2C if I2C
select SND_SOC_TLV320AIC23_SPI if SPI_MASTER
@ -158,6 +161,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_TLV320AIC3X if I2C
select SND_SOC_TPA6130A2 if I2C
select SND_SOC_TLV320DAC33 if I2C
select SND_SOC_TSCS42XX if I2C
select SND_SOC_TS3A227E if I2C
select SND_SOC_TWL4030 if TWL4030_CORE
select SND_SOC_TWL6040 if TWL6040_CORE
@ -623,6 +627,10 @@ config SND_SOC_MAX98927
tristate "Maxim Integrated MAX98927 Speaker Amplifier"
depends on I2C
config SND_SOC_MAX98373
tristate "Maxim Integrated MAX98373 Speaker Amplifier"
depends on I2C
config SND_SOC_MAX9850
tristate
@ -661,6 +669,21 @@ config SND_SOC_PCM179X_SPI
Enable support for Texas Instruments PCM179x CODEC.
Select this if your PCM179x is connected via an SPI bus.
config SND_SOC_PCM186X
tristate
config SND_SOC_PCM186X_I2C
tristate "Texas Instruments PCM186x CODECs - I2C"
depends on I2C
select SND_SOC_PCM186X
select REGMAP_I2C
config SND_SOC_PCM186X_SPI
tristate "Texas Instruments PCM186x CODECs - SPI"
depends on SPI_MASTER
select SND_SOC_PCM186X
select REGMAP_SPI
config SND_SOC_PCM3008
tristate
@ -818,9 +841,6 @@ config SND_SOC_SIRF_AUDIO_CODEC
tristate "SiRF SoC internal audio codec"
select REGMAP_MMIO
config SND_SOC_SN95031
tristate
config SND_SOC_SPDIF
tristate "S/PDIF CODEC"
@ -883,6 +903,13 @@ config SND_SOC_TAS5720
Enable support for Texas Instruments TAS5720L/M high-efficiency mono
Class-D audio power amplifiers.
config SND_SOC_TAS6424
tristate "Texas Instruments TAS6424 Quad-Channel Audio amplifier"
depends on I2C
help
Enable support for Texas Instruments TAS6424 high-efficiency
digital input quad-channel Class-D audio power amplifiers.
config SND_SOC_TFA9879
tristate "NXP Semiconductors TFA9879 amplifier"
depends on I2C
@ -913,12 +940,12 @@ config SND_SOC_TLV320AIC32X4
tristate
config SND_SOC_TLV320AIC32X4_I2C
tristate
tristate "Texas Instruments TLV320AIC32x4 audio CODECs - I2C"
depends on I2C
select SND_SOC_TLV320AIC32X4
config SND_SOC_TLV320AIC32X4_SPI
tristate
tristate "Texas Instruments TLV320AIC32x4 audio CODECs - SPI"
depends on SPI_MASTER
select SND_SOC_TLV320AIC32X4
@ -933,6 +960,13 @@ config SND_SOC_TS3A227E
tristate "TI Headset/Mic detect and keypress chip"
depends on I2C
config SND_SOC_TSCS42XX
tristate "Tempo Semiconductor TSCS42xx CODEC"
depends on I2C
select REGMAP_I2C
help
Add support for Tempo Semiconductor's TSCS42xx audio CODEC.
config SND_SOC_TWL4030
select MFD_TWL4030_AUDIO
tristate

13
sound/soc/codecs/Makefile
View File

@ -90,6 +90,7 @@ snd-soc-max9867-objs := max9867.o
snd-soc-max98925-objs := max98925.o
snd-soc-max98926-objs := max98926.o
snd-soc-max98927-objs := max98927.o
snd-soc-max98373-objs := max98373.o
snd-soc-max9850-objs := max9850.o
snd-soc-max9860-objs := max9860.o
snd-soc-mc13783-objs := mc13783.o
@ -105,6 +106,9 @@ snd-soc-pcm1681-objs := pcm1681.o
snd-soc-pcm179x-codec-objs := pcm179x.o
snd-soc-pcm179x-i2c-objs := pcm179x-i2c.o
snd-soc-pcm179x-spi-objs := pcm179x-spi.o
snd-soc-pcm186x-objs := pcm186x.o
snd-soc-pcm186x-i2c-objs := pcm186x-i2c.o
snd-soc-pcm186x-spi-objs := pcm186x-spi.o
snd-soc-pcm3008-objs := pcm3008.o
snd-soc-pcm3168a-objs := pcm3168a.o
snd-soc-pcm3168a-i2c-objs := pcm3168a-i2c.o
@ -140,7 +144,6 @@ snd-soc-sigmadsp-i2c-objs := sigmadsp-i2c.o
snd-soc-sigmadsp-regmap-objs := sigmadsp-regmap.o
snd-soc-si476x-objs := si476x.o
snd-soc-sirf-audio-codec-objs := sirf-audio-codec.o
snd-soc-sn95031-objs := sn95031.o
snd-soc-spdif-tx-objs := spdif_transmitter.o
snd-soc-spdif-rx-objs := spdif_receiver.o
snd-soc-ssm2518-objs := ssm2518.o
@ -156,6 +159,7 @@ snd-soc-sti-sas-objs := sti-sas.o
snd-soc-tas5086-objs := tas5086.o
snd-soc-tas571x-objs := tas571x.o
snd-soc-tas5720-objs := tas5720.o
snd-soc-tas6424-objs := tas6424.o
snd-soc-tfa9879-objs := tfa9879.o
snd-soc-tlv320aic23-objs := tlv320aic23.o
snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o
@ -167,6 +171,7 @@ snd-soc-tlv320aic32x4-i2c-objs := tlv320aic32x4-i2c.o
snd-soc-tlv320aic32x4-spi-objs := tlv320aic32x4-spi.o
snd-soc-tlv320aic3x-objs := tlv320aic3x.o
snd-soc-tlv320dac33-objs := tlv320dac33.o
snd-soc-tscs42xx-objs := tscs42xx.o
snd-soc-ts3a227e-objs := ts3a227e.o
snd-soc-twl4030-objs := twl4030.o
snd-soc-twl6040-objs := twl6040.o
@ -330,6 +335,7 @@ obj-$(CONFIG_SND_SOC_MAX9867) += snd-soc-max9867.o
obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o
obj-$(CONFIG_SND_SOC_MAX98927) += snd-soc-max98927.o
obj-$(CONFIG_SND_SOC_MAX98373) += snd-soc-max98373.o
obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
@ -345,6 +351,9 @@ obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o
obj-$(CONFIG_SND_SOC_PCM179X) += snd-soc-pcm179x-codec.o
obj-$(CONFIG_SND_SOC_PCM179X_I2C) += snd-soc-pcm179x-i2c.o
obj-$(CONFIG_SND_SOC_PCM179X_SPI) += snd-soc-pcm179x-spi.o
obj-$(CONFIG_SND_SOC_PCM186X) += snd-soc-pcm186x.o
obj-$(CONFIG_SND_SOC_PCM186X_I2C) += snd-soc-pcm186x-i2c.o
obj-$(CONFIG_SND_SOC_PCM186X_SPI) += snd-soc-pcm186x-spi.o
obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
obj-$(CONFIG_SND_SOC_PCM3168A) += snd-soc-pcm3168a.o
obj-$(CONFIG_SND_SOC_PCM3168A_I2C) += snd-soc-pcm3168a-i2c.o
@ -395,6 +404,7 @@ obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o
obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
obj-$(CONFIG_SND_SOC_TAS6424) += snd-soc-tas6424.o
obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o
obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o
@ -406,6 +416,7 @@ obj-$(CONFIG_SND_SOC_TLV320AIC32X4_I2C) += snd-soc-tlv320aic32x4-i2c.o
obj-$(CONFIG_SND_SOC_TLV320AIC32X4_SPI) += snd-soc-tlv320aic32x4-spi.o
obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o
obj-$(CONFIG_SND_SOC_TSCS42XX) += snd-soc-tscs42xx.o
obj-$(CONFIG_SND_SOC_TS3A227E) += snd-soc-ts3a227e.o
obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o

10
sound/soc/codecs/cq93vc.c
View File

@ -121,17 +121,19 @@ static struct snd_soc_dai_driver cq93vc_dai = {
.ops = &cq93vc_dai_ops,
};
static struct regmap *cq93vc_get_regmap(struct device *dev)
static int cq93vc_probe(struct snd_soc_component *component)
{
struct davinci_vc *davinci_vc = dev->platform_data;
struct davinci_vc *davinci_vc = component->dev->platform_data;
return davinci_vc->regmap;
snd_soc_component_init_regmap(component, davinci_vc->regmap);
return 0;
}
static const struct snd_soc_codec_driver soc_codec_dev_cq93vc = {
.set_bias_level = cq93vc_set_bias_level,
.get_regmap = cq93vc_get_regmap,
.component_driver = {
.probe = cq93vc_probe,
.controls = cq93vc_snd_controls,
.num_controls = ARRAY_SIZE(cq93vc_snd_controls),
},

18
sound/soc/codecs/cs35l32.c
View File

@ -355,13 +355,9 @@ static int cs35l32_i2c_probe(struct i2c_client *i2c_client,
unsigned int devid = 0;
unsigned int reg;
cs35l32 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l32_private),
GFP_KERNEL);
if (!cs35l32) {
dev_err(&i2c_client->dev, "could not allocate codec\n");
cs35l32 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l32), GFP_KERNEL);
if (!cs35l32)
return -ENOMEM;
}
i2c_set_clientdata(i2c_client, cs35l32);
@ -375,13 +371,11 @@ static int cs35l32_i2c_probe(struct i2c_client *i2c_client,
if (pdata) {
cs35l32->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev,
sizeof(struct cs35l32_platform_data),
GFP_KERNEL);
if (!pdata) {
dev_err(&i2c_client->dev, "could not allocate pdata\n");
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
}
if (i2c_client->dev.of_node) {
ret = cs35l32_handle_of_data(i2c_client,
&cs35l32->pdata);

19
sound/soc/codecs/cs35l34.c
View File

@ -1004,13 +1004,9 @@ static int cs35l34_i2c_probe(struct i2c_client *i2c_client,
unsigned int devid = 0;
unsigned int reg;
cs35l34 = devm_kzalloc(&i2c_client->dev,
sizeof(struct cs35l34_private),
GFP_KERNEL);
if (!cs35l34) {
dev_err(&i2c_client->dev, "could not allocate codec\n");
cs35l34 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l34), GFP_KERNEL);
if (!cs35l34)
return -ENOMEM;
}
i2c_set_clientdata(i2c_client, cs35l34);
cs35l34->regmap = devm_regmap_init_i2c(i2c_client, &cs35l34_regmap);
@ -1044,14 +1040,11 @@ static int cs35l34_i2c_probe(struct i2c_client *i2c_client,
if (pdata) {
cs35l34->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev,
sizeof(struct cs35l34_platform_data),
GFP_KERNEL);
if (!pdata) {
dev_err(&i2c_client->dev,
"could not allocate pdata\n");
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
}
if (i2c_client->dev.of_node) {
ret = cs35l34_handle_of_data(i2c_client, pdata);
if (ret != 0)

13
sound/soc/codecs/cs42l52.c
View File

@ -1100,8 +1100,7 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
unsigned int reg;
u32 val32;
cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
GFP_KERNEL);
cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l52), GFP_KERNEL);
if (cs42l52 == NULL)
return -ENOMEM;
cs42l52->dev = &i2c_client->dev;
@ -1115,13 +1114,11 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
if (pdata) {
cs42l52->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev,
sizeof(struct cs42l52_platform_data),
GFP_KERNEL);
if (!pdata) {
dev_err(&i2c_client->dev, "could not allocate pdata\n");
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
}
if (i2c_client->dev.of_node) {
if (of_property_read_bool(i2c_client->dev.of_node,
"cirrus,mica-differential-cfg"))

13
sound/soc/codecs/cs42l56.c
View File

@ -1190,9 +1190,7 @@ static int cs42l56_i2c_probe(struct i2c_client *i2c_client,
unsigned int alpha_rev, metal_rev;
unsigned int reg;
cs42l56 = devm_kzalloc(&i2c_client->dev,
sizeof(struct cs42l56_private),
GFP_KERNEL);
cs42l56 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l56), GFP_KERNEL);
if (cs42l56 == NULL)
return -ENOMEM;
cs42l56->dev = &i2c_client->dev;
@ -1207,14 +1205,11 @@ static int cs42l56_i2c_probe(struct i2c_client *i2c_client,
if (pdata) {
cs42l56->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev,
sizeof(struct cs42l56_platform_data),
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata) {
dev_err(&i2c_client->dev,
"could not allocate pdata\n");
if (!pdata)
return -ENOMEM;
}
if (i2c_client->dev.of_node) {
ret = cs42l56_handle_of_data(i2c_client,
&cs42l56->pdata);

15
sound/soc/codecs/cs42l73.c
View File

@ -1289,8 +1289,7 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
unsigned int reg;
u32 val32;
cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private),
GFP_KERNEL);
cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l73), GFP_KERNEL);
if (!cs42l73)
return -ENOMEM;
@ -1304,13 +1303,11 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
if (pdata) {
cs42l73->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev,
sizeof(struct cs42l73_platform_data),
GFP_KERNEL);
if (!pdata) {
dev_err(&i2c_client->dev, "could not allocate pdata\n");
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
}
if (i2c_client->dev.of_node) {
if (of_property_read_u32(i2c_client->dev.of_node,
"chgfreq", &val32) >= 0)
@ -1358,7 +1355,7 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
ret = regmap_read(cs42l73->regmap, CS42L73_REVID, &reg);
if (ret < 0) {
dev_err(&i2c_client->dev, "Get Revision ID failed\n");
return ret;;
return ret;
}
dev_info(&i2c_client->dev,

12
sound/soc/codecs/cs47l24.c
View File

@ -1120,9 +1120,11 @@ static int cs47l24_codec_probe(struct snd_soc_codec *codec)
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
struct cs47l24_priv *priv = snd_soc_codec_get_drvdata(codec);
struct arizona *arizona = priv->core.arizona;
int ret;
priv->core.arizona->dapm = dapm;
arizona->dapm = dapm;
snd_soc_codec_init_regmap(codec, arizona->regmap);
ret = arizona_init_spk(codec);
if (ret < 0)
@ -1175,17 +1177,9 @@ static unsigned int cs47l24_digital_vu[] = {
ARIZONA_DAC_DIGITAL_VOLUME_4L,
};
static struct regmap *cs47l24_get_regmap(struct device *dev)
{
struct cs47l24_priv *priv = dev_get_drvdata(dev);
return priv->core.arizona->regmap;
}
static const struct snd_soc_codec_driver soc_codec_dev_cs47l24 = {
.probe = cs47l24_codec_probe,
.remove = cs47l24_codec_remove,
.get_regmap = cs47l24_get_regmap,
.idle_bias_off = true,

46
sound/soc/codecs/cx20442.c
View File

@ -26,8 +26,9 @@
struct cx20442_priv {
void *control_data;
struct tty_struct *tty;
struct regulator *por;
u8 reg_cache;
};
#define CX20442_PM 0x0
@ -89,14 +90,14 @@ static const struct snd_soc_dapm_route cx20442_audio_map[] = {
};
static unsigned int cx20442_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
unsigned int reg)
{
u8 *reg_cache = codec->reg_cache;
struct cx20442_priv *cx20442 = snd_soc_codec_get_drvdata(codec);
if (reg >= codec->driver->reg_cache_size)
if (reg >= 1)
return -EINVAL;
return reg_cache[reg];
return cx20442->reg_cache;
}
enum v253_vls {
@ -156,20 +157,19 @@ static int cx20442_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
struct cx20442_priv *cx20442 = snd_soc_codec_get_drvdata(codec);
u8 *reg_cache = codec->reg_cache;
int vls, vsp, old, len;
char buf[18];
if (reg >= codec->driver->reg_cache_size)
if (reg >= 1)
return -EINVAL;
/* hw_write and control_data pointers required for talking to the modem
/* tty and write pointers required for talking to the modem
* are expected to be set by the line discipline initialization code */
if (!codec->hw_write || !cx20442->control_data)
if (!cx20442->tty || !cx20442->tty->ops->write)
return -EIO;
old = reg_cache[reg];
reg_cache[reg] = value;
old = cx20442->reg_cache;
cx20442->reg_cache = value;
vls = cx20442_pm_to_v253_vls(value);
if (vls < 0)
@ -194,13 +194,12 @@ static int cx20442_write(struct snd_soc_codec *codec, unsigned int reg,
return -ENOMEM;
dev_dbg(codec->dev, "%s: %s\n", __func__, buf);
if (codec->hw_write(cx20442->control_data, buf, len) != len)
if (cx20442->tty->ops->write(cx20442->tty, buf, len) != len)
return -EIO;
return 0;
}
/*
* Line discpline related code
*
@ -252,8 +251,7 @@ static void v253_close(struct tty_struct *tty)
cx20442 = snd_soc_codec_get_drvdata(codec);
/* Prevent the codec driver from further accessing the modem */
codec->hw_write = NULL;
cx20442->control_data = NULL;
cx20442->tty = NULL;
codec->component.card->pop_time = 0;
}
@ -276,12 +274,11 @@ static void v253_receive(struct tty_struct *tty,
cx20442 = snd_soc_codec_get_drvdata(codec);
if (!cx20442->control_data) {
if (!cx20442->tty) {
/* First modem response, complete setup procedure */
/* Set up codec driver access to modem controls */
cx20442->control_data = tty;
codec->hw_write = (hw_write_t)tty->ops->write;
cx20442->tty = tty;
codec->component.card->pop_time = 1;
}
}
@ -367,10 +364,9 @@ static int cx20442_codec_probe(struct snd_soc_codec *codec)
cx20442->por = regulator_get(codec->dev, "POR");
if (IS_ERR(cx20442->por))
dev_warn(codec->dev, "failed to get the regulator");
cx20442->control_data = NULL;
cx20442->tty = NULL;
snd_soc_codec_set_drvdata(codec, cx20442);
codec->hw_write = NULL;
codec->component.card->pop_time = 0;
return 0;
@ -381,8 +377,8 @@ static int cx20442_codec_remove(struct snd_soc_codec *codec)
{
struct cx20442_priv *cx20442 = snd_soc_codec_get_drvdata(codec);
if (cx20442->control_data) {
struct tty_struct *tty = cx20442->control_data;
if (cx20442->tty) {
struct tty_struct *tty = cx20442->tty;
tty_hangup(tty);
}
@ -396,17 +392,13 @@ static int cx20442_codec_remove(struct snd_soc_codec *codec)
return 0;
}
static const u8 cx20442_reg;
static const struct snd_soc_codec_driver cx20442_codec_dev = {
.probe = cx20442_codec_probe,
.remove = cx20442_codec_remove,
.set_bias_level = cx20442_set_bias_level,
.reg_cache_default = &cx20442_reg,
.reg_cache_size = 1,
.reg_word_size = sizeof(u8),
.read = cx20442_read_reg_cache,
.write = cx20442_write,
.component_driver = {
.dapm_widgets = cx20442_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cx20442_dapm_widgets),

7
sound/soc/codecs/da7213.c
View File

@ -1654,10 +1654,8 @@ static struct da7213_platform_data
u32 fw_val32;
pdata = devm_kzalloc(codec->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
dev_warn(codec->dev, "Failed to allocate memory for pdata\n");
if (!pdata)
return NULL;
}
if (device_property_read_u32(dev, "dlg,micbias1-lvl", &fw_val32) >= 0)
pdata->micbias1_lvl = da7213_of_micbias_lvl(codec, fw_val32);
@ -1855,8 +1853,7 @@ static int da7213_i2c_probe(struct i2c_client *i2c,
struct da7213_priv *da7213;
int ret;
da7213 = devm_kzalloc(&i2c->dev, sizeof(struct da7213_priv),
GFP_KERNEL);
da7213 = devm_kzalloc(&i2c->dev, sizeof(*da7213), GFP_KERNEL);
if (!da7213)
return -ENOMEM;

9
sound/soc/codecs/da7218.c
View File

@ -2455,10 +2455,8 @@ static struct da7218_pdata *da7218_of_to_pdata(struct snd_soc_codec *codec)
u32 of_val32;
pdata = devm_kzalloc(codec->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
dev_warn(codec->dev, "Failed to allocate memory for pdata\n");
if (!pdata)
return NULL;
}
if (of_property_read_u32(np, "dlg,micbias1-lvl-millivolt", &of_val32) >= 0)
pdata->micbias1_lvl = da7218_of_micbias_lvl(codec, of_val32);
@ -2527,8 +2525,6 @@ static struct da7218_pdata *da7218_of_to_pdata(struct snd_soc_codec *codec)
hpldet_pdata = devm_kzalloc(codec->dev, sizeof(*hpldet_pdata),
GFP_KERNEL);
if (!hpldet_pdata) {
dev_warn(codec->dev,
"Failed to allocate memory for hpldet pdata\n");
of_node_put(hpldet_np);
return pdata;
}
@ -3273,8 +3269,7 @@ static int da7218_i2c_probe(struct i2c_client *i2c,
struct da7218_priv *da7218;
int ret;
da7218 = devm_kzalloc(&i2c->dev, sizeof(struct da7218_priv),
GFP_KERNEL);
da7218 = devm_kzalloc(&i2c->dev, sizeof(*da7218), GFP_KERNEL);
if (!da7218)
return -ENOMEM;

24
sound/soc/codecs/dmic.c
View File

@ -107,8 +107,30 @@ static const struct snd_soc_codec_driver soc_dmic = {
static int dmic_dev_probe(struct platform_device *pdev)
{
int err;
u32 chans;
struct snd_soc_dai_driver *dai_drv = &dmic_dai;
if (pdev->dev.of_node) {
err = of_property_read_u32(pdev->dev.of_node, "num-channels", &chans);
if (err && (err != -ENOENT))
return err;
if (!err) {
if (chans < 1 || chans > 8)
return -EINVAL;
dai_drv = devm_kzalloc(&pdev->dev, sizeof(*dai_drv), GFP_KERNEL);
if (!dai_drv)
return -ENOMEM;
memcpy(dai_drv, &dmic_dai, sizeof(*dai_drv));
dai_drv->capture.channels_max = chans;
}
}
return snd_soc_register_codec(&pdev->dev,
&soc_dmic, &dmic_dai, 1);
&soc_dmic, dai_drv, 1);
}
static int dmic_dev_remove(struct platform_device *pdev)

358
sound/soc/codecs/hdac_hdmi.c
View File

File diff suppressed because it is too large Load Diff

976
sound/soc/codecs/max98373.c Normal file
View File

@ -0,0 +1,976 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2017, Maxim Integrated */
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/tlv.h>
#include "max98373.h"
static struct reg_default max98373_reg[] = {
{MAX98373_R2000_SW_RESET, 0x00},
{MAX98373_R2001_INT_RAW1, 0x00},
{MAX98373_R2002_INT_RAW2, 0x00},
{MAX98373_R2003_INT_RAW3, 0x00},
{MAX98373_R2004_INT_STATE1, 0x00},
{MAX98373_R2005_INT_STATE2, 0x00},
{MAX98373_R2006_INT_STATE3, 0x00},
{MAX98373_R2007_INT_FLAG1, 0x00},
{MAX98373_R2008_INT_FLAG2, 0x00},
{MAX98373_R2009_INT_FLAG3, 0x00},
{MAX98373_R200A_INT_EN1, 0x00},
{MAX98373_R200B_INT_EN2, 0x00},
{MAX98373_R200C_INT_EN3, 0x00},
{MAX98373_R200D_INT_FLAG_CLR1, 0x00},
{MAX98373_R200E_INT_FLAG_CLR2, 0x00},
{MAX98373_R200F_INT_FLAG_CLR3, 0x00},
{MAX98373_R2010_IRQ_CTRL, 0x00},
{MAX98373_R2014_THERM_WARN_THRESH, 0x10},
{MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
{MAX98373_R2016_THERM_HYSTERESIS, 0x01},
{MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
{MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
{MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
{MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
{MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2022_PCM_TX_SRC_1, 0x00},
{MAX98373_R2023_PCM_TX_SRC_2, 0x00},
{MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
{MAX98373_R2025_AUDIO_IF_MODE, 0x00},
{MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
{MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
{MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
{MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
{MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
{MAX98373_R202B_PCM_RX_EN, 0x00},
{MAX98373_R202C_PCM_TX_EN, 0x00},
{MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
{MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
{MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
{MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
{MAX98373_R2034_ICC_TX_CNTL, 0x00},
{MAX98373_R2035_ICC_TX_EN, 0x00},
{MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
{MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
{MAX98373_R203E_AMP_PATH_GAIN, 0x08},
{MAX98373_R203F_AMP_DSP_CFG, 0x02},
{MAX98373_R2040_TONE_GEN_CFG, 0x00},
{MAX98373_R2041_AMP_CFG, 0x03},
{MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
{MAX98373_R2043_AMP_EN, 0x00},
{MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
{MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
{MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
{MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
{MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
{MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
{MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
{MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
{MAX98373_R2090_BDE_LVL_HOLD, 0x00},
{MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
{MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
{MAX98373_R2097_BDE_L1_THRESH, 0x00},
{MAX98373_R2098_BDE_L2_THRESH, 0x00},
{MAX98373_R2099_BDE_L3_THRESH, 0x00},
{MAX98373_R209A_BDE_L4_THRESH, 0x00},
{MAX98373_R209B_BDE_THRESH_HYST, 0x00},
{MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
{MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
{MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
{MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
{MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
{MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
{MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
{MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
{MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
{MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
{MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
{MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
{MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
{MAX98373_R20B5_BDE_EN, 0x00},
{MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
{MAX98373_R20D1_DHT_CFG, 0x01},
{MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
{MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
{MAX98373_R20D4_DHT_EN, 0x00},
{MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
{MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
{MAX98373_R20E2_LIMITER_EN, 0x00},
{MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
{MAX98373_R20FF_GLOBAL_SHDN, 0x00},
{MAX98373_R21FF_REV_ID, 0x42},
};
static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
unsigned int format = 0;
unsigned int invert = 0;
dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(codec->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = MAX98373_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = MAX98373_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = MAX98373_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format = MAX98373_PCM_FORMAT_TDM_MODE0;
break;
default:
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
return 0;
}
/* BCLKs per LRCLK */
static const int bclk_sel_table[] = {
32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
};
static int max98373_get_bclk_sel(int bclk)
{
int i;
/* match BCLKs per LRCLK */
for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
if (bclk_sel_table[i] == bclk)
return i + 2;
}
return 0;
}
static int max98373_set_clock(struct snd_soc_codec *codec,
struct snd_pcm_hw_params *params)
{
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98373->ch_size;
int value;
if (!max98373->tdm_mode) {
/* BCLK configuration */
value = max98373_get_bclk_sel(blr_clk_ratio);
if (!value) {
dev_err(codec->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_CLK_SETUP_BSEL_MASK,
value);
}
return 0;
}
static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(codec->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
max98373->ch_size = snd_pcm_format_width(params_format(params));
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(codec->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
break;
case 11025:
sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
break;
case 12000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
break;
case 16000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
break;
case 22050:
sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
break;
case 24000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
break;
case 32000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
break;
case 44100:
sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
break;
case 48000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
break;
default:
dev_err(codec->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98373->regmap,
MAX98373_R2027_PCM_SR_SETUP_1,
MAX98373_PCM_SR_SET1_SR_MASK,
sampling_rate);
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_SR_MASK,
sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
/* set sampling rate of IV */
if (max98373->interleave_mode &&
sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate - 3);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate);
return max98373_set_clock(codec, params);
err:
return -EINVAL;
}
static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_codec *codec = dai->codec;
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
int bsel = 0;
unsigned int chan_sz = 0;
unsigned int mask;
int x, slot_found;
if (!tx_mask && !rx_mask && !slots && !slot_width)
max98373->tdm_mode = false;
else
max98373->tdm_mode = true;
/* BCLK configuration */
bsel = max98373_get_bclk_sel(slots * slot_width);
if (bsel == 0) {
dev_err(codec->dev, "BCLK %d not supported\n",
slots * slot_width);
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_CLK_SETUP_BSEL_MASK,
bsel);
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(codec->dev, "format unsupported %d\n",
slot_width);
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
slot_found = 0;
mask = rx_mask;
for (x = 0 ; x < 16 ; x++, mask >>= 1) {
if (mask & 0x1) {
if (slot_found == 0)
regmap_update_bits(max98373->regmap,
MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
else
regmap_write(max98373->regmap,
MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
x);
slot_found++;
if (slot_found > 1)
break;
}
}
/* Tx slot Hi-Z configuration */
regmap_write(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
~tx_mask & 0xFF);
regmap_write(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
(~tx_mask & 0xFF00) >> 8);
return 0;
}
#define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98373_dai_ops = {
.set_fmt = max98373_dai_set_fmt,
.hw_params = max98373_dai_hw_params,
.set_tdm_slot = max98373_dai_tdm_slot,
};
static int max98373_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(max98373->regmap,
MAX98373_R20FF_GLOBAL_SHDN,
MAX98373_GLOBAL_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(max98373->regmap,
MAX98373_R20FF_GLOBAL_SHDN,
MAX98373_GLOBAL_EN_MASK, 0);
max98373->tdm_mode = 0;
break;
default:
return 0;
}
return 0;
}
static const char * const max98373_switch_text[] = {
"Left", "Right", "LeftRight"};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
3, max98373_switch_text);
static const struct snd_kcontrol_new max98373_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_kcontrol_new max98373_vi_control =
SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
static const struct snd_kcontrol_new max98373_spkfb_control =
SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98373_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
&max98373_vi_control),
SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
&max98373_spkfb_control),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
SND_SOC_DAPM_SIGGEN("FBMON"),
};
static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0);
static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0),
8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0),
10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0),
12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
0, 15, TLV_DB_SCALE_ITEM(0, -100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
0, 60, TLV_DB_SCALE_ITEM(0, -25, 0),
);
static bool max98373_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
case MAX98373_R2010_IRQ_CTRL:
case MAX98373_R2014_THERM_WARN_THRESH
... MAX98373_R2018_THERM_FOLDBACK_EN:
case MAX98373_R201E_PIN_DRIVE_STRENGTH
... MAX98373_R2036_SOUNDWIRE_CTRL:
case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
... MAX98373_R2047_IV_SENSE_ADC_EN:
case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
case MAX98373_R2097_BDE_L1_THRESH
... MAX98373_R209B_BDE_THRESH_HYST:
case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
... MAX98373_R20FF_GLOBAL_SHDN:
case MAX98373_R21FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R21FF_REV_ID:
return true;
default:
return false;
}
}
static const char * const max98373_output_voltage_lvl_text[] = {
"5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
"9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
};
static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
MAX98373_R203E_AMP_PATH_GAIN, 0,
max98373_output_voltage_lvl_text);
static const char * const max98373_dht_attack_rate_text[] = {
"17.5us", "35us", "70us", "140us",
"280us", "560us", "1120us", "2240us"
};
static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
MAX98373_R20D2_DHT_ATTACK_CFG, 0,
max98373_dht_attack_rate_text);
static const char * const max98373_dht_release_rate_text[] = {
"45ms", "225ms", "450ms", "1150ms",
"2250ms", "3100ms", "4500ms", "6750ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
MAX98373_R20D3_DHT_RELEASE_CFG, 0,
max98373_dht_release_rate_text);
static const char * const max98373_limiter_attack_rate_text[] = {
"10us", "20us", "40us", "80us",
"160us", "320us", "640us", "1.28ms",
"2.56ms", "5.12ms", "10.24ms", "20.48ms",
"40.96ms", "81.92ms", "16.384ms", "32.768ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
max98373_limiter_attack_rate_text);
static const char * const max98373_limiter_release_rate_text[] = {
"40us", "80us", "160us", "320us",
"640us", "1.28ms", "2.56ms", "5.120ms",
"10.24ms", "20.48ms", "40.96ms", "81.92ms",
"163.84ms", "327.68ms", "655.36ms", "1310.72ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
max98373_limiter_release_rate_text);
static const char * const max98373_ADC_samplerate_text[] = {
"333kHz", "192kHz", "64kHz", "48kHz"
};
static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
max98373_ADC_samplerate_text);
static const struct snd_kcontrol_new max98373_snd_controls[] = {
SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
MAX98373_CLOCK_MON_SHIFT, 1, 0),
SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
0, 0x7F, 0, max98373_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
SOC_ENUM("Output Voltage", max98373_out_volt_enum),
/* Dynamic Headroom Tracking */
SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
MAX98373_DHT_EN_SHIFT, 1, 0),
SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv),
SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
/* ADC configuration */
SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
MAX98373_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
MAX98373_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
0, 0x3, 0),
SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
0, 0x3, 0),
SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
/* Brownout Detection Engine */
SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
/* Limiter */
SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
MAX98373_LIMITER_EN_SHIFT, 1, 0),
SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
};
static const struct snd_soc_dapm_route max98373_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
/* Capture */
{ "VI Sense", "Switch", "VMON" },
{ "VI Sense", "Switch", "IMON" },
{ "SpkFB Sense", "Switch", "FBMON" },
{ "Voltage Sense", NULL, "VI Sense" },
{ "Current Sense", NULL, "VI Sense" },
{ "Speaker FB Sense", NULL, "SpkFB Sense" },
};
static struct snd_soc_dai_driver max98373_dai[] = {
{
.name = "max98373-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.ops = &max98373_dai_ops,
}
};
static int max98373_probe(struct snd_soc_codec *codec)
{
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
codec->control_data = max98373->regmap;
/* Software Reset */
regmap_write(max98373->regmap,
MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
/* IV default slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
0xFF);
regmap_write(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
0xFF);
/* L/R mix configuration */
regmap_write(max98373->regmap,
MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0x80);
regmap_write(max98373->regmap,
MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
0x1);
/* Set inital volume (0dB) */
regmap_write(max98373->regmap,
MAX98373_R203D_AMP_DIG_VOL_CTRL,
0x00);
regmap_write(max98373->regmap,
MAX98373_R203E_AMP_PATH_GAIN,
0x00);
/* Enable DC blocker */
regmap_write(max98373->regmap,
MAX98373_R203F_AMP_DSP_CFG,
0x3);
/* Enable IMON VMON DC blocker */
regmap_write(max98373->regmap,
MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
0x7);
/* voltage, current slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2022_PCM_TX_SRC_1,
(max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
max98373->v_slot) & 0xFF);
if (max98373->v_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->v_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->v_slot - 8), 0);
if (max98373->i_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->i_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->i_slot - 8), 0);
/* speaker feedback slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2023_PCM_TX_SRC_2,
max98373->spkfb_slot & 0xFF);
/* Set interleave mode */
if (max98373->interleave_mode)
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
/* Speaker enable */
regmap_update_bits(max98373->regmap,
MAX98373_R2043_AMP_EN,
MAX98373_SPK_EN_MASK, 1);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int max98373_suspend(struct device *dev)
{
struct max98373_priv *max98373 = dev_get_drvdata(dev);
regcache_cache_only(max98373->regmap, true);
regcache_mark_dirty(max98373->regmap);
return 0;
}
static int max98373_resume(struct device *dev)
{
struct max98373_priv *max98373 = dev_get_drvdata(dev);
regmap_write(max98373->regmap,
MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
regcache_cache_only(max98373->regmap, false);
regcache_sync(max98373->regmap);
return 0;
}
#endif
static const struct dev_pm_ops max98373_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
};
static const struct snd_soc_codec_driver soc_codec_dev_max98373 = {
.probe = max98373_probe,
.component_driver = {
.controls = max98373_snd_controls,
.num_controls = ARRAY_SIZE(max98373_snd_controls),
.dapm_widgets = max98373_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
.dapm_routes = max98373_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
},
};
static const struct regmap_config max98373_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98373_R21FF_REV_ID,
.reg_defaults = max98373_reg,
.num_reg_defaults = ARRAY_SIZE(max98373_reg),
.readable_reg = max98373_readable_register,
.volatile_reg = max98373_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static void max98373_slot_config(struct i2c_client *i2c,
struct max98373_priv *max98373)
{
int value;
struct device *dev = &i2c->dev;
if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
max98373->v_slot = value & 0xF;
else
max98373->v_slot = 0;
if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
max98373->i_slot = value & 0xF;
else
max98373->i_slot = 1;
if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
max98373->spkfb_slot = value & 0xF;
else
max98373->spkfb_slot = 2;
}
static int max98373_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
int ret = 0;
int reg = 0;
struct max98373_priv *max98373 = NULL;
max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
if (!max98373) {
ret = -ENOMEM;
return ret;
}
i2c_set_clientdata(i2c, max98373);
/* update interleave mode info */
if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
max98373->interleave_mode = 1;
else
max98373->interleave_mode = 0;
/* regmap initialization */
max98373->regmap
= devm_regmap_init_i2c(i2c, &max98373_regmap);
if (IS_ERR(max98373->regmap)) {
ret = PTR_ERR(max98373->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
/* Check Revision ID */
ret = regmap_read(max98373->regmap,
MAX98373_R21FF_REV_ID, &reg);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
return ret;
}
dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
/* voltage/current slot configuration */
max98373_slot_config(i2c, max98373);
/* codec registeration */
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98373,
max98373_dai, ARRAY_SIZE(max98373_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
return ret;
}
static int max98373_i2c_remove(struct i2c_client *client)
{
snd_soc_unregister_codec(&client->dev);
return 0;
}
static const struct i2c_device_id max98373_i2c_id[] = {
{ "max98373", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98373_of_match[] = {
{ .compatible = "maxim,max98373", },
{ }
};
MODULE_DEVICE_TABLE(of, max98373_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98373_acpi_match[] = {
{ "MX98373", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
#endif
static struct i2c_driver max98373_i2c_driver = {
.driver = {
.name = "max98373",
.of_match_table = of_match_ptr(max98373_of_match),
.acpi_match_table = ACPI_PTR(max98373_acpi_match),
.pm = &max98373_pm,
},
.probe = max98373_i2c_probe,
.remove = max98373_i2c_remove,
.id_table = max98373_i2c_id,
};
module_i2c_driver(max98373_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
MODULE_LICENSE("GPL");

212
sound/soc/codecs/max98373.h Normal file
View File

@ -0,0 +1,212 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2017, Maxim Integrated */
#ifndef _MAX98373_H
#define _MAX98373_H
#define MAX98373_R2000_SW_RESET 0x2000
#define MAX98373_R2001_INT_RAW1 0x2001
#define MAX98373_R2002_INT_RAW2 0x2002
#define MAX98373_R2003_INT_RAW3 0x2003
#define MAX98373_R2004_INT_STATE1 0x2004
#define MAX98373_R2005_INT_STATE2 0x2005
#define MAX98373_R2006_INT_STATE3 0x2006
#define MAX98373_R2007_INT_FLAG1 0x2007
#define MAX98373_R2008_INT_FLAG2 0x2008
#define MAX98373_R2009_INT_FLAG3 0x2009
#define MAX98373_R200A_INT_EN1 0x200A
#define MAX98373_R200B_INT_EN2 0x200B
#define MAX98373_R200C_INT_EN3 0x200C
#define MAX98373_R200D_INT_FLAG_CLR1 0x200D
#define MAX98373_R200E_INT_FLAG_CLR2 0x200E
#define MAX98373_R200F_INT_FLAG_CLR3 0x200F
#define MAX98373_R2010_IRQ_CTRL 0x2010
#define MAX98373_R2014_THERM_WARN_THRESH 0x2014
#define MAX98373_R2015_THERM_SHDN_THRESH 0x2015
#define MAX98373_R2016_THERM_HYSTERESIS 0x2016
#define MAX98373_R2017_THERM_FOLDBACK_SET 0x2017
#define MAX98373_R2018_THERM_FOLDBACK_EN 0x2018
#define MAX98373_R201E_PIN_DRIVE_STRENGTH 0x201E
#define MAX98373_R2020_PCM_TX_HIZ_EN_1 0x2020
#define MAX98373_R2021_PCM_TX_HIZ_EN_2 0x2021
#define MAX98373_R2022_PCM_TX_SRC_1 0x2022
#define MAX98373_R2023_PCM_TX_SRC_2 0x2023
#define MAX98373_R2024_PCM_DATA_FMT_CFG 0x2024
#define MAX98373_R2025_AUDIO_IF_MODE 0x2025
#define MAX98373_R2026_PCM_CLOCK_RATIO 0x2026
#define MAX98373_R2027_PCM_SR_SETUP_1 0x2027
#define MAX98373_R2028_PCM_SR_SETUP_2 0x2028
#define MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 0x2029
#define MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2 0x202A
#define MAX98373_R202B_PCM_RX_EN 0x202B
#define MAX98373_R202C_PCM_TX_EN 0x202C
#define MAX98373_R202E_ICC_RX_CH_EN_1 0x202E
#define MAX98373_R202F_ICC_RX_CH_EN_2 0x202F
#define MAX98373_R2030_ICC_TX_HIZ_EN_1 0x2030
#define MAX98373_R2031_ICC_TX_HIZ_EN_2 0x2031
#define MAX98373_R2032_ICC_LINK_EN_CFG 0x2032
#define MAX98373_R2034_ICC_TX_CNTL 0x2034
#define MAX98373_R2035_ICC_TX_EN 0x2035
#define MAX98373_R2036_SOUNDWIRE_CTRL 0x2036
#define MAX98373_R203D_AMP_DIG_VOL_CTRL 0x203D
#define MAX98373_R203E_AMP_PATH_GAIN 0x203E
#define MAX98373_R203F_AMP_DSP_CFG 0x203F
#define MAX98373_R2040_TONE_GEN_CFG 0x2040
#define MAX98373_R2041_AMP_CFG 0x2041
#define MAX98373_R2042_AMP_EDGE_RATE_CFG 0x2042
#define MAX98373_R2043_AMP_EN 0x2043
#define MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 0x2046
#define MAX98373_R2047_IV_SENSE_ADC_EN 0x2047
#define MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 0x2051
#define MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG 0x2052
#define MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG 0x2053
#define MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK 0x2054
#define MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK 0x2055
#define MAX98373_R2056_MEAS_ADC_PVDD_CH_EN 0x2056
#define MAX98373_R2090_BDE_LVL_HOLD 0x2090
#define MAX98373_R2091_BDE_GAIN_ATK_REL_RATE 0x2091
#define MAX98373_R2092_BDE_CLIPPER_MODE 0x2092
#define MAX98373_R2097_BDE_L1_THRESH 0x2097
#define MAX98373_R2098_BDE_L2_THRESH 0x2098
#define MAX98373_R2099_BDE_L3_THRESH 0x2099
#define MAX98373_R209A_BDE_L4_THRESH 0x209A
#define MAX98373_R209B_BDE_THRESH_HYST 0x209B
#define MAX98373_R20A8_BDE_L1_CFG_1 0x20A8
#define MAX98373_R20A9_BDE_L1_CFG_2 0x20A9
#define MAX98373_R20AA_BDE_L1_CFG_3 0x20AA
#define MAX98373_R20AB_BDE_L2_CFG_1 0x20AB
#define MAX98373_R20AC_BDE_L2_CFG_2 0x20AC
#define MAX98373_R20AD_BDE_L2_CFG_3 0x20AD
#define MAX98373_R20AE_BDE_L3_CFG_1 0x20AE
#define MAX98373_R20AF_BDE_L3_CFG_2 0x20AF
#define MAX98373_R20B0_BDE_L3_CFG_3 0x20B0
#define MAX98373_R20B1_BDE_L4_CFG_1 0x20B1
#define MAX98373_R20B2_BDE_L4_CFG_2 0x20B2
#define MAX98373_R20B3_BDE_L4_CFG_3 0x20B3
#define MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE 0x20B4
#define MAX98373_R20B5_BDE_EN 0x20B5
#define MAX98373_R20B6_BDE_CUR_STATE_READBACK 0x20B6
#define MAX98373_R20D1_DHT_CFG 0x20D1
#define MAX98373_R20D2_DHT_ATTACK_CFG 0x20D2
#define MAX98373_R20D3_DHT_RELEASE_CFG 0x20D3
#define MAX98373_R20D4_DHT_EN 0x20D4
#define MAX98373_R20E0_LIMITER_THRESH_CFG 0x20E0
#define MAX98373_R20E1_LIMITER_ATK_REL_RATES 0x20E1
#define MAX98373_R20E2_LIMITER_EN 0x20E2
#define MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 0x20FE
#define MAX98373_R20FF_GLOBAL_SHDN 0x20FF
#define MAX98373_R21FF_REV_ID 0x21FF
/* MAX98373_R2022_PCM_TX_SRC_1 */
#define MAX98373_PCM_TX_CH_SRC_A_V_SHIFT (0)
#define MAX98373_PCM_TX_CH_SRC_A_I_SHIFT (4)
/* MAX98373_R2024_PCM_DATA_FMT_CFG */
#define MAX98373_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
#define MAX98373_PCM_MODE_CFG_FORMAT_SHIFT (3)
#define MAX98373_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
#define MAX98373_PCM_FORMAT_I2S (0x0 << 0)
#define MAX98373_PCM_FORMAT_LJ (0x1 << 0)
#define MAX98373_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
#define MAX98373_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
#define MAX98373_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
#define MAX98373_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
#define MAX98373_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
#define MAX98373_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
#define MAX98373_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
/* MAX98373_R2026_PCM_CLOCK_RATIO */
#define MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)
#define MAX98373_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
/* MAX98373_R2027_PCM_SR_SETUP_1 */
#define MAX98373_PCM_SR_SET1_SR_MASK (0xF << 0)
#define MAX98373_PCM_SR_SET1_SR_8000 (0x0 << 0)
#define MAX98373_PCM_SR_SET1_SR_11025 (0x1 << 0)
#define MAX98373_PCM_SR_SET1_SR_12000 (0x2 << 0)
#define MAX98373_PCM_SR_SET1_SR_16000 (0x3 << 0)
#define MAX98373_PCM_SR_SET1_SR_22050 (0x4 << 0)
#define MAX98373_PCM_SR_SET1_SR_24000 (0x5 << 0)
#define MAX98373_PCM_SR_SET1_SR_32000 (0x6 << 0)
#define MAX98373_PCM_SR_SET1_SR_44100 (0x7 << 0)
#define MAX98373_PCM_SR_SET1_SR_48000 (0x8 << 0)
/* MAX98373_R2028_PCM_SR_SETUP_2 */
#define MAX98373_PCM_SR_SET2_SR_MASK (0xF << 4)
#define MAX98373_PCM_SR_SET2_SR_SHIFT (4)
#define MAX98373_PCM_SR_SET2_IVADC_SR_MASK (0xF << 0)
/* MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 */
#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
#define MAX98373_PCM_TO_SPK_CH0_SRC_MASK (0xF << 0)
/* MAX98373_R203E_AMP_PATH_GAIN */
#define MAX98373_SPK_DIGI_GAIN_MASK (0xF << 4)
#define MAX98373_SPK_DIGI_GAIN_SHIFT (4)
#define MAX98373_FS_GAIN_MAX_MASK (0xF << 0)
#define MAX98373_FS_GAIN_MAX_SHIFT (0)
/* MAX98373_R203F_AMP_DSP_CFG */
#define MAX98373_AMP_DSP_CFG_DCBLK_SHIFT (0)
#define MAX98373_AMP_DSP_CFG_DITH_SHIFT (1)
#define MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT (2)
#define MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT (3)
#define MAX98373_AMP_DSP_CFG_DAC_INV_SHIFT (5)
#define MAX98373_AMP_VOL_SEL_SHIFT (7)
/* MAX98373_R2043_AMP_EN */
#define MAX98373_SPKFB_EN_MASK (0x1 << 1)
#define MAX98373_SPK_EN_MASK (0x1 << 0)
#define MAX98373_SPKFB_EN_SHIFT (1)
/*MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG */
#define MAX98373_FLT_EN_SHIFT (4)
/* MAX98373_R20B2_BDE_L4_CFG_2 */
#define MAX98373_LVL4_MUTE_EN_SHIFT (7)
#define MAX98373_LVL4_HOLD_EN_SHIFT (6)
/* MAX98373_R20B5_BDE_EN */
#define MAX98373_BDE_EN_SHIFT (0)
/* MAX98373_R20D1_DHT_CFG */
#define MAX98373_DHT_SPK_GAIN_MIN_SHIFT (4)
#define MAX98373_DHT_ROT_PNT_SHIFT (0)
/* MAX98373_R20D2_DHT_ATTACK_CFG */
#define MAX98373_DHT_ATTACK_STEP_SHIFT (3)
#define MAX98373_DHT_ATTACK_RATE_SHIFT (0)
/* MAX98373_R20D3_DHT_RELEASE_CFG */
#define MAX98373_DHT_RELEASE_STEP_SHIFT (3)
#define MAX98373_DHT_RELEASE_RATE_SHIFT (0)
/* MAX98373_R20D4_DHT_EN */
#define MAX98373_DHT_EN_SHIFT (0)
/* MAX98373_R20E0_LIMITER_THRESH_CFG */
#define MAX98373_LIMITER_THRESH_SHIFT (2)
#define MAX98373_LIMITER_THRESH_SRC_SHIFT (0)
/* MAX98373_R20E2_LIMITER_EN */
#define MAX98373_LIMITER_EN_SHIFT (0)
/* MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG */
#define MAX98373_CLOCK_MON_SHIFT (0)
/* MAX98373_R20FF_GLOBAL_SHDN */
#define MAX98373_GLOBAL_EN_MASK (0x1 << 0)
/* MAX98373_R2000_SW_RESET */
#define MAX98373_SOFT_RESET (0x1 << 0)
struct max98373_priv {
struct regmap *regmap;
unsigned int v_slot;
unsigned int i_slot;
unsigned int spkfb_slot;
bool interleave_mode;
unsigned int ch_size;
bool tdm_mode;
};
#endif

2
sound/soc/codecs/max98926.c
View File

@ -490,7 +490,7 @@ static int max98926_probe(struct snd_soc_codec *codec)
struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
max98926->codec = codec;
codec->control_data = max98926->regmap;
/* Hi-Z all the slots */
regmap_write(max98926->regmap, MAX98926_DOUT_HIZ_CFG4, 0xF0);
return 0;

1
sound/soc/codecs/max98927.c
View File

@ -682,7 +682,6 @@ static int max98927_probe(struct snd_soc_codec *codec)
struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
max98927->codec = codec;
codec->control_data = max98927->regmap;
/* Software Reset */
regmap_write(max98927->regmap,

9
sound/soc/codecs/mc13783.c
View File

@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec)
{
struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
snd_soc_codec_init_regmap(codec,
dev_get_regmap(codec->dev->parent, NULL));
/* these are the reset values */
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = {
}
};
static struct regmap *mc13783_get_regmap(struct device *dev)
{
return dev_get_regmap(dev->parent, NULL);
}
static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
.probe = mc13783_probe,
.remove = mc13783_remove,
.get_regmap = mc13783_get_regmap,
.component_driver = {
.controls = mc13783_control_list,
.num_controls = ARRAY_SIZE(mc13783_control_list),

8
sound/soc/codecs/msm8916-wcd-analog.c
View File

@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec)
return err;
}
snd_soc_codec_init_regmap(codec,
dev_get_regmap(codec->dev->parent, NULL));
snd_soc_codec_set_drvdata(codec, priv);
priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);
priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec,
return 0;
}
static struct regmap *pm8916_get_regmap(struct device *dev)
{
return dev_get_regmap(dev->parent, NULL);
}
static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
{
struct pm8916_wcd_analog_priv *priv = arg;
@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = {
.probe = pm8916_wcd_analog_probe,
.remove = pm8916_wcd_analog_remove,
.set_jack = pm8916_wcd_analog_set_jack,
.get_regmap = pm8916_get_regmap,
.component_driver = {
.controls = pm8916_wcd_analog_snd_controls,
.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),

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