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iommu/arm-smmu: Use correct address mask for CMD_TLBI_S2_IPA
Stage-2 TLBI by IPA takes a 48-bit address field, as opposed to the 64-bit field used by the VA-based invalidation commands. This patch re-jigs the SMMUv3 command construction code so that the address field is correctly masked. Signed-off-by: Will Deacon <will.deacon@arm.com>
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1 changed files with 6 additions and 3 deletions
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@ -343,7 +343,8 @@
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#define CMDQ_TLBI_0_VMID_SHIFT 32
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#define CMDQ_TLBI_0_ASID_SHIFT 48
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#define CMDQ_TLBI_1_LEAF (1UL << 0)
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#define CMDQ_TLBI_1_ADDR_MASK ~0xfffUL
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#define CMDQ_TLBI_1_VA_MASK ~0xfffUL
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#define CMDQ_TLBI_1_IPA_MASK 0xfffffffff000UL
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#define CMDQ_PRI_0_SSID_SHIFT 12
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#define CMDQ_PRI_0_SSID_MASK 0xfffffUL
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@ -771,11 +772,13 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
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break;
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case CMDQ_OP_TLBI_NH_VA:
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cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
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/* Fallthrough */
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cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
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cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;
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break;
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case CMDQ_OP_TLBI_S2_IPA:
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cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;
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cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
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cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_ADDR_MASK;
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cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;
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break;
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case CMDQ_OP_TLBI_NH_ASID:
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cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
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