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spi: switch to use modern name (part4) 

Merge series from Yang Yingliang <yangyingliang@huawei.com>:

I'm trying to rename the legacy name to modern name used in SPI drivers,
this is part4 patchset.

After introducing devm_spi_alloc_host/spi_alloc_host(), the legacy
named function devm_spi_alloc_master/spi_alloc_master() can be replaced.
And also change other legacy name master/slave to modern name host/target
or controller. Each patch compile test passed.
This commit is contained in:
Mark Brown 2023-08-22 00:06:26 +01:00
parent 246f74bb11 557efcf4c6
commit 1c351c236a
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
25 changed files with 626 additions and 626 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
drivers/spi/spi-orion.c
View File

@ -90,7 +90,7 @@ struct orion_child_options {
};
struct orion_spi {
struct spi_master *master;
struct spi_controller *host;
void __iomem *base;
struct clk *clk;
struct clk *axi_clk;
@ -141,7 +141,7 @@ static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
struct orion_spi *orion_spi;
const struct orion_spi_dev *devdata;
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
devdata = orion_spi->devdata;
tclk_hz = clk_get_rate(orion_spi->clk);
@ -235,7 +235,7 @@ orion_spi_mode_set(struct spi_device *spi)
u32 reg;
struct orion_spi *orion_spi;
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
reg &= ~ORION_SPI_MODE_MASK;
@ -257,7 +257,7 @@ orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
u32 reg;
struct orion_spi *orion_spi;
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
/*
* Erratum description: (Erratum NO. FE-9144572) The device
@ -297,7 +297,7 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
unsigned int bits_per_word = spi->bits_per_word;
int rc;
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
if ((t != NULL) && t->speed_hz)
speed = t->speed_hz;
@ -330,7 +330,7 @@ static void orion_spi_set_cs(struct spi_device *spi, bool enable)
void __iomem *ctrl_reg;
u32 val;
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
ctrl_reg = spi_reg(orion_spi, ORION_SPI_IF_CTRL_REG);
val = readl(ctrl_reg);
@ -388,7 +388,7 @@ orion_spi_write_read_8bit(struct spi_device *spi,
cs_single_byte = spi->mode & SPI_CS_WORD;
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
if (cs_single_byte)
orion_spi_set_cs(spi, 0);
@ -439,7 +439,7 @@ orion_spi_write_read_16bit(struct spi_device *spi,
return -1;
}
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
@ -475,7 +475,7 @@ orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
word_len = spi->bits_per_word;
count = xfer->len;
orion_spi = spi_master_get_devdata(spi->master);
orion_spi = spi_controller_get_devdata(spi->controller);
/*
* Use SPI direct write mode if base address is available
@ -528,7 +528,7 @@ out:
return xfer->len - count;
}
static int orion_spi_transfer_one(struct spi_master *master,
static int orion_spi_transfer_one(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *t)
{
@ -548,7 +548,7 @@ static int orion_spi_setup(struct spi_device *spi)
{
int ret;
#ifdef CONFIG_PM
struct orion_spi *orion_spi = spi_master_get_devdata(spi->master);
struct orion_spi *orion_spi = spi_controller_get_devdata(spi->controller);
struct device *dev = orion_spi->dev;
orion_spi_runtime_resume(dev);
@ -644,44 +644,44 @@ MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
static int orion_spi_probe(struct platform_device *pdev)
{
const struct orion_spi_dev *devdata;
struct spi_master *master;
struct spi_controller *host;
struct orion_spi *spi;
struct resource *r;
unsigned long tclk_hz;
int status = 0;
struct device_node *np;
master = spi_alloc_master(&pdev->dev, sizeof(*spi));
if (master == NULL) {
dev_dbg(&pdev->dev, "master allocation failed\n");
host = spi_alloc_host(&pdev->dev, sizeof(*spi));
if (host == NULL) {
dev_dbg(&pdev->dev, "host allocation failed\n");
return -ENOMEM;
}
if (pdev->id != -1)
master->bus_num = pdev->id;
host->bus_num = pdev->id;
if (pdev->dev.of_node) {
u32 cell_index;
if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
&cell_index))
master->bus_num = cell_index;
host->bus_num = cell_index;
}
/* we support all 4 SPI modes and LSB first option */
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;
master->set_cs = orion_spi_set_cs;
master->transfer_one = orion_spi_transfer_one;
master->num_chipselect = ORION_NUM_CHIPSELECTS;
master->setup = orion_spi_setup;
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
master->auto_runtime_pm = true;
master->use_gpio_descriptors = true;
master->flags = SPI_CONTROLLER_GPIO_SS;
host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;
host->set_cs = orion_spi_set_cs;
host->transfer_one = orion_spi_transfer_one;
host->num_chipselect = ORION_NUM_CHIPSELECTS;
host->setup = orion_spi_setup;
host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
host->auto_runtime_pm = true;
host->use_gpio_descriptors = true;
host->flags = SPI_CONTROLLER_GPIO_SS;
platform_set_drvdata(pdev, master);
platform_set_drvdata(pdev, host);
spi = spi_master_get_devdata(master);
spi->master = master;
spi = spi_controller_get_devdata(host);
spi->host = host;
spi->dev = &pdev->dev;
devdata = device_get_match_data(&pdev->dev);
@ -718,14 +718,14 @@ static int orion_spi_probe(struct platform_device *pdev)
*/
if (of_device_is_compatible(pdev->dev.of_node,
"marvell,armada-370-spi"))
master->max_speed_hz = min(devdata->max_hz,
host->max_speed_hz = min(devdata->max_hz,
DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
else if (devdata->min_divisor)
master->max_speed_hz =
host->max_speed_hz =
DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
else
master->max_speed_hz = devdata->max_hz;
master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
host->max_speed_hz = devdata->max_hz;
host->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
if (IS_ERR(spi->base)) {
@ -784,8 +784,8 @@ static int orion_spi_probe(struct platform_device *pdev)
if (status < 0)
goto out_rel_pm;
master->dev.of_node = pdev->dev.of_node;
status = spi_register_master(master);
host->dev.of_node = pdev->dev.of_node;
status = spi_register_controller(host);
if (status < 0)
goto out_rel_pm;
@ -798,21 +798,21 @@ out_rel_axi_clk:
out_rel_clk:
clk_disable_unprepare(spi->clk);
out:
spi_master_put(master);
spi_controller_put(host);
return status;
}
static void orion_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct orion_spi *spi = spi_master_get_devdata(master);
struct spi_controller *host = platform_get_drvdata(pdev);
struct orion_spi *spi = spi_controller_get_devdata(host);
pm_runtime_get_sync(&pdev->dev);
clk_disable_unprepare(spi->axi_clk);
clk_disable_unprepare(spi->clk);
spi_unregister_master(master);
spi_unregister_controller(host);
pm_runtime_disable(&pdev->dev);
}
@ -821,8 +821,8 @@ MODULE_ALIAS("platform:" DRIVER_NAME);
#ifdef CONFIG_PM
static int orion_spi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct orion_spi *spi = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct orion_spi *spi = spi_controller_get_devdata(host);
clk_disable_unprepare(spi->axi_clk);
clk_disable_unprepare(spi->clk);
@ -831,8 +831,8 @@ static int orion_spi_runtime_suspend(struct device *dev)
static int orion_spi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct orion_spi *spi = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct orion_spi *spi = spi_controller_get_devdata(host);
if (!IS_ERR(spi->axi_clk))
clk_prepare_enable(spi->axi_clk);

14
drivers/spi/spi-pci1xxxx.c
View File

@ -65,7 +65,7 @@ struct pci1xxxx_spi_internal {
bool spi_xfer_in_progress;
int irq;
struct completion spi_xfer_done;
struct spi_master *spi_host;
struct spi_controller *spi_host;
struct pci1xxxx_spi *parent;
struct {
unsigned int dev_sel : 3;
@ -250,7 +250,7 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
struct pci1xxxx_spi_internal *spi_sub_ptr;
struct device *dev = &pdev->dev;
struct pci1xxxx_spi *spi_bus;
struct spi_master *spi_host;
struct spi_controller *spi_host;
u32 regval;
int ret;
@ -276,7 +276,7 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
sizeof(struct pci1xxxx_spi_internal),
GFP_KERNEL);
spi_sub_ptr = spi_bus->spi_int[iter];
spi_sub_ptr->spi_host = devm_spi_alloc_master(dev, sizeof(struct spi_master));
spi_sub_ptr->spi_host = devm_spi_alloc_host(dev, sizeof(struct spi_controller));
if (!spi_sub_ptr->spi_host)
return -ENOMEM;
@ -366,8 +366,8 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;
spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ;
spi_host->flags = SPI_CONTROLLER_MUST_TX;
spi_master_set_devdata(spi_host, spi_sub_ptr);
ret = devm_spi_register_master(dev, spi_host);
spi_controller_set_devdata(spi_host, spi_sub_ptr);
ret = devm_spi_register_controller(dev, spi_host);
if (ret)
goto error;
}
@ -415,7 +415,7 @@ static int pci1xxxx_spi_resume(struct device *dev)
for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
spi_sub_ptr = spi_ptr->spi_int[iter];
spi_master_resume(spi_sub_ptr->spi_host);
spi_controller_resume(spi_sub_ptr->spi_host);
writel(regval, spi_ptr->reg_base +
SPI_MST_EVENT_MASK_REG_OFFSET(iter));
@ -441,7 +441,7 @@ static int pci1xxxx_spi_suspend(struct device *dev)
/* Store existing config before suspend */
store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);
spi_master_suspend(spi_sub_ptr->spi_host);
spi_controller_suspend(spi_sub_ptr->spi_host);
writel(reg1, spi_ptr->reg_base +
SPI_MST_EVENT_MASK_REG_OFFSET(iter));
}

84
drivers/spi/spi-pic32-sqi.c
View File

@ -139,7 +139,7 @@ struct pic32_sqi {
void __iomem *regs;
struct clk *sys_clk;
struct clk *base_clk; /* drives spi clock */
struct spi_master *master;
struct spi_controller *host;
int irq;
struct completion xfer_done;
struct ring_desc *ring;
@ -316,9 +316,9 @@ static int pic32_sqi_one_transfer(struct pic32_sqi *sqi,
return 0;
}
static int pic32_sqi_prepare_hardware(struct spi_master *master)
static int pic32_sqi_prepare_hardware(struct spi_controller *host)
{
struct pic32_sqi *sqi = spi_master_get_devdata(master);
struct pic32_sqi *sqi = spi_controller_get_devdata(host);
/* enable spi interface */
pic32_setbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
@ -328,7 +328,7 @@ static int pic32_sqi_prepare_hardware(struct spi_master *master)
return 0;
}
static bool pic32_sqi_can_dma(struct spi_master *master,
static bool pic32_sqi_can_dma(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *x)
{
@ -336,7 +336,7 @@ static bool pic32_sqi_can_dma(struct spi_master *master,
return true;
}
static int pic32_sqi_one_message(struct spi_master *master,
static int pic32_sqi_one_message(struct spi_controller *host,
struct spi_message *msg)
{
struct spi_device *spi = msg->spi;
@ -347,7 +347,7 @@ static int pic32_sqi_one_message(struct spi_master *master,
unsigned long timeout;
u32 val;
sqi = spi_master_get_devdata(master);
sqi = spi_controller_get_devdata(host);
reinit_completion(&sqi->xfer_done);
msg->actual_length = 0;
@ -412,7 +412,7 @@ static int pic32_sqi_one_message(struct spi_master *master,
/* wait for xfer completion */
timeout = wait_for_completion_timeout(&sqi->xfer_done, 5 * HZ);
if (timeout == 0) {
dev_err(&sqi->master->dev, "wait timedout/interrupted\n");
dev_err(&sqi->host->dev, "wait timedout/interrupted\n");
ret = -ETIMEDOUT;
msg->status = ret;
} else {
@ -434,14 +434,14 @@ xfer_out:
/* release ring descr */
ring_desc_put(sqi, rdesc);
}
spi_finalize_current_message(spi->master);
spi_finalize_current_message(spi->controller);
return ret;
}
static int pic32_sqi_unprepare_hardware(struct spi_master *master)
static int pic32_sqi_unprepare_hardware(struct spi_controller *host)
{
struct pic32_sqi *sqi = spi_master_get_devdata(master);
struct pic32_sqi *sqi = spi_controller_get_devdata(host);
/* disable clk */
pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
@ -458,18 +458,18 @@ static int ring_desc_ring_alloc(struct pic32_sqi *sqi)
int i;
/* allocate coherent DMAable memory for hardware buffer descriptors. */
sqi->bd = dma_alloc_coherent(&sqi->master->dev,
sqi->bd = dma_alloc_coherent(&sqi->host->dev,
sizeof(*bd) * PESQI_BD_COUNT,
&sqi->bd_dma, GFP_KERNEL);
if (!sqi->bd) {
dev_err(&sqi->master->dev, "failed allocating dma buffer\n");
dev_err(&sqi->host->dev, "failed allocating dma buffer\n");
return -ENOMEM;
}
/* allocate software ring descriptors */
sqi->ring = kcalloc(PESQI_BD_COUNT, sizeof(*rdesc), GFP_KERNEL);
if (!sqi->ring) {
dma_free_coherent(&sqi->master->dev,
dma_free_coherent(&sqi->host->dev,
sizeof(*bd) * PESQI_BD_COUNT,
sqi->bd, sqi->bd_dma);
return -ENOMEM;
@ -498,7 +498,7 @@ static int ring_desc_ring_alloc(struct pic32_sqi *sqi)
static void ring_desc_ring_free(struct pic32_sqi *sqi)
{
dma_free_coherent(&sqi->master->dev,
dma_free_coherent(&sqi->host->dev,
sizeof(struct buf_desc) * PESQI_BD_COUNT,
sqi->bd, sqi->bd_dma);
kfree(sqi->ring);
@ -568,28 +568,28 @@ static void pic32_sqi_hw_init(struct pic32_sqi *sqi)
static int pic32_sqi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct spi_controller *host;
struct pic32_sqi *sqi;
int ret;
master = spi_alloc_master(&pdev->dev, sizeof(*sqi));
if (!master)
host = spi_alloc_host(&pdev->dev, sizeof(*sqi));
if (!host)
return -ENOMEM;
sqi = spi_master_get_devdata(master);
sqi->master = master;
sqi = spi_controller_get_devdata(host);
sqi->host = host;
sqi->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sqi->regs)) {
ret = PTR_ERR(sqi->regs);
goto err_free_master;
goto err_free_host;
}
/* irq */
sqi->irq = platform_get_irq(pdev, 0);
if (sqi->irq < 0) {
ret = sqi->irq;
goto err_free_master;
goto err_free_host;
}
/* clocks */
@ -597,27 +597,27 @@ static int pic32_sqi_probe(struct platform_device *pdev)
if (IS_ERR(sqi->sys_clk)) {
ret = PTR_ERR(sqi->sys_clk);
dev_err(&pdev->dev, "no sys_clk ?\n");
goto err_free_master;
goto err_free_host;
}
sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck");
if (IS_ERR(sqi->base_clk)) {
ret = PTR_ERR(sqi->base_clk);
dev_err(&pdev->dev, "no base clk ?\n");
goto err_free_master;
goto err_free_host;
}
ret = clk_prepare_enable(sqi->sys_clk);
if (ret) {
dev_err(&pdev->dev, "sys clk enable failed\n");
goto err_free_master;
goto err_free_host;
}
ret = clk_prepare_enable(sqi->base_clk);
if (ret) {
dev_err(&pdev->dev, "base clk enable failed\n");
clk_disable_unprepare(sqi->sys_clk);
goto err_free_master;
goto err_free_host;
}
init_completion(&sqi->xfer_done);
@ -640,24 +640,24 @@ static int pic32_sqi_probe(struct platform_device *pdev)
goto err_free_ring;
}
/* register master */
master->num_chipselect = 2;
master->max_speed_hz = clk_get_rate(sqi->base_clk);
master->dma_alignment = 32;
master->max_dma_len = PESQI_BD_BUF_LEN_MAX;
master->dev.of_node = pdev->dev.of_node;
master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL |
/* register host */
host->num_chipselect = 2;
host->max_speed_hz = clk_get_rate(sqi->base_clk);
host->dma_alignment = 32;
host->max_dma_len = PESQI_BD_BUF_LEN_MAX;
host->dev.of_node = pdev->dev.of_node;
host->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL |
SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD;
master->flags = SPI_CONTROLLER_HALF_DUPLEX;
master->can_dma = pic32_sqi_can_dma;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
master->transfer_one_message = pic32_sqi_one_message;
master->prepare_transfer_hardware = pic32_sqi_prepare_hardware;
master->unprepare_transfer_hardware = pic32_sqi_unprepare_hardware;
host->flags = SPI_CONTROLLER_HALF_DUPLEX;
host->can_dma = pic32_sqi_can_dma;
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
host->transfer_one_message = pic32_sqi_one_message;
host->prepare_transfer_hardware = pic32_sqi_prepare_hardware;
host->unprepare_transfer_hardware = pic32_sqi_unprepare_hardware;
ret = devm_spi_register_master(&pdev->dev, master);
ret = devm_spi_register_controller(&pdev->dev, host);
if (ret) {
dev_err(&master->dev, "failed registering spi master\n");
dev_err(&host->dev, "failed registering spi host\n");
free_irq(sqi->irq, sqi);
goto err_free_ring;
}
@ -673,8 +673,8 @@ err_disable_clk:
clk_disable_unprepare(sqi->base_clk);
clk_disable_unprepare(sqi->sys_clk);
err_free_master:
spi_master_put(master);
err_free_host:
spi_controller_put(host);
return ret;
}

152
drivers/spi/spi-pic32.c
View File

@ -100,7 +100,7 @@ struct pic32_spi {
int tx_irq;
u32 fifo_n_byte; /* FIFO depth in bytes */
struct clk *clk;
struct spi_master *master;
struct spi_controller *host;
/* Current controller setting */
u32 speed_hz; /* spi-clk rate */
u32 mode;
@ -224,9 +224,9 @@ static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg)
disable_irq_nosync(pic32s->tx_irq);
/* Show err message and abort xfer with err */
dev_err(&pic32s->master->dev, "%s\n", msg);
if (pic32s->master->cur_msg)
pic32s->master->cur_msg->status = -EIO;
dev_err(&pic32s->host->dev, "%s\n", msg);
if (pic32s->host->cur_msg)
pic32s->host->cur_msg->status = -EIO;
complete(&pic32s->xfer_done);
}
@ -250,7 +250,7 @@ static irqreturn_t pic32_spi_fault_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
if (!pic32s->master->cur_msg) {
if (!pic32s->host->cur_msg) {
pic32_err_stop(pic32s, "err_irq: no mesg");
return IRQ_NONE;
}
@ -300,16 +300,16 @@ static void pic32_spi_dma_rx_notify(void *data)
static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
struct spi_transfer *xfer)
{
struct spi_master *master = pic32s->master;
struct spi_controller *host = pic32s->host;
struct dma_async_tx_descriptor *desc_rx;
struct dma_async_tx_descriptor *desc_tx;
dma_cookie_t cookie;
int ret;
if (!master->dma_rx || !master->dma_tx)
if (!host->dma_rx || !host->dma_tx)
return -ENODEV;
desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
desc_rx = dmaengine_prep_slave_sg(host->dma_rx,
xfer->rx_sg.sgl,
xfer->rx_sg.nents,
DMA_DEV_TO_MEM,
@ -319,7 +319,7 @@ static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
goto err_dma;
}
desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
desc_tx = dmaengine_prep_slave_sg(host->dma_tx,
xfer->tx_sg.sgl,
xfer->tx_sg.nents,
DMA_MEM_TO_DEV,
@ -343,13 +343,13 @@ static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
if (ret)
goto err_dma_tx;
dma_async_issue_pending(master->dma_rx);
dma_async_issue_pending(master->dma_tx);
dma_async_issue_pending(host->dma_rx);
dma_async_issue_pending(host->dma_tx);
return 0;
err_dma_tx:
dmaengine_terminate_all(master->dma_rx);
dmaengine_terminate_all(host->dma_rx);
err_dma:
return ret;
}
@ -357,7 +357,7 @@ err_dma:
static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
{
int buf_offset = offsetof(struct pic32_spi_regs, buf);
struct spi_master *master = pic32s->master;
struct spi_controller *host = pic32s->host;
struct dma_slave_config cfg;
int ret;
@ -371,16 +371,16 @@ static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
cfg.dst_addr_width = dma_width;
/* tx channel */
cfg.direction = DMA_MEM_TO_DEV;
ret = dmaengine_slave_config(master->dma_tx, &cfg);
ret = dmaengine_slave_config(host->dma_tx, &cfg);
if (ret) {
dev_err(&master->dev, "tx channel setup failed\n");
dev_err(&host->dev, "tx channel setup failed\n");
return ret;
}
/* rx channel */
cfg.direction = DMA_DEV_TO_MEM;
ret = dmaengine_slave_config(master->dma_rx, &cfg);
ret = dmaengine_slave_config(host->dma_rx, &cfg);
if (ret)
dev_err(&master->dev, "rx channel setup failed\n");
dev_err(&host->dev, "rx channel setup failed\n");
return ret;
}
@ -430,19 +430,19 @@ static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word)
return 0;
}
static int pic32_spi_prepare_hardware(struct spi_master *master)
static int pic32_spi_prepare_hardware(struct spi_controller *host)
{
struct pic32_spi *pic32s = spi_master_get_devdata(master);
struct pic32_spi *pic32s = spi_controller_get_devdata(host);
pic32_spi_enable(pic32s);
return 0;
}
static int pic32_spi_prepare_message(struct spi_master *master,
static int pic32_spi_prepare_message(struct spi_controller *host,
struct spi_message *msg)
{
struct pic32_spi *pic32s = spi_master_get_devdata(master);
struct pic32_spi *pic32s = spi_controller_get_devdata(host);
struct spi_device *spi = msg->spi;
u32 val;
@ -481,18 +481,18 @@ static int pic32_spi_prepare_message(struct spi_master *master,
return 0;
}
static bool pic32_spi_can_dma(struct spi_master *master,
static bool pic32_spi_can_dma(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *xfer)
{
struct pic32_spi *pic32s = spi_master_get_devdata(master);
struct pic32_spi *pic32s = spi_controller_get_devdata(host);
/* skip using DMA on small size transfer to avoid overhead.*/
return (xfer->len >= PIC32_DMA_LEN_MIN) &&
test_bit(PIC32F_DMA_PREP, &pic32s->flags);
}
static int pic32_spi_one_transfer(struct spi_master *master,
static int pic32_spi_one_transfer(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *transfer)
{
@ -501,7 +501,7 @@ static int pic32_spi_one_transfer(struct spi_master *master,
unsigned long timeout;
int ret;
pic32s = spi_master_get_devdata(master);
pic32s = spi_controller_get_devdata(host);
/* handle transfer specific word size change */
if (transfer->bits_per_word &&
@ -549,8 +549,8 @@ static int pic32_spi_one_transfer(struct spi_master *master,
if (timeout == 0) {
dev_err(&spi->dev, "wait error/timedout\n");
if (dma_issued) {
dmaengine_terminate_all(master->dma_rx);
dmaengine_terminate_all(master->dma_tx);
dmaengine_terminate_all(host->dma_rx);
dmaengine_terminate_all(host->dma_tx);
}
ret = -ETIMEDOUT;
} else {
@ -560,16 +560,16 @@ static int pic32_spi_one_transfer(struct spi_master *master,
return ret;
}
static int pic32_spi_unprepare_message(struct spi_master *master,
static int pic32_spi_unprepare_message(struct spi_controller *host,
struct spi_message *msg)
{
/* nothing to do */
return 0;
}
static int pic32_spi_unprepare_hardware(struct spi_master *master)
static int pic32_spi_unprepare_hardware(struct spi_controller *host)
{
struct pic32_spi *pic32s = spi_master_get_devdata(master);
struct pic32_spi *pic32s = spi_controller_get_devdata(host);
pic32_spi_disable(pic32s);
@ -605,28 +605,28 @@ static void pic32_spi_cleanup(struct spi_device *spi)
static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
{
struct spi_master *master = pic32s->master;
struct spi_controller *host = pic32s->host;
int ret = 0;
master->dma_rx = dma_request_chan(dev, "spi-rx");
if (IS_ERR(master->dma_rx)) {
if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER)
host->dma_rx = dma_request_chan(dev, "spi-rx");
if (IS_ERR(host->dma_rx)) {
if (PTR_ERR(host->dma_rx) == -EPROBE_DEFER)
ret = -EPROBE_DEFER;
else
dev_warn(dev, "RX channel not found.\n");
master->dma_rx = NULL;
host->dma_rx = NULL;
goto out_err;
}
master->dma_tx = dma_request_chan(dev, "spi-tx");
if (IS_ERR(master->dma_tx)) {
if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER)
host->dma_tx = dma_request_chan(dev, "spi-tx");
if (IS_ERR(host->dma_tx)) {
if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER)
ret = -EPROBE_DEFER;
else
dev_warn(dev, "TX channel not found.\n");
master->dma_tx = NULL;
host->dma_tx = NULL;
goto out_err;
}
@ -639,14 +639,14 @@ static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
return 0;
out_err:
if (master->dma_rx) {
dma_release_channel(master->dma_rx);
master->dma_rx = NULL;
if (host->dma_rx) {
dma_release_channel(host->dma_rx);
host->dma_rx = NULL;
}
if (master->dma_tx) {
dma_release_channel(master->dma_tx);
master->dma_tx = NULL;
if (host->dma_tx) {
dma_release_channel(host->dma_tx);
host->dma_tx = NULL;
}
return ret;
@ -658,11 +658,11 @@ static void pic32_spi_dma_unprep(struct pic32_spi *pic32s)
return;
clear_bit(PIC32F_DMA_PREP, &pic32s->flags);
if (pic32s->master->dma_rx)
dma_release_channel(pic32s->master->dma_rx);
if (pic32s->host->dma_rx)
dma_release_channel(pic32s->host->dma_rx);
if (pic32s->master->dma_tx)
dma_release_channel(pic32s->master->dma_tx);
if (pic32s->host->dma_tx)
dma_release_channel(pic32s->host->dma_tx);
}
static void pic32_spi_hw_init(struct pic32_spi *pic32s)
@ -680,7 +680,7 @@ static void pic32_spi_hw_init(struct pic32_spi *pic32s)
/* disable framing mode */
ctrl &= ~CTRL_FRMEN;
/* enable master mode while disabled */
/* enable host mode while disabled */
ctrl |= CTRL_MSTEN;
/* set tx fifo threshold interrupt */
@ -752,36 +752,36 @@ err_unmap_mem:
static int pic32_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct spi_controller *host;
struct pic32_spi *pic32s;
int ret;
master = spi_alloc_master(&pdev->dev, sizeof(*pic32s));
if (!master)
host = spi_alloc_host(&pdev->dev, sizeof(*pic32s));
if (!host)
return -ENOMEM;
pic32s = spi_master_get_devdata(master);
pic32s->master = master;
pic32s = spi_controller_get_devdata(host);
pic32s->host = host;
ret = pic32_spi_hw_probe(pdev, pic32s);
if (ret)
goto err_master;
goto err_host;
master->dev.of_node = pdev->dev.of_node;
master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;
master->num_chipselect = 1; /* single chip-select */
master->max_speed_hz = clk_get_rate(pic32s->clk);
master->setup = pic32_spi_setup;
master->cleanup = pic32_spi_cleanup;
master->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_MUST_RX;
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
host->dev.of_node = pdev->dev.of_node;
host->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;
host->num_chipselect = 1; /* single chip-select */
host->max_speed_hz = clk_get_rate(pic32s->clk);
host->setup = pic32_spi_setup;
host->cleanup = pic32_spi_cleanup;
host->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_MUST_RX;
host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
SPI_BPW_MASK(32);
master->transfer_one = pic32_spi_one_transfer;
master->prepare_message = pic32_spi_prepare_message;
master->unprepare_message = pic32_spi_unprepare_message;
master->prepare_transfer_hardware = pic32_spi_prepare_hardware;
master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware;
master->use_gpio_descriptors = true;
host->transfer_one = pic32_spi_one_transfer;
host->prepare_message = pic32_spi_prepare_message;
host->unprepare_message = pic32_spi_unprepare_message;
host->prepare_transfer_hardware = pic32_spi_prepare_hardware;
host->unprepare_transfer_hardware = pic32_spi_unprepare_hardware;
host->use_gpio_descriptors = true;
/* optional DMA support */
ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
@ -789,7 +789,7 @@ static int pic32_spi_probe(struct platform_device *pdev)
goto err_bailout;
if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
master->can_dma = pic32_spi_can_dma;
host->can_dma = pic32_spi_can_dma;
init_completion(&pic32s->xfer_done);
pic32s->mode = -1;
@ -824,10 +824,10 @@ static int pic32_spi_probe(struct platform_device *pdev)
goto err_bailout;
}
/* register master */
ret = devm_spi_register_master(&pdev->dev, master);
/* register host */
ret = devm_spi_register_controller(&pdev->dev, host);
if (ret) {
dev_err(&master->dev, "failed registering spi master\n");
dev_err(&host->dev, "failed registering spi host\n");
goto err_bailout;
}
@ -838,8 +838,8 @@ static int pic32_spi_probe(struct platform_device *pdev)
err_bailout:
pic32_spi_dma_unprep(pic32s);
clk_disable_unprepare(pic32s->clk);
err_master:
spi_master_put(master);
err_host:
spi_controller_put(host);
return ret;
}

94
drivers/spi/spi-pl022.c
View File

@ -336,8 +336,8 @@ struct vendor_data {
* @phybase: the physical memory where the SSP device resides
* @virtbase: the virtual memory where the SSP is mapped
* @clk: outgoing clock "SPICLK" for the SPI bus
* @master: SPI framework hookup
* @master_info: controller-specific data from machine setup
* @host: SPI framework hookup
* @host_info: controller-specific data from machine setup
* @pump_transfers: Tasklet used in Interrupt Transfer mode
* @cur_msg: Pointer to current spi_message being processed
* @cur_transfer: Pointer to current spi_transfer
@ -370,8 +370,8 @@ struct pl022 {
resource_size_t phybase;
void __iomem *virtbase;
struct clk *clk;
struct spi_master *master;
struct pl022_ssp_controller *master_info;
struct spi_controller *host;
struct pl022_ssp_controller *host_info;
/* Message per-transfer pump */
struct tasklet_struct pump_transfers;
struct spi_message *cur_msg;
@ -500,7 +500,7 @@ static void giveback(struct pl022 *pl022)
* could invalidate the cs_control() callback...
*/
/* get a pointer to the next message, if any */
next_msg = spi_get_next_queued_message(pl022->master);
next_msg = spi_get_next_queued_message(pl022->host);
/*
* see if the next and current messages point
@ -523,7 +523,7 @@ static void giveback(struct pl022 *pl022)
writew((readw(SSP_CR1(pl022->virtbase)) &
(~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
spi_finalize_current_message(pl022->master);
spi_finalize_current_message(pl022->host);
}
/**
@ -1110,16 +1110,16 @@ static int pl022_dma_probe(struct pl022 *pl022)
* of them.
*/
pl022->dma_rx_channel = dma_request_channel(mask,
pl022->master_info->dma_filter,
pl022->master_info->dma_rx_param);
pl022->host_info->dma_filter,
pl022->host_info->dma_rx_param);
if (!pl022->dma_rx_channel) {
dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
goto err_no_rxchan;
}
pl022->dma_tx_channel = dma_request_channel(mask,
pl022->master_info->dma_filter,
pl022->master_info->dma_tx_param);
pl022->host_info->dma_filter,
pl022->host_info->dma_tx_param);
if (!pl022->dma_tx_channel) {
dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
goto err_no_txchan;
@ -1573,10 +1573,10 @@ out:
return;
}
static int pl022_transfer_one_message(struct spi_master *master,
static int pl022_transfer_one_message(struct spi_controller *host,
struct spi_message *msg)
{
struct pl022 *pl022 = spi_master_get_devdata(master);
struct pl022 *pl022 = spi_controller_get_devdata(host);
/* Initial message state */
pl022->cur_msg = msg;
@ -1602,9 +1602,9 @@ static int pl022_transfer_one_message(struct spi_master *master,
return 0;
}
static int pl022_unprepare_transfer_hardware(struct spi_master *master)
static int pl022_unprepare_transfer_hardware(struct spi_controller *host)
{
struct pl022 *pl022 = spi_master_get_devdata(master);
struct pl022 *pl022 = spi_controller_get_devdata(host);
/* nothing more to do - disable spi/ssp and power off */
writew((readw(SSP_CR1(pl022->virtbase)) &
@ -1826,10 +1826,10 @@ static const struct pl022_config_chip pl022_default_chip_info = {
};
/**
* pl022_setup - setup function registered to SPI master framework
* pl022_setup - setup function registered to SPI host framework
* @spi: spi device which is requesting setup
*
* This function is registered to the SPI framework for this SPI master
* This function is registered to the SPI framework for this SPI host
* controller. If it is the first time when setup is called by this device,
* this function will initialize the runtime state for this chip and save
* the same in the device structure. Else it will update the runtime info
@ -1844,7 +1844,7 @@ static int pl022_setup(struct spi_device *spi)
struct chip_data *chip;
struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
int status = 0;
struct pl022 *pl022 = spi_master_get_devdata(spi->master);
struct pl022 *pl022 = spi_controller_get_devdata(spi->controller);
unsigned int bits = spi->bits_per_word;
u32 tmp;
struct device_node *np = spi->dev.of_node;
@ -1964,7 +1964,7 @@ static int pl022_setup(struct spi_device *spi)
chip->dmacr = 0;
chip->cpsr = 0;
if ((chip_info->com_mode == DMA_TRANSFER)
&& ((pl022->master_info)->enable_dma)) {
&& ((pl022->host_info)->enable_dma)) {
chip->enable_dma = true;
dev_dbg(&spi->dev, "DMA mode set in controller state\n");
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
@ -2061,10 +2061,10 @@ static int pl022_setup(struct spi_device *spi)
}
/**
* pl022_cleanup - cleanup function registered to SPI master framework
* pl022_cleanup - cleanup function registered to SPI host framework
* @spi: spi device which is requesting cleanup
*
* This function is registered to the SPI framework for this SPI master
* This function is registered to the SPI framework for this SPI host
* controller. It will free the runtime state of chip.
*/
static void pl022_cleanup(struct spi_device *spi)
@ -2103,7 +2103,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
struct device *dev = &adev->dev;
struct pl022_ssp_controller *platform_info =
dev_get_platdata(&adev->dev);
struct spi_master *master;
struct spi_controller *host;
struct pl022 *pl022 = NULL; /*Data for this driver */
int status = 0;
@ -2117,16 +2117,16 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
return -ENODEV;
}
/* Allocate master with space for data */
master = spi_alloc_master(dev, sizeof(struct pl022));
if (master == NULL) {
dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
/* Allocate host with space for data */
host = spi_alloc_host(dev, sizeof(struct pl022));
if (host == NULL) {
dev_err(&adev->dev, "probe - cannot alloc SPI host\n");
return -ENOMEM;
}
pl022 = spi_master_get_devdata(master);
pl022->master = master;
pl022->master_info = platform_info;
pl022 = spi_controller_get_devdata(host);
pl022->host = host;
pl022->host_info = platform_info;
pl022->adev = adev;
pl022->vendor = id->data;
@ -2134,25 +2134,25 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
* Bus Number Which has been Assigned to this SSP controller
* on this board
*/
master->bus_num = platform_info->bus_id;
master->cleanup = pl022_cleanup;
master->setup = pl022_setup;
master->auto_runtime_pm = true;
master->transfer_one_message = pl022_transfer_one_message;
master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
master->rt = platform_info->rt;
master->dev.of_node = dev->of_node;
master->use_gpio_descriptors = true;
host->bus_num = platform_info->bus_id;
host->cleanup = pl022_cleanup;
host->setup = pl022_setup;
host->auto_runtime_pm = true;
host->transfer_one_message = pl022_transfer_one_message;
host->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
host->rt = platform_info->rt;
host->dev.of_node = dev->of_node;
host->use_gpio_descriptors = true;
/*
* Supports mode 0-3, loopback, and active low CS. Transfers are
* always MS bit first on the original pl022.
*/
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
if (pl022->vendor->extended_cr)
master->mode_bits |= SPI_LSB_FIRST;
host->mode_bits |= SPI_LSB_FIRST;
dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
dev_dbg(&adev->dev, "BUSNO: %d\n", host->bus_num);
status = amba_request_regions(adev, NULL);
if (status)
@ -2215,10 +2215,10 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
/* Register with the SPI framework */
amba_set_drvdata(adev, pl022);
status = devm_spi_register_master(&adev->dev, master);
status = devm_spi_register_controller(&adev->dev, host);
if (status != 0) {
dev_err_probe(&adev->dev, status,
"problem registering spi master\n");
"problem registering spi host\n");
goto err_spi_register;
}
dev_dbg(dev, "probe succeeded\n");
@ -2246,7 +2246,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
err_no_ioremap:
amba_release_regions(adev);
err_no_ioregion:
spi_master_put(master);
spi_controller_put(host);
return status;
}
@ -2265,7 +2265,7 @@ pl022_remove(struct amba_device *adev)
pm_runtime_get_noresume(&adev->dev);
load_ssp_default_config(pl022);
if (pl022->master_info->enable_dma)
if (pl022->host_info->enable_dma)
pl022_dma_remove(pl022);
clk_disable_unprepare(pl022->clk);
@ -2279,13 +2279,13 @@ static int pl022_suspend(struct device *dev)
struct pl022 *pl022 = dev_get_drvdata(dev);
int ret;
ret = spi_master_suspend(pl022->master);
ret = spi_controller_suspend(pl022->host);
if (ret)
return ret;
ret = pm_runtime_force_suspend(dev);
if (ret) {
spi_master_resume(pl022->master);
spi_controller_resume(pl022->host);
return ret;
}
@ -2305,7 +2305,7 @@ static int pl022_resume(struct device *dev)
dev_err(dev, "problem resuming\n");
/* Start the queue running */
ret = spi_master_resume(pl022->master);
ret = spi_controller_resume(pl022->host);
if (!ret)
dev_dbg(dev, "resumed\n");

44
drivers/spi/spi-ppc4xx.c
View File

@ -126,7 +126,7 @@ struct ppc4xx_spi {
unsigned char *rx;
struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
struct spi_master *master;
struct spi_controller *host;
struct device *dev;
};
@ -143,7 +143,7 @@ static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
t->tx_buf, t->rx_buf, t->len);
hw = spi_master_get_devdata(spi->master);
hw = spi_controller_get_devdata(spi->controller);
hw->tx = t->tx_buf;
hw->rx = t->rx_buf;
@ -161,7 +161,7 @@ static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
{
struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
struct ppc4xx_spi *hw = spi_controller_get_devdata(spi->controller);
struct spi_ppc4xx_cs *cs = spi->controller_state;
int scr;
u8 cdm = 0;
@ -340,7 +340,7 @@ static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
static int spi_ppc4xx_of_probe(struct platform_device *op)
{
struct ppc4xx_spi *hw;
struct spi_master *master;
struct spi_controller *host;
struct spi_bitbang *bbp;
struct resource resource;
struct device_node *np = op->dev.of_node;
@ -349,20 +349,20 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
int ret;
const unsigned int *clk;
master = spi_alloc_master(dev, sizeof(*hw));
if (master == NULL)
host = spi_alloc_host(dev, sizeof(*hw));
if (host == NULL)
return -ENOMEM;
master->dev.of_node = np;
platform_set_drvdata(op, master);
hw = spi_master_get_devdata(master);
hw->master = master;
host->dev.of_node = np;
platform_set_drvdata(op, host);
hw = spi_controller_get_devdata(host);
hw->host = host;
hw->dev = dev;
init_completion(&hw->done);
/* Setup the state for the bitbang driver */
bbp = &hw->bitbang;
bbp->master = hw->master;
bbp->master = hw->host;
bbp->setup_transfer = spi_ppc4xx_setupxfer;
bbp->txrx_bufs = spi_ppc4xx_txrx;
bbp->use_dma = 0;
@ -385,7 +385,7 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
if (opbnp == NULL) {
dev_err(dev, "OPB: cannot find node\n");
ret = -ENODEV;
goto free_master;
goto free_host;
}
/* Get the clock (Hz) for the OPB */
clk = of_get_property(opbnp, "clock-frequency", NULL);
@ -393,7 +393,7 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
dev_err(dev, "OPB: no clock-frequency property set\n");
of_node_put(opbnp);
ret = -ENODEV;
goto free_master;
goto free_host;
}
hw->opb_freq = *clk;
hw->opb_freq >>= 2;
@ -402,7 +402,7 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
ret = of_address_to_resource(np, 0, &resource);
if (ret) {
dev_err(dev, "error while parsing device node resource\n");
goto free_master;
goto free_host;
}
hw->mapbase = resource.start;
hw->mapsize = resource_size(&resource);
@ -411,7 +411,7 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
dev_err(dev, "too small to map registers\n");
ret = -EINVAL;
goto free_master;
goto free_host;
}
/* Request IRQ */
@ -420,7 +420,7 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
0, "spi_ppc4xx_of", (void *)hw);
if (ret) {
dev_err(dev, "unable to allocate interrupt\n");
goto free_master;
goto free_host;
}
if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
@ -443,7 +443,7 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
dev->dma_mask = 0;
ret = spi_bitbang_start(bbp);
if (ret) {
dev_err(dev, "failed to register SPI master\n");
dev_err(dev, "failed to register SPI host\n");
goto unmap_regs;
}
@ -457,8 +457,8 @@ map_io_error:
release_mem_region(hw->mapbase, hw->mapsize);
request_mem_error:
free_irq(hw->irqnum, hw);
free_master:
spi_master_put(master);
free_host:
spi_controller_put(host);
dev_err(dev, "initialization failed\n");
return ret;
@ -466,14 +466,14 @@ free_master:
static void spi_ppc4xx_of_remove(struct platform_device *op)
{
struct spi_master *master = platform_get_drvdata(op);
struct ppc4xx_spi *hw = spi_master_get_devdata(master);
struct spi_controller *host = platform_get_drvdata(op);
struct ppc4xx_spi *hw = spi_controller_get_devdata(host);
spi_bitbang_stop(&hw->bitbang);
release_mem_region(hw->mapbase, hw->mapsize);
free_irq(hw->irqnum, hw);
iounmap(hw->regs);
spi_master_put(master);
spi_controller_put(host);
}
static const struct of_device_id spi_ppc4xx_of_match[] = {

24
drivers/spi/spi-pxa2xx.c
View File

@ -1102,7 +1102,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
}
}
if (spi_controller_is_slave(controller)) {
if (spi_controller_is_target(controller)) {
while (drv_data->write(drv_data))
;
if (drv_data->gpiod_ready) {
@ -1121,7 +1121,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
return 1;
}
static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
static int pxa2xx_spi_target_abort(struct spi_controller *controller)
{
struct driver_data *drv_data = spi_controller_get_devdata(controller);
@ -1199,7 +1199,7 @@ static int setup(struct spi_device *spi)
break;
default:
tx_hi_thres = 0;
if (spi_controller_is_slave(drv_data->controller)) {
if (spi_controller_is_target(drv_data->controller)) {
tx_thres = 1;
rx_thres = 2;
} else {
@ -1248,7 +1248,7 @@ static int setup(struct spi_device *spi)
}
chip->cr1 = 0;
if (spi_controller_is_slave(drv_data->controller)) {
if (spi_controller_is_target(drv_data->controller)) {
chip->cr1 |= SSCR1_SCFR;
chip->cr1 |= SSCR1_SCLKDIR;
chip->cr1 |= SSCR1_SFRMDIR;
@ -1395,7 +1395,7 @@ pxa2xx_spi_init_pdata(struct platform_device *pdev)
else
ssp->port_id = uid;
pdata->is_slave = device_property_read_bool(dev, "spi-slave");
pdata->is_target = device_property_read_bool(dev, "spi-slave");
pdata->num_chipselect = 1;
pdata->enable_dma = true;
pdata->dma_burst_size = 1;
@ -1461,10 +1461,10 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
return -ENODEV;
}
if (platform_info->is_slave)
controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
if (platform_info->is_target)
controller = devm_spi_alloc_target(dev, sizeof(*drv_data));
else
controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
controller = devm_spi_alloc_host(dev, sizeof(*drv_data));
if (!controller) {
dev_err(&pdev->dev, "cannot alloc spi_controller\n");
@ -1487,7 +1487,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
controller->setup = setup;
controller->set_cs = pxa2xx_spi_set_cs;
controller->transfer_one = pxa2xx_spi_transfer_one;
controller->slave_abort = pxa2xx_spi_slave_abort;
controller->target_abort = pxa2xx_spi_target_abort;
controller->handle_err = pxa2xx_spi_handle_err;
controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
@ -1579,7 +1579,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
break;
default:
if (spi_controller_is_slave(controller)) {
if (spi_controller_is_target(controller)) {
tmp = SSCR1_SCFR |
SSCR1_SCLKDIR |
SSCR1_SFRMDIR |
@ -1592,7 +1592,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
}
pxa2xx_spi_write(drv_data, SSCR1, tmp);
tmp = SSCR0_Motorola | SSCR0_DataSize(8);
if (!spi_controller_is_slave(controller))
if (!spi_controller_is_target(controller))
tmp |= SSCR0_SCR(2);
pxa2xx_spi_write(drv_data, SSCR0, tmp);
break;
@ -1620,7 +1620,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
controller->num_chipselect = platform_info->num_chipselect;
controller->use_gpio_descriptors = true;
if (platform_info->is_slave) {
if (platform_info->is_target) {
drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
"ready", GPIOD_OUT_LOW);
if (IS_ERR(drv_data->gpiod_ready)) {

80
drivers/spi/spi-qcom-qspi.c
View File

@ -247,11 +247,11 @@ static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl)
qcom_qspi_pio_xfer_ctrl(ctrl);
}
static void qcom_qspi_handle_err(struct spi_master *master,
static void qcom_qspi_handle_err(struct spi_controller *host,
struct spi_message *msg)
{
u32 int_status;
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
unsigned long flags;
int i;
@ -411,11 +411,11 @@ static bool qcom_qspi_can_dma(struct spi_controller *ctlr,
return xfer->len > QSPI_MAX_BYTES_FIFO;
}
static int qcom_qspi_transfer_one(struct spi_master *master,
static int qcom_qspi_transfer_one(struct spi_controller *host,
struct spi_device *slv,
struct spi_transfer *xfer)
{
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
int ret;
unsigned long speed_hz;
unsigned long flags;
@ -443,7 +443,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
ctrl->xfer.tx_buf = xfer->tx_buf;
}
ctrl->xfer.is_last = list_is_last(&xfer->transfer_list,
&master->cur_msg->transfers);
&host->cur_msg->transfers);
ctrl->xfer.rem_bytes = xfer->len;
if (xfer->rx_sg.nents || xfer->tx_sg.nents) {
@ -481,7 +481,7 @@ exit:
return 1;
}
static int qcom_qspi_prepare_message(struct spi_master *master,
static int qcom_qspi_prepare_message(struct spi_controller *host,
struct spi_message *message)
{
u32 mstr_cfg;
@ -490,7 +490,7 @@ static int qcom_qspi_prepare_message(struct spi_master *master,
int tx_data_delay = 1;
unsigned long flags;
ctrl = spi_master_get_devdata(master);
ctrl = spi_controller_get_devdata(host);
spin_lock_irqsave(&ctrl->lock, flags);
mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
@ -694,18 +694,18 @@ static int qcom_qspi_probe(struct platform_device *pdev)
{
int ret;
struct device *dev;
struct spi_master *master;
struct spi_controller *host;
struct qcom_qspi *ctrl;
dev = &pdev->dev;
master = devm_spi_alloc_master(dev, sizeof(*ctrl));
if (!master)
host = devm_spi_alloc_host(dev, sizeof(*ctrl));
if (!host)
return -ENOMEM;
platform_set_drvdata(pdev, master);
platform_set_drvdata(pdev, host);
ctrl = spi_master_get_devdata(master);
ctrl = spi_controller_get_devdata(host);
spin_lock_init(&ctrl->lock);
ctrl->dev = dev;
@ -758,23 +758,23 @@ static int qcom_qspi_probe(struct platform_device *pdev)
if (ret)
return dev_err_probe(dev, ret, "could not set DMA mask\n");
master->max_speed_hz = 300000000;
master->max_dma_len = 65536; /* as per HPG */
master->dma_alignment = QSPI_ALIGN_REQ;
master->num_chipselect = QSPI_NUM_CS;
master->bus_num = -1;
master->dev.of_node = pdev->dev.of_node;
master->mode_bits = SPI_MODE_0 |
SPI_TX_DUAL | SPI_RX_DUAL |
SPI_TX_QUAD | SPI_RX_QUAD;
master->flags = SPI_CONTROLLER_HALF_DUPLEX;
master->prepare_message = qcom_qspi_prepare_message;
master->transfer_one = qcom_qspi_transfer_one;
master->handle_err = qcom_qspi_handle_err;
host->max_speed_hz = 300000000;
host->max_dma_len = 65536; /* as per HPG */
host->dma_alignment = QSPI_ALIGN_REQ;
host->num_chipselect = QSPI_NUM_CS;
host->bus_num = -1;
host->dev.of_node = pdev->dev.of_node;
host->mode_bits = SPI_MODE_0 |
SPI_TX_DUAL | SPI_RX_DUAL |
SPI_TX_QUAD | SPI_RX_QUAD;
host->flags = SPI_CONTROLLER_HALF_DUPLEX;
host->prepare_message = qcom_qspi_prepare_message;
host->transfer_one = qcom_qspi_transfer_one;
host->handle_err = qcom_qspi_handle_err;
if (of_property_read_bool(pdev->dev.of_node, "iommus"))
master->can_dma = qcom_qspi_can_dma;
master->auto_runtime_pm = true;
master->mem_ops = &qcom_qspi_mem_ops;
host->can_dma = qcom_qspi_can_dma;
host->auto_runtime_pm = true;
host->mem_ops = &qcom_qspi_mem_ops;
ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
if (ret)
@ -794,7 +794,7 @@ static int qcom_qspi_probe(struct platform_device *pdev)
pm_runtime_set_autosuspend_delay(dev, 250);
pm_runtime_enable(dev);
ret = spi_register_master(master);
ret = spi_register_controller(host);
if (!ret)
return 0;
@ -805,18 +805,18 @@ static int qcom_qspi_probe(struct platform_device *pdev)
static void qcom_qspi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct spi_controller *host = platform_get_drvdata(pdev);
/* Unregister _before_ disabling pm_runtime() so we stop transfers */
spi_unregister_master(master);
spi_unregister_controller(host);
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
int ret;
/* Drop the performance state vote */
@ -837,8 +837,8 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
int ret;
pinctrl_pm_select_default_state(dev);
@ -859,30 +859,30 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
static int __maybe_unused qcom_qspi_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct spi_controller *host = dev_get_drvdata(dev);
int ret;
ret = spi_master_suspend(master);
ret = spi_controller_suspend(host);
if (ret)
return ret;
ret = pm_runtime_force_suspend(dev);
if (ret)
spi_master_resume(master);
spi_controller_resume(host);
return ret;
}
static int __maybe_unused qcom_qspi_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct spi_controller *host = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_force_resume(dev);
if (ret)
return ret;
ret = spi_master_resume(master);
ret = spi_controller_resume(host);
if (ret)
pm_runtime_force_suspend(dev);

166
drivers/spi/spi-qup.c
View File

@ -385,20 +385,20 @@ static void spi_qup_write(struct spi_qup *controller)
} while (remainder);
}
static int spi_qup_prep_sg(struct spi_master *master, struct scatterlist *sgl,
static int spi_qup_prep_sg(struct spi_controller *host, struct scatterlist *sgl,
unsigned int nents, enum dma_transfer_direction dir,
dma_async_tx_callback callback)
{
struct spi_qup *qup = spi_master_get_devdata(master);
struct spi_qup *qup = spi_controller_get_devdata(host);
unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
struct dma_async_tx_descriptor *desc;
struct dma_chan *chan;
dma_cookie_t cookie;
if (dir == DMA_MEM_TO_DEV)
chan = master->dma_tx;
chan = host->dma_tx;
else
chan = master->dma_rx;
chan = host->dma_rx;
desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
if (IS_ERR_OR_NULL(desc))
@ -412,13 +412,13 @@ static int spi_qup_prep_sg(struct spi_master *master, struct scatterlist *sgl,
return dma_submit_error(cookie);
}
static void spi_qup_dma_terminate(struct spi_master *master,
static void spi_qup_dma_terminate(struct spi_controller *host,
struct spi_transfer *xfer)
{
if (xfer->tx_buf)
dmaengine_terminate_all(master->dma_tx);
dmaengine_terminate_all(host->dma_tx);
if (xfer->rx_buf)
dmaengine_terminate_all(master->dma_rx);
dmaengine_terminate_all(host->dma_rx);
}
static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max,
@ -445,8 +445,8 @@ static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
unsigned long timeout)
{
dma_async_tx_callback rx_done = NULL, tx_done = NULL;
struct spi_master *master = spi->master;
struct spi_qup *qup = spi_master_get_devdata(master);
struct spi_controller *host = spi->controller;
struct spi_qup *qup = spi_controller_get_devdata(host);
struct scatterlist *tx_sgl, *rx_sgl;
int ret;
@ -481,20 +481,20 @@ static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
return ret;
}
if (rx_sgl) {
ret = spi_qup_prep_sg(master, rx_sgl, rx_nents,
ret = spi_qup_prep_sg(host, rx_sgl, rx_nents,
DMA_DEV_TO_MEM, rx_done);
if (ret)
return ret;
dma_async_issue_pending(master->dma_rx);
dma_async_issue_pending(host->dma_rx);
}
if (tx_sgl) {
ret = spi_qup_prep_sg(master, tx_sgl, tx_nents,
ret = spi_qup_prep_sg(host, tx_sgl, tx_nents,
DMA_MEM_TO_DEV, tx_done);
if (ret)
return ret;
dma_async_issue_pending(master->dma_tx);
dma_async_issue_pending(host->dma_tx);
}
if (!wait_for_completion_timeout(&qup->done, timeout))
@ -513,8 +513,8 @@ static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
unsigned long timeout)
{
struct spi_master *master = spi->master;
struct spi_qup *qup = spi_master_get_devdata(master);
struct spi_controller *host = spi->controller;
struct spi_qup *qup = spi_controller_get_devdata(host);
int ret, n_words, iterations, offset = 0;
n_words = qup->n_words;
@ -658,7 +658,7 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
/* set clock freq ... bits per word, determine mode */
static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
{
struct spi_qup *controller = spi_master_get_devdata(spi->master);
struct spi_qup *controller = spi_controller_get_devdata(spi->controller);
int ret;
if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
@ -679,9 +679,9 @@ static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
controller->mode = QUP_IO_M_MODE_FIFO;
else if (spi->master->can_dma &&
spi->master->can_dma(spi->master, spi, xfer) &&
spi->master->cur_msg_mapped)
else if (spi->controller->can_dma &&
spi->controller->can_dma(spi->controller, spi, xfer) &&
spi->controller->cur_msg_mapped)
controller->mode = QUP_IO_M_MODE_BAM;
else
controller->mode = QUP_IO_M_MODE_BLOCK;
@ -692,7 +692,7 @@ static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
/* prep qup for another spi transaction of specific type */
static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
{
struct spi_qup *controller = spi_master_get_devdata(spi->master);
struct spi_qup *controller = spi_controller_get_devdata(spi->controller);
u32 config, iomode, control;
unsigned long flags;
@ -840,11 +840,11 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
return 0;
}
static int spi_qup_transfer_one(struct spi_master *master,
static int spi_qup_transfer_one(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *xfer)
{
struct spi_qup *controller = spi_master_get_devdata(master);
struct spi_qup *controller = spi_controller_get_devdata(host);
unsigned long timeout, flags;
int ret;
@ -878,21 +878,21 @@ static int spi_qup_transfer_one(struct spi_master *master,
spin_unlock_irqrestore(&controller->lock, flags);
if (ret && spi_qup_is_dma_xfer(controller->mode))
spi_qup_dma_terminate(master, xfer);
spi_qup_dma_terminate(host, xfer);
return ret;
}
static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
static bool spi_qup_can_dma(struct spi_controller *host, struct spi_device *spi,
struct spi_transfer *xfer)
{
struct spi_qup *qup = spi_master_get_devdata(master);
struct spi_qup *qup = spi_controller_get_devdata(host);
size_t dma_align = dma_get_cache_alignment();
int n_words;
if (xfer->rx_buf) {
if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
IS_ERR_OR_NULL(master->dma_rx))
IS_ERR_OR_NULL(host->dma_rx))
return false;
if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
return false;
@ -900,7 +900,7 @@ static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
if (xfer->tx_buf) {
if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
IS_ERR_OR_NULL(master->dma_tx))
IS_ERR_OR_NULL(host->dma_tx))
return false;
if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
return false;
@ -913,30 +913,30 @@ static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
return true;
}
static void spi_qup_release_dma(struct spi_master *master)
static void spi_qup_release_dma(struct spi_controller *host)
{
if (!IS_ERR_OR_NULL(master->dma_rx))
dma_release_channel(master->dma_rx);
if (!IS_ERR_OR_NULL(master->dma_tx))
dma_release_channel(master->dma_tx);
if (!IS_ERR_OR_NULL(host->dma_rx))
dma_release_channel(host->dma_rx);
if (!IS_ERR_OR_NULL(host->dma_tx))
dma_release_channel(host->dma_tx);
}
static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
static int spi_qup_init_dma(struct spi_controller *host, resource_size_t base)
{
struct spi_qup *spi = spi_master_get_devdata(master);
struct spi_qup *spi = spi_controller_get_devdata(host);
struct dma_slave_config *rx_conf = &spi->rx_conf,
*tx_conf = &spi->tx_conf;
struct device *dev = spi->dev;
int ret;
/* allocate dma resources, if available */
master->dma_rx = dma_request_chan(dev, "rx");
if (IS_ERR(master->dma_rx))
return PTR_ERR(master->dma_rx);
host->dma_rx = dma_request_chan(dev, "rx");
if (IS_ERR(host->dma_rx))
return PTR_ERR(host->dma_rx);
master->dma_tx = dma_request_chan(dev, "tx");
if (IS_ERR(master->dma_tx)) {
ret = PTR_ERR(master->dma_tx);
host->dma_tx = dma_request_chan(dev, "tx");
if (IS_ERR(host->dma_tx)) {
ret = PTR_ERR(host->dma_tx);
goto err_tx;
}
@ -951,13 +951,13 @@ static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
tx_conf->dst_maxburst = spi->out_blk_sz;
ret = dmaengine_slave_config(master->dma_rx, rx_conf);
ret = dmaengine_slave_config(host->dma_rx, rx_conf);
if (ret) {
dev_err(dev, "failed to configure RX channel\n");
goto err;
}
ret = dmaengine_slave_config(master->dma_tx, tx_conf);
ret = dmaengine_slave_config(host->dma_tx, tx_conf);
if (ret) {
dev_err(dev, "failed to configure TX channel\n");
goto err;
@ -966,9 +966,9 @@ static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
return 0;
err:
dma_release_channel(master->dma_tx);
dma_release_channel(host->dma_tx);
err_tx:
dma_release_channel(master->dma_rx);
dma_release_channel(host->dma_rx);
return ret;
}
@ -978,7 +978,7 @@ static void spi_qup_set_cs(struct spi_device *spi, bool val)
u32 spi_ioc;
u32 spi_ioc_orig;
controller = spi_master_get_devdata(spi->master);
controller = spi_controller_get_devdata(spi->controller);
spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
spi_ioc_orig = spi_ioc;
if (!val)
@ -992,7 +992,7 @@ static void spi_qup_set_cs(struct spi_device *spi, bool val)
static int spi_qup_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct spi_controller *host;
struct clk *iclk, *cclk;
struct spi_qup *controller;
struct resource *res;
@ -1027,34 +1027,34 @@ static int spi_qup_probe(struct platform_device *pdev)
return -ENXIO;
}
master = spi_alloc_master(dev, sizeof(struct spi_qup));
if (!master) {
dev_err(dev, "cannot allocate master\n");
host = spi_alloc_host(dev, sizeof(struct spi_qup));
if (!host) {
dev_err(dev, "cannot allocate host\n");
return -ENOMEM;
}
/* use num-cs unless not present or out of range */
if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
num_cs > SPI_NUM_CHIPSELECTS)
master->num_chipselect = SPI_NUM_CHIPSELECTS;
host->num_chipselect = SPI_NUM_CHIPSELECTS;
else
master->num_chipselect = num_cs;
host->num_chipselect = num_cs;
master->use_gpio_descriptors = true;
master->max_native_cs = SPI_NUM_CHIPSELECTS;
master->bus_num = pdev->id;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
master->max_speed_hz = max_freq;
master->transfer_one = spi_qup_transfer_one;
master->dev.of_node = pdev->dev.of_node;
master->auto_runtime_pm = true;
master->dma_alignment = dma_get_cache_alignment();
master->max_dma_len = SPI_MAX_XFER;
host->use_gpio_descriptors = true;
host->max_native_cs = SPI_NUM_CHIPSELECTS;
host->bus_num = pdev->id;
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
host->max_speed_hz = max_freq;
host->transfer_one = spi_qup_transfer_one;
host->dev.of_node = pdev->dev.of_node;
host->auto_runtime_pm = true;
host->dma_alignment = dma_get_cache_alignment();
host->max_dma_len = SPI_MAX_XFER;
platform_set_drvdata(pdev, master);
platform_set_drvdata(pdev, host);
controller = spi_master_get_devdata(master);
controller = spi_controller_get_devdata(host);
controller->dev = dev;
controller->base = base;
@ -1062,16 +1062,16 @@ static int spi_qup_probe(struct platform_device *pdev)
controller->cclk = cclk;
controller->irq = irq;
ret = spi_qup_init_dma(master, res->start);
ret = spi_qup_init_dma(host, res->start);
if (ret == -EPROBE_DEFER)
goto error;
else if (!ret)
master->can_dma = spi_qup_can_dma;
host->can_dma = spi_qup_can_dma;
controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
if (!controller->qup_v1)
master->set_cs = spi_qup_set_cs;
host->set_cs = spi_qup_set_cs;
spin_lock_init(&controller->lock);
init_completion(&controller->done);
@ -1149,7 +1149,7 @@ static int spi_qup_probe(struct platform_device *pdev)
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
ret = devm_spi_register_master(dev, master);
ret = devm_spi_register_controller(dev, host);
if (ret)
goto disable_pm;
@ -1161,17 +1161,17 @@ error_clk:
clk_disable_unprepare(cclk);
clk_disable_unprepare(iclk);
error_dma:
spi_qup_release_dma(master);
spi_qup_release_dma(host);
error:
spi_master_put(master);
spi_controller_put(host);
return ret;
}
#ifdef CONFIG_PM
static int spi_qup_pm_suspend_runtime(struct device *device)
{
struct spi_master *master = dev_get_drvdata(device);
struct spi_qup *controller = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(device);
struct spi_qup *controller = spi_controller_get_devdata(host);
u32 config;
/* Enable clocks auto gaiting */
@ -1187,8 +1187,8 @@ static int spi_qup_pm_suspend_runtime(struct device *device)
static int spi_qup_pm_resume_runtime(struct device *device)
{
struct spi_master *master = dev_get_drvdata(device);
struct spi_qup *controller = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(device);
struct spi_qup *controller = spi_controller_get_devdata(host);
u32 config;
int ret;
@ -1213,8 +1213,8 @@ static int spi_qup_pm_resume_runtime(struct device *device)
#ifdef CONFIG_PM_SLEEP
static int spi_qup_suspend(struct device *device)
{
struct spi_master *master = dev_get_drvdata(device);
struct spi_qup *controller = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(device);
struct spi_qup *controller = spi_controller_get_devdata(host);
int ret;
if (pm_runtime_suspended(device)) {
@ -1222,7 +1222,7 @@ static int spi_qup_suspend(struct device *device)
if (ret)
return ret;
}
ret = spi_master_suspend(master);
ret = spi_controller_suspend(host);
if (ret)
return ret;
@ -1237,8 +1237,8 @@ static int spi_qup_suspend(struct device *device)
static int spi_qup_resume(struct device *device)
{
struct spi_master *master = dev_get_drvdata(device);
struct spi_qup *controller = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(device);
struct spi_qup *controller = spi_controller_get_devdata(host);
int ret;
ret = clk_prepare_enable(controller->iclk);
@ -1255,7 +1255,7 @@ static int spi_qup_resume(struct device *device)
if (ret)
goto disable_clk;
ret = spi_master_resume(master);
ret = spi_controller_resume(host);
if (ret)
goto disable_clk;
@ -1270,8 +1270,8 @@ disable_clk:
static void spi_qup_remove(struct platform_device *pdev)
{
struct spi_master *master = dev_get_drvdata(&pdev->dev);
struct spi_qup *controller = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(&pdev->dev);
struct spi_qup *controller = spi_controller_get_devdata(host);
int ret;
ret = pm_runtime_get_sync(&pdev->dev);
@ -1289,7 +1289,7 @@ static void spi_qup_remove(struct platform_device *pdev)
ERR_PTR(ret));
}
spi_qup_release_dma(master);
spi_qup_release_dma(host);
pm_runtime_put_noidle(&pdev->dev);
pm_runtime_disable(&pdev->dev);

36
drivers/spi/spi-rb4xx.c
View File

@ -80,7 +80,7 @@ static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
static void rb4xx_set_cs(struct spi_device *spi, bool enable)
{
struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
struct rb4xx_spi *rbspi = spi_controller_get_devdata(spi->controller);
/*
* Setting CS is done along with bitbanging the actual values,
@ -92,10 +92,10 @@ static void rb4xx_set_cs(struct spi_device *spi, bool enable)
AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
}
static int rb4xx_transfer_one(struct spi_master *master,
static int rb4xx_transfer_one(struct spi_controller *host,
struct spi_device *spi, struct spi_transfer *t)
{
struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
struct rb4xx_spi *rbspi = spi_controller_get_devdata(host);
int i;
u32 spi_ioc;
u8 *rx_buf;
@ -126,14 +126,14 @@ static int rb4xx_transfer_one(struct spi_master *master,
continue;
rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
}
spi_finalize_current_transfer(master);
spi_finalize_current_transfer(host);
return 0;
}
static int rb4xx_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct spi_controller *host;
struct clk *ahb_clk;
struct rb4xx_spi *rbspi;
int err;
@ -143,31 +143,31 @@ static int rb4xx_spi_probe(struct platform_device *pdev)
if (IS_ERR(spi_base))
return PTR_ERR(spi_base);
master = devm_spi_alloc_master(&pdev->dev, sizeof(*rbspi));
if (!master)
host = devm_spi_alloc_host(&pdev->dev, sizeof(*rbspi));
if (!host)
return -ENOMEM;
ahb_clk = devm_clk_get(&pdev->dev, "ahb");
if (IS_ERR(ahb_clk))
return PTR_ERR(ahb_clk);
master->dev.of_node = pdev->dev.of_node;
master->bus_num = 0;
master->num_chipselect = 3;
master->mode_bits = SPI_TX_DUAL;
master->bits_per_word_mask = SPI_BPW_MASK(8);
master->flags = SPI_CONTROLLER_MUST_TX;
master->transfer_one = rb4xx_transfer_one;
master->set_cs = rb4xx_set_cs;
host->dev.of_node = pdev->dev.of_node;
host->bus_num = 0;
host->num_chipselect = 3;
host->mode_bits = SPI_TX_DUAL;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->flags = SPI_CONTROLLER_MUST_TX;
host->transfer_one = rb4xx_transfer_one;
host->set_cs = rb4xx_set_cs;
rbspi = spi_master_get_devdata(master);
rbspi = spi_controller_get_devdata(host);
rbspi->base = spi_base;
rbspi->clk = ahb_clk;
platform_set_drvdata(pdev, rbspi);
err = devm_spi_register_master(&pdev->dev, master);
err = devm_spi_register_controller(&pdev->dev, host);
if (err) {
dev_err(&pdev->dev, "failed to register SPI master\n");
dev_err(&pdev->dev, "failed to register SPI host\n");
return err;
}

2
drivers/spi/spi-realtek-rtl.c
View File

@ -153,7 +153,7 @@ static int realtek_rtl_spi_probe(struct platform_device *pdev)
struct rtspi *rtspi;
int err;
ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi));
ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*rtspi));
if (!ctrl) {
dev_err(&pdev->dev, "Error allocating SPI controller\n");
return -ENOMEM;

30
drivers/spi/spi-rockchip-sfc.c
View File

@ -487,7 +487,7 @@ static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master);
struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller);
u32 len = op->data.nbytes;
int ret;
@ -523,7 +523,7 @@ static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op
static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
{
struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master);
struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller);
op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
@ -557,22 +557,22 @@ static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id)
static int rockchip_sfc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct spi_master *master;
struct spi_controller *host;
struct rockchip_sfc *sfc;
int ret;
master = devm_spi_alloc_master(&pdev->dev, sizeof(*sfc));
if (!master)
host = devm_spi_alloc_host(&pdev->dev, sizeof(*sfc));
if (!host)
return -ENOMEM;
master->flags = SPI_CONTROLLER_HALF_DUPLEX;
master->mem_ops = &rockchip_sfc_mem_ops;
master->dev.of_node = pdev->dev.of_node;
master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL;
master->max_speed_hz = SFC_MAX_SPEED;
master->num_chipselect = SFC_MAX_CHIPSELECT_NUM;
host->flags = SPI_CONTROLLER_HALF_DUPLEX;
host->mem_ops = &rockchip_sfc_mem_ops;
host->dev.of_node = pdev->dev.of_node;
host->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL;
host->max_speed_hz = SFC_MAX_SPEED;
host->num_chipselect = SFC_MAX_CHIPSELECT_NUM;
sfc = spi_master_get_devdata(master);
sfc = spi_controller_get_devdata(host);
sfc->dev = dev;
sfc->regbase = devm_platform_ioremap_resource(pdev, 0);
@ -640,7 +640,7 @@ static int rockchip_sfc_probe(struct platform_device *pdev)
sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
sfc->version = rockchip_sfc_get_version(sfc);
ret = spi_register_master(master);
ret = spi_register_controller(host);
if (ret)
goto err_irq;
@ -656,10 +656,10 @@ err_hclk:
static void rockchip_sfc_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct spi_controller *host = platform_get_drvdata(pdev);
struct rockchip_sfc *sfc = platform_get_drvdata(pdev);
spi_unregister_master(master);
spi_unregister_controller(host);
clk_disable_unprepare(sfc->clk);
clk_disable_unprepare(sfc->hclk);

58
drivers/spi/spi-rockchip.c
View File

@ -104,8 +104,8 @@
#define CR0_XFM_RO 0x2
#define CR0_OPM_OFFSET 20
#define CR0_OPM_MASTER 0x0
#define CR0_OPM_SLAVE 0x1
#define CR0_OPM_HOST 0x0
#define CR0_OPM_TARGET 0x1
#define CR0_SOI_OFFSET 23
@ -125,7 +125,7 @@
#define SR_TF_EMPTY (1 << 2)
#define SR_RF_EMPTY (1 << 3)
#define SR_RF_FULL (1 << 4)
#define SR_SLAVE_TX_BUSY (1 << 5)
#define SR_TARGET_TX_BUSY (1 << 5)
/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
#define INT_MASK 0x1f
@ -151,7 +151,7 @@
#define RXDMA (1 << 0)
#define TXDMA (1 << 1)
/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
/* sclk_out: spi host internal logic in rk3x can support 50Mhz */
#define MAX_SCLK_OUT 50000000U
/*
@ -194,8 +194,8 @@ struct rockchip_spi {
bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
bool slave_abort;
bool cs_inactive; /* spi slave tansmition stop when cs inactive */
bool target_abort;
bool cs_inactive; /* spi target tansmition stop when cs inactive */
bool cs_high_supported; /* native CS supports active-high polarity */
struct spi_transfer *xfer; /* Store xfer temporarily */
@ -206,13 +206,13 @@ static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
}
static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool target_mode)
{
unsigned long timeout = jiffies + msecs_to_jiffies(5);
do {
if (slave_mode) {
if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
if (target_mode) {
if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) &&
!((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
return;
} else {
@ -351,9 +351,9 @@ static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
struct spi_controller *ctlr = dev_id;
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
/* When int_cs_inactive comes, spi slave abort */
/* When int_cs_inactive comes, spi target abort */
if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
ctlr->slave_abort(ctlr);
ctlr->target_abort(ctlr);
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
@ -405,7 +405,7 @@ static void rockchip_spi_dma_rxcb(void *data)
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
int state = atomic_fetch_andnot(RXDMA, &rs->state);
if (state & TXDMA && !rs->slave_abort)
if (state & TXDMA && !rs->target_abort)
return;
if (rs->cs_inactive)
@ -421,11 +421,11 @@ static void rockchip_spi_dma_txcb(void *data)
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
int state = atomic_fetch_andnot(TXDMA, &rs->state);
if (state & RXDMA && !rs->slave_abort)
if (state & RXDMA && !rs->target_abort)
return;
/* Wait until the FIFO data completely. */
wait_for_tx_idle(rs, ctlr->slave);
wait_for_tx_idle(rs, ctlr->target);
spi_enable_chip(rs, false);
spi_finalize_current_transfer(ctlr);
@ -525,7 +525,7 @@ static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
static int rockchip_spi_config(struct rockchip_spi *rs,
struct spi_device *spi, struct spi_transfer *xfer,
bool use_dma, bool slave_mode)
bool use_dma, bool target_mode)
{
u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
| CR0_BHT_8BIT << CR0_BHT_OFFSET
@ -534,9 +534,9 @@ static int rockchip_spi_config(struct rockchip_spi *rs,
u32 cr1;
u32 dmacr = 0;
if (slave_mode)
cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
rs->slave_abort = false;
if (target_mode)
cr0 |= CR0_OPM_TARGET << CR0_OPM_OFFSET;
rs->target_abort = false;
cr0 |= rs->rsd << CR0_RSD_OFFSET;
cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
@ -614,7 +614,7 @@ static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
return ROCKCHIP_SPI_MAX_TRANLEN;
}
static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
static int rockchip_spi_target_abort(struct spi_controller *ctlr)
{
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
u32 rx_fifo_left;
@ -659,7 +659,7 @@ out:
dmaengine_terminate_sync(ctlr->dma_tx);
atomic_set(&rs->state, 0);
spi_enable_chip(rs, false);
rs->slave_abort = true;
rs->target_abort = true;
spi_finalize_current_transfer(ctlr);
return 0;
@ -697,7 +697,7 @@ static int rockchip_spi_transfer_one(
rs->xfer = xfer;
use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->target);
if (ret)
return ret;
@ -757,15 +757,15 @@ static int rockchip_spi_probe(struct platform_device *pdev)
struct resource *mem;
struct device_node *np = pdev->dev.of_node;
u32 rsd_nsecs, num_cs;
bool slave_mode;
bool target_mode;
slave_mode = of_property_read_bool(np, "spi-slave");
target_mode = of_property_read_bool(np, "spi-slave");
if (slave_mode)
ctlr = spi_alloc_slave(&pdev->dev,
if (target_mode)
ctlr = spi_alloc_target(&pdev->dev,
sizeof(struct rockchip_spi));
else
ctlr = spi_alloc_master(&pdev->dev,
ctlr = spi_alloc_host(&pdev->dev,
sizeof(struct rockchip_spi));
if (!ctlr)
@ -854,9 +854,9 @@ static int rockchip_spi_probe(struct platform_device *pdev)
ctlr->auto_runtime_pm = true;
ctlr->bus_num = pdev->id;
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
if (slave_mode) {
if (target_mode) {
ctlr->mode_bits |= SPI_NO_CS;
ctlr->slave_abort = rockchip_spi_slave_abort;
ctlr->target_abort = rockchip_spi_target_abort;
} else {
ctlr->flags = SPI_CONTROLLER_GPIO_SS;
ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
@ -911,7 +911,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
case ROCKCHIP_SPI_VER2_TYPE2:
rs->cs_high_supported = true;
ctlr->mode_bits |= SPI_CS_HIGH;
if (ctlr->can_dma && slave_mode)
if (ctlr->can_dma && target_mode)
rs->cs_inactive = true;
else
rs->cs_inactive = false;

2
drivers/spi/spi-rspi.c
View File

@ -1294,7 +1294,7 @@ static int rspi_probe(struct platform_device *pdev)
const struct spi_ops *ops;
unsigned long clksrc;
ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
ctlr = spi_alloc_host(&pdev->dev, sizeof(struct rspi_data));
if (ctlr == NULL)
return -ENOMEM;

2
drivers/spi/spi-rzv2m-csi.c
View File

@ -555,7 +555,7 @@ static int rzv2m_csi_probe(struct platform_device *pdev)
int irq;
int ret;
controller = devm_spi_alloc_master(dev, sizeof(*csi));
controller = devm_spi_alloc_host(dev, sizeof(*csi));
if (!controller)
return -ENOMEM;

126
drivers/spi/spi-s3c64xx.c
View File

@ -163,9 +163,9 @@ struct s3c64xx_spi_port_config {
* struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
* @clk: Pointer to the spi clock.
* @src_clk: Pointer to the clock used to generate SPI signals.
* @ioclk: Pointer to the i/o clock between master and slave
* @ioclk: Pointer to the i/o clock between host and target
* @pdev: Pointer to device's platform device data
* @master: Pointer to the SPI Protocol master.
* @host: Pointer to the SPI Protocol host.
* @cntrlr_info: Platform specific data for the controller this driver manages.
* @lock: Controller specific lock.
* @state: Set of FLAGS to indicate status.
@ -186,7 +186,7 @@ struct s3c64xx_spi_driver_data {
struct clk *src_clk;
struct clk *ioclk;
struct platform_device *pdev;
struct spi_master *master;
struct spi_controller *host;
struct s3c64xx_spi_info *cntrlr_info;
spinlock_t lock;
unsigned long sfr_start;
@ -329,7 +329,7 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
{
struct s3c64xx_spi_driver_data *sdd =
spi_master_get_devdata(spi->master);
spi_controller_get_devdata(spi->controller);
if (sdd->cntrlr_info->no_cs)
return;
@ -351,9 +351,9 @@ static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
}
}
static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi)
{
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
if (is_polling(sdd))
return 0;
@ -381,9 +381,9 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
return 0;
}
static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi)
{
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
if (is_polling(sdd))
return 0;
@ -399,11 +399,11 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
return 0;
}
static bool s3c64xx_spi_can_dma(struct spi_master *master,
static bool s3c64xx_spi_can_dma(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *xfer)
{
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
@ -712,10 +712,10 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
static int s3c64xx_spi_prepare_message(struct spi_master *master,
static int s3c64xx_spi_prepare_message(struct spi_controller *host,
struct spi_message *msg)
{
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
struct spi_device *spi = msg->spi;
struct s3c64xx_spi_csinfo *cs = spi->controller_data;
@ -736,11 +736,11 @@ static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
}
static int s3c64xx_spi_transfer_one(struct spi_master *master,
static int s3c64xx_spi_transfer_one(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *xfer)
{
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
const void *tx_buf = NULL;
void *rx_buf = NULL;
@ -890,15 +890,15 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
return status;
}
static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
static struct s3c64xx_spi_csinfo *s3c64xx_get_target_ctrldata(
struct spi_device *spi)
{
struct s3c64xx_spi_csinfo *cs;
struct device_node *slave_np, *data_np = NULL;
struct device_node *target_np, *data_np = NULL;
u32 fb_delay = 0;
slave_np = spi->dev.of_node;
if (!slave_np) {
target_np = spi->dev.of_node;
if (!target_np) {
dev_err(&spi->dev, "device node not found\n");
return ERR_PTR(-EINVAL);
}
@ -907,7 +907,7 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
if (!cs)
return ERR_PTR(-ENOMEM);
data_np = of_get_child_by_name(slave_np, "controller-data");
data_np = of_get_child_by_name(target_np, "controller-data");
if (!data_np) {
dev_info(&spi->dev, "feedback delay set to default (0)\n");
return cs;
@ -932,9 +932,9 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
int err;
int div;
sdd = spi_master_get_devdata(spi->master);
sdd = spi_controller_get_devdata(spi->controller);
if (spi->dev.of_node) {
cs = s3c64xx_get_slave_ctrldata(spi);
cs = s3c64xx_get_target_ctrldata(spi);
spi->controller_data = cs;
}
@ -1022,7 +1022,7 @@ static void s3c64xx_spi_cleanup(struct spi_device *spi)
static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
{
struct s3c64xx_spi_driver_data *sdd = data;
struct spi_master *spi = sdd->master;
struct spi_controller *spi = sdd->host;
unsigned int val, clr = 0;
val = readl(sdd->regs + S3C64XX_SPI_STATUS);
@ -1151,7 +1151,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
struct resource *mem_res;
struct s3c64xx_spi_driver_data *sdd;
struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
struct spi_master *master;
struct spi_controller *host;
int ret, irq;
char clk_name[16];
@ -1169,16 +1169,16 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
master = devm_spi_alloc_master(&pdev->dev, sizeof(*sdd));
if (!master)
host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd));
if (!host)
return dev_err_probe(&pdev->dev, -ENOMEM,
"Unable to allocate SPI Master\n");
"Unable to allocate SPI Host\n");
platform_set_drvdata(pdev, master);
platform_set_drvdata(pdev, host);
sdd = spi_master_get_devdata(master);
sdd = spi_controller_get_devdata(host);
sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
sdd->master = master;
sdd->host = host;
sdd->cntrlr_info = sci;
sdd->pdev = pdev;
if (pdev->dev.of_node) {
@ -1196,27 +1196,27 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
sdd->tx_dma.direction = DMA_MEM_TO_DEV;
sdd->rx_dma.direction = DMA_DEV_TO_MEM;
master->dev.of_node = pdev->dev.of_node;
master->bus_num = sdd->port_id;
master->setup = s3c64xx_spi_setup;
master->cleanup = s3c64xx_spi_cleanup;
master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
master->prepare_message = s3c64xx_spi_prepare_message;
master->transfer_one = s3c64xx_spi_transfer_one;
master->max_transfer_size = s3c64xx_spi_max_transfer_size;
master->num_chipselect = sci->num_cs;
master->use_gpio_descriptors = true;
master->dma_alignment = 8;
master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
SPI_BPW_MASK(8);
host->dev.of_node = pdev->dev.of_node;
host->bus_num = sdd->port_id;
host->setup = s3c64xx_spi_setup;
host->cleanup = s3c64xx_spi_cleanup;
host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
host->prepare_message = s3c64xx_spi_prepare_message;
host->transfer_one = s3c64xx_spi_transfer_one;
host->max_transfer_size = s3c64xx_spi_max_transfer_size;
host->num_chipselect = sci->num_cs;
host->use_gpio_descriptors = true;
host->dma_alignment = 8;
host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
SPI_BPW_MASK(8);
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
if (sdd->port_conf->has_loopback)
master->mode_bits |= SPI_LOOP;
master->auto_runtime_pm = true;
host->mode_bits |= SPI_LOOP;
host->auto_runtime_pm = true;
if (!is_polling(sdd))
master->can_dma = s3c64xx_spi_can_dma;
host->can_dma = s3c64xx_spi_can_dma;
sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
if (IS_ERR(sdd->regs))
@ -1271,14 +1271,14 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
sdd->regs + S3C64XX_SPI_INT_EN);
ret = devm_spi_register_master(&pdev->dev, master);
ret = devm_spi_register_controller(&pdev->dev, host);
if (ret != 0) {
dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret);
goto err_pm_put;
}
dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
sdd->port_id, master->num_chipselect);
dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n",
sdd->port_id, host->num_chipselect);
dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
@ -1297,8 +1297,8 @@ err_pm_put:
static void s3c64xx_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct spi_controller *host = platform_get_drvdata(pdev);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
pm_runtime_get_sync(&pdev->dev);
@ -1317,10 +1317,10 @@ static void s3c64xx_spi_remove(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int s3c64xx_spi_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
int ret = spi_master_suspend(master);
int ret = spi_controller_suspend(host);
if (ret)
return ret;
@ -1335,8 +1335,8 @@ static int s3c64xx_spi_suspend(struct device *dev)
static int s3c64xx_spi_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
int ret;
@ -1347,15 +1347,15 @@ static int s3c64xx_spi_resume(struct device *dev)
if (ret < 0)
return ret;
return spi_master_resume(master);
return spi_controller_resume(host);
}
#endif /* CONFIG_PM_SLEEP */
#ifdef CONFIG_PM
static int s3c64xx_spi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
clk_disable_unprepare(sdd->clk);
clk_disable_unprepare(sdd->src_clk);
@ -1366,8 +1366,8 @@ static int s3c64xx_spi_runtime_suspend(struct device *dev)
static int s3c64xx_spi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
int ret;
if (sdd->port_conf->clk_ioclk) {

48
drivers/spi/spi-sc18is602.c
View File

@ -30,7 +30,7 @@ enum chips { sc18is602, sc18is602b, sc18is603 };
#define SC18IS602_MODE_CLOCK_DIV_128 0x3
struct sc18is602 {
struct spi_master *master;
struct spi_controller *host;
struct device *dev;
u8 ctrl;
u32 freq;
@ -179,10 +179,10 @@ static int sc18is602_check_transfer(struct spi_device *spi,
return 0;
}
static int sc18is602_transfer_one(struct spi_master *master,
static int sc18is602_transfer_one(struct spi_controller *host,
struct spi_message *m)
{
struct sc18is602 *hw = spi_master_get_devdata(master);
struct sc18is602 *hw = spi_controller_get_devdata(host);
struct spi_device *spi = m->spi;
struct spi_transfer *t;
int status = 0;
@ -213,7 +213,7 @@ static int sc18is602_transfer_one(struct spi_master *master,
spi_transfer_delay_exec(t);
}
m->status = status;
spi_finalize_current_message(master);
spi_finalize_current_message(host);
return status;
}
@ -225,7 +225,7 @@ static size_t sc18is602_max_transfer_size(struct spi_device *spi)
static int sc18is602_setup(struct spi_device *spi)
{
struct sc18is602 *hw = spi_master_get_devdata(spi->master);
struct sc18is602 *hw = spi_controller_get_devdata(spi->controller);
/* SC18IS602 does not support CS2 */
if (hw->id == sc18is602 && (spi_get_chipselect(spi, 0) == 2))
@ -241,17 +241,17 @@ static int sc18is602_probe(struct i2c_client *client)
struct device_node *np = dev->of_node;
struct sc18is602_platform_data *pdata = dev_get_platdata(dev);
struct sc18is602 *hw;
struct spi_master *master;
struct spi_controller *host;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
return -EINVAL;
master = devm_spi_alloc_master(dev, sizeof(struct sc18is602));
if (!master)
host = devm_spi_alloc_host(dev, sizeof(struct sc18is602));
if (!host)
return -ENOMEM;
hw = spi_master_get_devdata(master);
hw = spi_controller_get_devdata(host);
i2c_set_clientdata(client, hw);
/* assert reset and then release */
@ -260,7 +260,7 @@ static int sc18is602_probe(struct i2c_client *client)
return PTR_ERR(hw->reset);
gpiod_set_value_cansleep(hw->reset, 0);
hw->master = master;
hw->host = host;
hw->client = client;
hw->dev = dev;
hw->ctrl = 0xff;
@ -273,11 +273,11 @@ static int sc18is602_probe(struct i2c_client *client)
switch (hw->id) {
case sc18is602:
case sc18is602b:
master->num_chipselect = 4;
host->num_chipselect = 4;
hw->freq = SC18IS602_CLOCK;
break;
case sc18is603:
master->num_chipselect = 2;
host->num_chipselect = 2;
if (pdata) {
hw->freq = pdata->clock_frequency;
} else {
@ -292,18 +292,18 @@ static int sc18is602_probe(struct i2c_client *client)
hw->freq = SC18IS602_CLOCK;
break;
}
master->bus_num = np ? -1 : client->adapter->nr;
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
master->bits_per_word_mask = SPI_BPW_MASK(8);
master->setup = sc18is602_setup;
master->transfer_one_message = sc18is602_transfer_one;
master->max_transfer_size = sc18is602_max_transfer_size;
master->max_message_size = sc18is602_max_transfer_size;
master->dev.of_node = np;
master->min_speed_hz = hw->freq / 128;
master->max_speed_hz = hw->freq / 4;
host->bus_num = np ? -1 : client->adapter->nr;
host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->setup = sc18is602_setup;
host->transfer_one_message = sc18is602_transfer_one;
host->max_transfer_size = sc18is602_max_transfer_size;
host->max_message_size = sc18is602_max_transfer_size;
host->dev.of_node = np;
host->min_speed_hz = hw->freq / 128;
host->max_speed_hz = hw->freq / 4;
return devm_spi_register_master(dev, master);
return devm_spi_register_controller(dev, host);
}
static const struct i2c_device_id sc18is602_id[] = {
@ -342,6 +342,6 @@ static struct i2c_driver sc18is602_driver = {
module_i2c_driver(sc18is602_driver);
MODULE_DESCRIPTION("SC18IS602/603 SPI Master Driver");
MODULE_DESCRIPTION("SC18IS602/603 SPI Host Driver");
MODULE_AUTHOR("Guenter Roeck");
MODULE_LICENSE("GPL");

4
drivers/spi/spi-sh-hspi.c
View File

@ -82,7 +82,7 @@ static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
}
/*
* spi master function
* spi host function
*/
#define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
@ -224,7 +224,7 @@ static int hspi_probe(struct platform_device *pdev)
return -EINVAL;
}
ctlr = spi_alloc_master(&pdev->dev, sizeof(*hspi));
ctlr = spi_alloc_host(&pdev->dev, sizeof(*hspi));
if (!ctlr)
return -ENOMEM;

50
drivers/spi/spi-sh-msiof.c
View File

@ -54,7 +54,7 @@ struct sh_msiof_spi_priv {
dma_addr_t rx_dma_addr;
bool native_cs_inited;
bool native_cs_high;
bool slave_aborted;
bool target_aborted;
};
#define MAX_SS 3 /* Maximum number of native chip selects */
@ -361,7 +361,7 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
if (spi_controller_is_slave(p->ctlr)) {
if (spi_controller_is_target(p->ctlr)) {
sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
} else {
sh_msiof_write(p, SITMDR1,
@ -553,7 +553,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
spi_controller_get_devdata(spi->controller);
u32 clr, set, tmp;
if (spi_get_csgpiod(spi, 0) || spi_controller_is_slave(p->ctlr))
if (spi_get_csgpiod(spi, 0) || spi_controller_is_target(p->ctlr))
return 0;
if (p->native_cs_inited &&
@ -602,11 +602,11 @@ static int sh_msiof_prepare_message(struct spi_controller *ctlr,
static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
{
bool slave = spi_controller_is_slave(p->ctlr);
bool target = spi_controller_is_target(p->ctlr);
int ret = 0;
/* setup clock and rx/tx signals */
if (!slave)
if (!target)
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
if (rx_buf && !ret)
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
@ -614,7 +614,7 @@ static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
/* start by setting frame bit */
if (!ret && !slave)
if (!ret && !target)
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
return ret;
@ -622,27 +622,27 @@ static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
{
bool slave = spi_controller_is_slave(p->ctlr);
bool target = spi_controller_is_target(p->ctlr);
int ret = 0;
/* shut down frame, rx/tx and clock signals */
if (!slave)
if (!target)
ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
if (!ret)
ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
if (rx_buf && !ret)
ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
if (!ret && !slave)
if (!ret && !target)
ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
return ret;
}
static int sh_msiof_slave_abort(struct spi_controller *ctlr)
static int sh_msiof_target_abort(struct spi_controller *ctlr)
{
struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
p->slave_aborted = true;
p->target_aborted = true;
complete(&p->done);
complete(&p->done_txdma);
return 0;
@ -651,9 +651,9 @@ static int sh_msiof_slave_abort(struct spi_controller *ctlr)
static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
struct completion *x)
{
if (spi_controller_is_slave(p->ctlr)) {
if (spi_controller_is_target(p->ctlr)) {
if (wait_for_completion_interruptible(x) ||
p->slave_aborted) {
p->target_aborted) {
dev_dbg(&p->pdev->dev, "interrupted\n");
return -EINTR;
}
@ -699,7 +699,7 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
tx_fifo(p, tx_buf, words, fifo_shift);
reinit_completion(&p->done);
p->slave_aborted = false;
p->target_aborted = false;
ret = sh_msiof_spi_start(p, rx_buf);
if (ret) {
@ -796,7 +796,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
reinit_completion(&p->done);
if (tx)
reinit_completion(&p->done_txdma);
p->slave_aborted = false;
p->target_aborted = false;
/* Now start DMA */
if (rx)
@ -925,7 +925,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr,
sh_msiof_spi_reset_regs(p);
/* setup clocks (clock already enabled in chipselect()) */
if (!spi_controller_is_slave(p->ctlr))
if (!spi_controller_is_target(p->ctlr))
sh_msiof_spi_set_clk_regs(p, t);
while (ctlr->dma_tx && len > 15) {
@ -1101,11 +1101,11 @@ static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
if (!info)
return NULL;
info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
: MSIOF_SPI_MASTER;
info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_TARGET
: MSIOF_SPI_HOST;
/* Parse the MSIOF properties */
if (info->mode == MSIOF_SPI_MASTER)
if (info->mode == MSIOF_SPI_HOST)
of_property_read_u32(np, "num-cs", &num_cs);
of_property_read_u32(np, "renesas,tx-fifo-size",
&info->tx_fifo_override);
@ -1279,12 +1279,12 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
return -ENXIO;
}
if (info->mode == MSIOF_SPI_SLAVE)
ctlr = spi_alloc_slave(&pdev->dev,
sizeof(struct sh_msiof_spi_priv));
if (info->mode == MSIOF_SPI_TARGET)
ctlr = spi_alloc_target(&pdev->dev,
sizeof(struct sh_msiof_spi_priv));
else
ctlr = spi_alloc_master(&pdev->dev,
sizeof(struct sh_msiof_spi_priv));
ctlr = spi_alloc_host(&pdev->dev,
sizeof(struct sh_msiof_spi_priv));
if (ctlr == NULL)
return -ENOMEM;
@ -1347,7 +1347,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
ctlr->dev.of_node = pdev->dev.of_node;
ctlr->setup = sh_msiof_spi_setup;
ctlr->prepare_message = sh_msiof_prepare_message;
ctlr->slave_abort = sh_msiof_slave_abort;
ctlr->target_abort = sh_msiof_target_abort;
ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
ctlr->auto_runtime_pm = true;
ctlr->transfer_one = sh_msiof_transfer_one;

24
drivers/spi/spi-sh-sci.c
View File

@ -56,17 +56,17 @@ static inline void setbits(struct sh_sci_spi *sp, int bits, int on)
static inline void setsck(struct spi_device *dev, int on)
{
setbits(spi_master_get_devdata(dev->master), PIN_SCK, on);
setbits(spi_controller_get_devdata(dev->controller), PIN_SCK, on);
}
static inline void setmosi(struct spi_device *dev, int on)
{
setbits(spi_master_get_devdata(dev->master), PIN_TXD, on);
setbits(spi_controller_get_devdata(dev->controller), PIN_TXD, on);
}
static inline u32 getmiso(struct spi_device *dev)
{
struct sh_sci_spi *sp = spi_master_get_devdata(dev->master);
struct sh_sci_spi *sp = spi_controller_get_devdata(dev->controller);
return (ioread8(SCSPTR(sp)) & PIN_RXD) ? 1 : 0;
}
@ -105,7 +105,7 @@ static u32 sh_sci_spi_txrx_mode3(struct spi_device *spi,
static void sh_sci_spi_chipselect(struct spi_device *dev, int value)
{
struct sh_sci_spi *sp = spi_master_get_devdata(dev->master);
struct sh_sci_spi *sp = spi_controller_get_devdata(dev->controller);
if (sp->info->chip_select)
(sp->info->chip_select)(sp->info, spi_get_chipselect(dev, 0), value);
@ -114,18 +114,18 @@ static void sh_sci_spi_chipselect(struct spi_device *dev, int value)
static int sh_sci_spi_probe(struct platform_device *dev)
{
struct resource *r;
struct spi_master *master;
struct spi_controller *host;
struct sh_sci_spi *sp;
int ret;
master = spi_alloc_master(&dev->dev, sizeof(struct sh_sci_spi));
if (master == NULL) {
dev_err(&dev->dev, "failed to allocate spi master\n");
host = spi_alloc_host(&dev->dev, sizeof(struct sh_sci_spi));
if (host == NULL) {
dev_err(&dev->dev, "failed to allocate spi host\n");
ret = -ENOMEM;
goto err0;
}
sp = spi_master_get_devdata(master);
sp = spi_controller_get_devdata(host);
platform_set_drvdata(dev, sp);
sp->info = dev_get_platdata(&dev->dev);
@ -136,7 +136,7 @@ static int sh_sci_spi_probe(struct platform_device *dev)
}
/* setup spi bitbang adaptor */
sp->bitbang.master = master;
sp->bitbang.master = host;
sp->bitbang.master->bus_num = sp->info->bus_num;
sp->bitbang.master->num_chipselect = sp->info->num_chipselect;
sp->bitbang.chipselect = sh_sci_spi_chipselect;
@ -166,7 +166,7 @@ static int sh_sci_spi_probe(struct platform_device *dev)
setbits(sp, PIN_INIT, 0);
iounmap(sp->membase);
err1:
spi_master_put(sp->bitbang.master);
spi_controller_put(sp->bitbang.master);
err0:
return ret;
}
@ -178,7 +178,7 @@ static void sh_sci_spi_remove(struct platform_device *dev)
spi_bitbang_stop(&sp->bitbang);
setbits(sp, PIN_INIT, 0);
iounmap(sp->membase);
spi_master_put(sp->bitbang.master);
spi_controller_put(sp->bitbang.master);
}
static struct platform_driver sh_sci_spi_drv = {

34
drivers/spi/spi-sh.c
View File

@ -72,7 +72,7 @@
struct spi_sh_data {
void __iomem *addr;
int irq;
struct spi_master *master;
struct spi_controller *host;
unsigned long cr1;
wait_queue_head_t wait;
int width;
@ -327,7 +327,7 @@ static int spi_sh_transfer_one_message(struct spi_controller *ctlr,
static int spi_sh_setup(struct spi_device *spi)
{
struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
pr_debug("%s: enter\n", __func__);
@ -346,7 +346,7 @@ static int spi_sh_setup(struct spi_device *spi)
static void spi_sh_cleanup(struct spi_device *spi)
{
struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
pr_debug("%s: enter\n", __func__);
@ -381,14 +381,14 @@ static void spi_sh_remove(struct platform_device *pdev)
{
struct spi_sh_data *ss = platform_get_drvdata(pdev);
spi_unregister_master(ss->master);
spi_unregister_controller(ss->host);
free_irq(ss->irq, ss);
}
static int spi_sh_probe(struct platform_device *pdev)
{
struct resource *res;
struct spi_master *master;
struct spi_controller *host;
struct spi_sh_data *ss;
int ret, irq;
@ -403,13 +403,13 @@ static int spi_sh_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
master = devm_spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
if (master == NULL) {
dev_err(&pdev->dev, "spi_alloc_master error.\n");
host = devm_spi_alloc_host(&pdev->dev, sizeof(struct spi_sh_data));
if (host == NULL) {
dev_err(&pdev->dev, "devm_spi_alloc_host error.\n");
return -ENOMEM;
}
ss = spi_master_get_devdata(master);
ss = spi_controller_get_devdata(host);
platform_set_drvdata(pdev, ss);
switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
@ -424,7 +424,7 @@ static int spi_sh_probe(struct platform_device *pdev)
return -ENODEV;
}
ss->irq = irq;
ss->master = master;
ss->host = host;
ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (ss->addr == NULL) {
dev_err(&pdev->dev, "ioremap error.\n");
@ -438,15 +438,15 @@ static int spi_sh_probe(struct platform_device *pdev)
return ret;
}
master->num_chipselect = 2;
master->bus_num = pdev->id;
master->setup = spi_sh_setup;
master->transfer_one_message = spi_sh_transfer_one_message;
master->cleanup = spi_sh_cleanup;
host->num_chipselect = 2;
host->bus_num = pdev->id;
host->setup = spi_sh_setup;
host->transfer_one_message = spi_sh_transfer_one_message;
host->cleanup = spi_sh_cleanup;
ret = spi_register_master(master);
ret = spi_register_controller(host);
if (ret < 0) {
printk(KERN_ERR "spi_register_master error.\n");
printk(KERN_ERR "spi_register_controller error.\n");
goto error3;
}

80
drivers/spi/spi-sifive.c
View File

@ -128,9 +128,9 @@ static void sifive_spi_init(struct sifive_spi *spi)
}
static int
sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
sifive_spi_prepare_message(struct spi_controller *host, struct spi_message *msg)
{
struct sifive_spi *spi = spi_master_get_devdata(master);
struct sifive_spi *spi = spi_controller_get_devdata(host);
struct spi_device *device = msg->spi;
/* Update the chip select polarity */
@ -152,7 +152,7 @@ sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
{
struct sifive_spi *spi = spi_master_get_devdata(device->master);
struct sifive_spi *spi = spi_controller_get_devdata(device->controller);
/* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
if (device->mode & SPI_CS_HIGH)
@ -252,10 +252,10 @@ static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
}
static int
sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
sifive_spi_transfer_one(struct spi_controller *host, struct spi_device *device,
struct spi_transfer *t)
{
struct sifive_spi *spi = spi_master_get_devdata(master);
struct sifive_spi *spi = spi_controller_get_devdata(host);
int poll = sifive_spi_prep_transfer(spi, device, t);
const u8 *tx_ptr = t->tx_buf;
u8 *rx_ptr = t->rx_buf;
@ -294,35 +294,35 @@ static int sifive_spi_probe(struct platform_device *pdev)
struct sifive_spi *spi;
int ret, irq, num_cs;
u32 cs_bits, max_bits_per_word;
struct spi_master *master;
struct spi_controller *host;
master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi));
if (!master) {
host = spi_alloc_host(&pdev->dev, sizeof(struct sifive_spi));
if (!host) {
dev_err(&pdev->dev, "out of memory\n");
return -ENOMEM;
}
spi = spi_master_get_devdata(master);
spi = spi_controller_get_devdata(host);
init_completion(&spi->done);
platform_set_drvdata(pdev, master);
platform_set_drvdata(pdev, host);
spi->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(spi->regs)) {
ret = PTR_ERR(spi->regs);
goto put_master;
goto put_host;
}
spi->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(spi->clk)) {
dev_err(&pdev->dev, "Unable to find bus clock\n");
ret = PTR_ERR(spi->clk);
goto put_master;
goto put_host;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto put_master;
goto put_host;
}
/* Optional parameters */
@ -339,14 +339,14 @@ static int sifive_spi_probe(struct platform_device *pdev)
if (!ret && max_bits_per_word < 8) {
dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
ret = -EINVAL;
goto put_master;
goto put_host;
}
/* Spin up the bus clock before hitting registers */
ret = clk_prepare_enable(spi->clk);
if (ret) {
dev_err(&pdev->dev, "Unable to enable bus clock\n");
goto put_master;
goto put_host;
}
/* probe the number of CS lines */
@ -362,30 +362,30 @@ static int sifive_spi_probe(struct platform_device *pdev)
num_cs = ilog2(cs_bits) + 1;
if (num_cs > SIFIVE_SPI_MAX_CS) {
dev_err(&pdev->dev, "Invalid number of spi slaves\n");
dev_err(&pdev->dev, "Invalid number of spi targets\n");
ret = -EINVAL;
goto disable_clk;
}
/* Define our master */
master->dev.of_node = pdev->dev.of_node;
master->bus_num = pdev->id;
master->num_chipselect = num_cs;
master->mode_bits = SPI_CPHA | SPI_CPOL
/* Define our host */
host->dev.of_node = pdev->dev.of_node;
host->bus_num = pdev->id;
host->num_chipselect = num_cs;
host->mode_bits = SPI_CPHA | SPI_CPOL
| SPI_CS_HIGH | SPI_LSB_FIRST
| SPI_TX_DUAL | SPI_TX_QUAD
| SPI_RX_DUAL | SPI_RX_QUAD;
/* TODO: add driver support for bits_per_word < 8
* we need to "left-align" the bits (unless SPI_LSB_FIRST)
*/
master->bits_per_word_mask = SPI_BPW_MASK(8);
master->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_GPIO_SS;
master->prepare_message = sifive_spi_prepare_message;
master->set_cs = sifive_spi_set_cs;
master->transfer_one = sifive_spi_transfer_one;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_GPIO_SS;
host->prepare_message = sifive_spi_prepare_message;
host->set_cs = sifive_spi_set_cs;
host->transfer_one = sifive_spi_transfer_one;
pdev->dev.dma_mask = NULL;
/* Configure the SPI master hardware */
/* Configure the SPI host hardware */
sifive_spi_init(spi);
/* Register for SPI Interrupt */
@ -397,11 +397,11 @@ static int sifive_spi_probe(struct platform_device *pdev)
}
dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
irq, master->num_chipselect);
irq, host->num_chipselect);
ret = devm_spi_register_master(&pdev->dev, master);
ret = devm_spi_register_controller(&pdev->dev, host);
if (ret < 0) {
dev_err(&pdev->dev, "spi_register_master failed\n");
dev_err(&pdev->dev, "spi_register_host failed\n");
goto disable_clk;
}
@ -409,16 +409,16 @@ static int sifive_spi_probe(struct platform_device *pdev)
disable_clk:
clk_disable_unprepare(spi->clk);
put_master:
spi_master_put(master);
put_host:
spi_controller_put(host);
return ret;
}
static void sifive_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct sifive_spi *spi = spi_master_get_devdata(master);
struct spi_controller *host = platform_get_drvdata(pdev);
struct sifive_spi *spi = spi_controller_get_devdata(host);
/* Disable all the interrupts just in case */
sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
@ -427,11 +427,11 @@ static void sifive_spi_remove(struct platform_device *pdev)
static int sifive_spi_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct sifive_spi *spi = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct sifive_spi *spi = spi_controller_get_devdata(host);
int ret;
ret = spi_master_suspend(master);
ret = spi_controller_suspend(host);
if (ret)
return ret;
@ -445,14 +445,14 @@ static int sifive_spi_suspend(struct device *dev)
static int sifive_spi_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct sifive_spi *spi = spi_master_get_devdata(master);
struct spi_controller *host = dev_get_drvdata(dev);
struct sifive_spi *spi = spi_controller_get_devdata(host);
int ret;
ret = clk_prepare_enable(spi->clk);
if (ret)
return ret;
ret = spi_master_resume(master);
ret = spi_controller_resume(host);
if (ret)
clk_disable_unprepare(spi->clk);

4
drivers/spi/spi-sn-f-ospi.c
View File

@ -501,7 +501,7 @@ out:
static int f_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct f_ospi *ospi = spi_controller_get_devdata(mem->spi->master);
struct f_ospi *ospi = spi_controller_get_devdata(mem->spi->controller);
int err = 0;
switch (op->data.dir) {
@ -606,7 +606,7 @@ static int f_ospi_probe(struct platform_device *pdev)
u32 num_cs = OSPI_NUM_CS;
int ret;
ctlr = spi_alloc_master(dev, sizeof(*ospi));
ctlr = spi_alloc_host(dev, sizeof(*ospi));
if (!ctlr)
return -ENOMEM;

4
include/linux/spi/pxa2xx_spi.h
View File

@ -19,7 +19,7 @@ struct pxa2xx_spi_controller {
u16 num_chipselect;
u8 enable_dma;
u8 dma_burst_size;
bool is_slave;
bool is_target;
/* DMA engine specific config */
bool (*dma_filter)(struct dma_chan *chan, void *param);
@ -31,7 +31,7 @@ struct pxa2xx_spi_controller {
};
/*
* The controller specific data for SPI slave devices
* The controller specific data for SPI target devices
* (resides in spi_board_info.controller_data),
* copied to spi_device.platform_data ... mostly for
* DMA tuning.

4
include/linux/spi/sh_msiof.h
View File

@ -3,8 +3,8 @@
#define __SPI_SH_MSIOF_H__
enum {
MSIOF_SPI_MASTER,
MSIOF_SPI_SLAVE,
MSIOF_SPI_HOST,
MSIOF_SPI_TARGET,
};
struct sh_msiof_spi_info {