ARM: dts: imx: Add i.MXRT1050-EVK support
The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MXRT, which features NXP's implementation of the Arm Cortex-M7 core. The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket, USB 2.0 OTG. This patch aims to support the preliminary booting up features as follows: GPIO LPUART SD/MMC Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> [Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl] Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Giulio Benetti
Shawn Guo
parent
9ac0ae97e3
commit
1c4f01be34
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@ -751,6 +751,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
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dtb-$(CONFIG_SOC_IMX7ULP) += \
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imx7ulp-com.dtb \
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imx7ulp-evk.dtb
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dtb-$(CONFIG_SOC_IMXRT) += \
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imxrt1050-evk.dtb
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dtb-$(CONFIG_SOC_LAN966) += \
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lan966x-pcb8291.dtb
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dtb-$(CONFIG_SOC_LS1021A) += \
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@ -0,0 +1,72 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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/dts-v1/;
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#include "imxrt1050.dtsi"
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#include "imxrt1050-pinfunc.h"
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/ {
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model = "NXP IMXRT1050-evk board";
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compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
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chosen {
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stdout-path = &lpuart1;
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};
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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mmc0 = &usdhc1;
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serial0 = &lpuart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x2000000>;
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};
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};
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
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MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
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MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
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MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
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>;
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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pinctrl-2 = <&pinctrl_usdhc0>;
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pinctrl-3 = <&pinctrl_usdhc0>;
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cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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@ -0,0 +1,160 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#include "armv7-m.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imxrt1050-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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clocks {
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osc: osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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osc3M: osc3M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <3000000>;
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};
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};
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soc {
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lpuart1: serial@40184000 {
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compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x40184000 0x4000>;
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interrupts = <20>;
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clocks = <&clks IMXRT1050_CLK_LPUART1>;
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clock-names = "ipg";
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status = "disabled";
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};
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iomuxc: pinctrl@401f8000 {
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compatible = "fsl,imxrt1050-iomuxc";
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reg = <0x401f8000 0x4000>;
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fsl,mux_mask = <0x7>;
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};
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anatop: anatop@400d8000 {
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compatible = "fsl,imxrt-anatop";
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reg = <0x400d8000 0x4000>;
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};
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clks: clock-controller@400fc000 {
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compatible = "fsl,imxrt1050-ccm";
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reg = <0x400fc000 0x4000>;
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interrupts = <95>, <96>;
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clocks = <&osc>;
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clock-names = "osc";
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#clock-cells = <1>;
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assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
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<&clks IMXRT1050_CLK_PLL1_BYPASS>,
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<&clks IMXRT1050_CLK_PLL2_BYPASS>,
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<&clks IMXRT1050_CLK_PLL3_BYPASS>,
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<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
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<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
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assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
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<&clks IMXRT1050_CLK_PLL1_ARM>,
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<&clks IMXRT1050_CLK_PLL2_SYS>,
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<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
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<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
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<&clks IMXRT1050_CLK_PLL2_SYS>;
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};
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edma1: dma-controller@400e8000 {
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#dma-cells = <2>;
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compatible = "fsl,imx7ulp-edma";
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reg = <0x400e8000 0x4000>,
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<0x400ec000 0x4000>;
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dma-channels = <32>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
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<9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
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clock-names = "dma", "dmamux0";
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clocks = <&clks IMXRT1050_CLK_DMA>,
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<&clks IMXRT1050_CLK_DMA_MUX>;
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};
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usdhc1: mmc@402c0000 {
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compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
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reg = <0x402c0000 0x4000>;
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interrupts = <110>;
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clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
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<&clks IMXRT1050_CLK_OSC>,
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<&clks IMXRT1050_CLK_USDHC1>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,wp-controller;
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no-1-8-v;
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max-frequency = <4000000>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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gpio1: gpio@401b8000 {
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compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
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reg = <0x401b8000 0x4000>;
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interrupts = <80>, <81>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@401bc000 {
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compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
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reg = <0x401bc000 0x4000>;
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interrupts = <82>, <83>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@401c0000 {
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compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
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reg = <0x401c0000 0x4000>;
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interrupts = <84>, <85>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@401c4000 {
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compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
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reg = <0x401c4000 0x4000>;
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interrupts = <86>, <87>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@400c0000 {
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compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
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reg = <0x400c0000 0x4000>;
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interrupts = <88>, <89>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpt: timer@401ec000 {
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compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
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reg = <0x401ec000 0x4000>;
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interrupts = <100>;
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clocks = <&osc3M>;
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clock-names = "per";
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};
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};
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};
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