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ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+
The external memory arbitration configuration is getting reset after memory entering into self-refresh mode, it shall be restored on the exit. Note that MC_EMEM_ARB_CFG register is shadowed and latching happens on the EMC timing update. This fixes 2x GPU performance degradation after resuming from LP1 on Tegra30. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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2 changed files with 30 additions and 0 deletions
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@ -79,15 +79,24 @@
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#define TEGRA_PMC_BASE 0x7000E400
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#define TEGRA_PMC_SIZE SZ_256
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#define TEGRA_MC_BASE 0x7000F000
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#define TEGRA_MC_SIZE SZ_1K
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#define TEGRA_EMC_BASE 0x7000F400
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#define TEGRA_EMC_SIZE SZ_1K
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#define TEGRA114_MC_BASE 0x70019000
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#define TEGRA114_MC_SIZE SZ_4K
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#define TEGRA_EMC0_BASE 0x7001A000
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#define TEGRA_EMC0_SIZE SZ_2K
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#define TEGRA_EMC1_BASE 0x7001A800
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#define TEGRA_EMC1_SIZE SZ_2K
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#define TEGRA124_MC_BASE 0x70019000
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#define TEGRA124_MC_SIZE SZ_4K
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#define TEGRA124_EMC_BASE 0x7001B000
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#define TEGRA124_EMC_SIZE SZ_2K
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@ -44,6 +44,8 @@
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#define EMC_XM2VTTGENPADCTRL 0x310
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#define EMC_XM2VTTGENPADCTRL2 0x314
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#define MC_EMEM_ARB_CFG 0x90
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#define PMC_CTRL 0x0
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#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
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@ -418,6 +420,22 @@ _pll_m_c_x_done:
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movweq r0, #:lower16:TEGRA124_EMC_BASE
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movteq r0, #:upper16:TEGRA124_EMC_BASE
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cmp r10, #TEGRA30
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moveq r2, #0x20
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movweq r4, #:lower16:TEGRA_MC_BASE
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movteq r4, #:upper16:TEGRA_MC_BASE
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cmp r10, #TEGRA114
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moveq r2, #0x34
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movweq r4, #:lower16:TEGRA114_MC_BASE
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movteq r4, #:upper16:TEGRA114_MC_BASE
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cmp r10, #TEGRA124
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moveq r2, #0x20
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movweq r4, #:lower16:TEGRA124_MC_BASE
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movteq r4, #:upper16:TEGRA124_MC_BASE
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ldr r1, [r5, r2] @ restore MC_EMEM_ARB_CFG
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str r1, [r4, #MC_EMEM_ARB_CFG]
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exit_self_refresh:
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ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
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str r1, [r0, #EMC_XM2VTTGENPADCTRL]
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@ -546,6 +564,7 @@ tegra30_sdram_pad_address:
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.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
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.word TEGRA_MC_BASE + MC_EMEM_ARB_CFG @0x20
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tegra30_sdram_pad_address_end:
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tegra114_sdram_pad_address:
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@ -562,6 +581,7 @@ tegra114_sdram_pad_address:
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.word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
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.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
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.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
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.word TEGRA114_MC_BASE + MC_EMEM_ARB_CFG @0x34
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tegra114_sdram_pad_adress_end:
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tegra124_sdram_pad_address:
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@ -573,6 +593,7 @@ tegra124_sdram_pad_address:
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.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
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.word TEGRA124_MC_BASE + MC_EMEM_ARB_CFG @0x20
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tegra124_sdram_pad_address_end:
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tegra30_sdram_pad_size:
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