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drm/i915/psr: Make idle_frames sensible again
This reverts commitdfaf37baa0
Author: Rodrigo Vivi <rodrigo.vivi@intel.com> Date: Mon Dec 7 14:45:20 2015 -0800 drm/i915: Fix idle_frames counter. and commit97173eaf5f
Author: Rodrigo Vivi <rodrigo.vivi@intel.com> Date: Tue Jul 7 16:28:55 2015 -0700 drm/i915: PSR: Increase idle_frames and implements commitd44b4dcbd1
Author: Rodrigo Vivi <rodrigo.vivi@intel.com> Date: Fri Nov 14 08:52:31 2014 -0800 drm/i915: HSW/BDW PSR Set idle_frames = VBT + 1 without the hack to use 2 idle frames when VBT says 1. We keep the + 1 just for safety, although I haven't really figured out why that one exists. It's nonsense. idle_frames = number of frames where the screen is entirely idle before we think about entering PSR. idle_patter = part of link training, and we probably totally butchered link training because we told the hw to entirely skip it. No wonder PSR occasionally just fell over. I suspect the reason we've increased idle frames is that it makes PSR entry slightly less likely, and more likely to happen in a quite system, which probably increased the changes the panel came back up without link training. The proper fix is to implement link training for PSR. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Sonika Jindal <sonika.jindal@intel.com> Cc: Durgadoss R <durgadoss.r@intel.com> Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1463590036-17824-3-git-send-email-daniel.vetter@ffwll.ch
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1 changed files with 7 additions and 7 deletions
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@ -272,14 +272,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t max_sleep_time = 0x1f;
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/*
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* Let's respect VBT in case VBT asks a higher idle_frame value.
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* Let's use 6 as the minimum to cover all known cases including
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* the off-by-one issue that HW has in some cases. Also there are
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* cases where sink should be able to train
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* with the 5 or 6 idle patterns.
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/* Lately it was identified that depending on panel idle frame count
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* calculated at HW can be off by 1. So let's use what came
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* from VBT + 1.
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* There are also other cases where panel demands at least 4
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* but VBT is not being set. To cover these 2 cases lets use
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* at least 5 when VBT isn't set to be on the safest side.
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*/
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uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
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uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1;
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uint32_t val = EDP_PSR_ENABLE;
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val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
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