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ARM: DRA7: clockdomain: Implement timer workaround for errata i874
Errata Title: i874: TIMER5/6/7/8 interrupts not propagated Description: When TIMER5, TIMER6, TIMER7, or TIMER8 clocks are enabled (CM_IPU_TIMER5/6/7/8_CLKCTRL[0:1]MODULEMODE=0x2:ENABLE) and the CD-IPU is in HW_AUTO mode (CM_IPU_CLKSTCTRL[0:1]CLKTRCTRL=0x3:HW_AUTO) the corresponding TIMER will continue counting, but enabled interrupts will not be propagated to the destinations (MPU, DSP, etc) in the SoC until the TIMER registers are accessed from the CPUs (MPU, DSP etc.). This can result in missed timer interrupts. Workaround: In order for TIMER5/6/7/8 interrupts to be propagated and serviced correctly the CD_IPU domain should be set to SW_WKUP mode (CM_IPU_CLKSTCTRL[0:1]CLKTRCTRL=0x2:SW_WKUP). The above workaround is achieved by switching the IPU clockdomain flags from HWSUP_SWSUP to SWSUP only. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -461,7 +461,7 @@ static struct clockdomain ipu_7xx_clkdm = {
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.cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
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.clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
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.dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mpu1_7xx_clkdm = {
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