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arm64: dts: rockchip: Add BT support on px30-engicam

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Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have
an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected
on the UART bus.

UART bus on the design routed via USB to UART CP20x bridge. This
bridge powered from 3V3 regualtor gpio.

This patch adds BT enablement nodes for these respective boards.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20201109181017.206834-7-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Suniel Mahesh 2020-11-09 23:40:14 +05:30 committed by Heiko Stuebner
parent 93a4e7d124
commit 1cc1e851d1
3 changed files with 32 additions and 0 deletions
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12
arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
View file

@ -24,6 +24,18 @@ sdio_pwrseq: sdio-pwrseq {
pinctrl-0 = <&wifi_enable_h>;
};
vcc3v3_btreg: vcc3v3-btreg {
compatible = "regulator-gpio";
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&bt_enable_h>;
regulator-name = "btreg-gpio-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
states = <3300000 0x0>;
};
vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_rf_aux_mod";

10
arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
View file

@ -8,6 +8,12 @@
#include "px30-engicam-common.dtsi"
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
@ -18,3 +24,7 @@ wifi_enable_h: wifi-enable-h {
&sdio_pwrseq {
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
&vcc3v3_btreg {
enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
};

10
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
View file

@ -21,6 +21,12 @@ chosen {
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
@ -31,3 +37,7 @@ wifi_enable_h: wifi-enable-h {
&sdio_pwrseq {
reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
};
&vcc3v3_btreg {
enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
};