brcmfmac: support chipsets with different core enumeration space
Historically the broadcom wifi chipsets always had enumeration space containing all core information at same place. However, for new chipsets the ASIC developers moved away from that given fact. So we have to accommodate that it can differ per chipset. Reviewed-by: Hante Meuleman <hante.meuleman@broadcom.com> Reviewed-by: Pieter-Paul Giesberts <pieter-paul.giesberts@broadcom.com> Reviewed-by: Franky Lin <franky.lin@broadcom.com> Signed-off-by: Arend van Spriel <arend.vanspriel@broadcom.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1627505434-9544-5-git-send-email-arend.vanspriel@broadcom.com
This commit is contained in:
Arend van Spriel
Kalle Valo
parent
a7dd0ac945
commit
1ce050c159
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@ -128,7 +128,8 @@ int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev)
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if (sdiodev->bus_if->chip == BRCM_CC_43362_CHIP_ID) {
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/* assign GPIO to SDIO core */
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addr = CORE_CC_REG(SI_ENUM_BASE, gpiocontrol);
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addr = brcmf_chip_enum_base(sdiodev->func1->device);
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addr = CORE_CC_REG(addr, gpiocontrol);
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gpiocontrol = brcmf_sdiod_readl(sdiodev, addr, &ret);
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gpiocontrol |= 0x2;
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brcmf_sdiod_writel(sdiodev, addr, gpiocontrol, &ret);
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@ -896,7 +896,8 @@ int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
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u32 base, wrap;
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int err;
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eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
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eromaddr = ci->ops->read32(ci->ctx,
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CORE_CC_REG(ci->pub.enum_base, eromptr));
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while (desc_type != DMP_DESC_EOT) {
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val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
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@ -944,6 +945,11 @@ int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
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return 0;
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}
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u32 brcmf_chip_enum_base(u16 devid)
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{
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return SI_ENUM_BASE_DEFAULT;
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}
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static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
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{
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struct brcmf_core *core;
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@ -956,7 +962,8 @@ static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
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* For different chiptypes or old sdio hosts w/o chipcommon,
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* other ways of recognition should be added here.
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*/
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regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
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regdata = ci->ops->read32(ci->ctx,
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CORE_CC_REG(ci->pub.enum_base, chipid));
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ci->pub.chip = regdata & CID_ID_MASK;
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ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
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socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
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@ -976,7 +983,7 @@ static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
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ci->resetcore = brcmf_chip_sb_resetcore;
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core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
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SI_ENUM_BASE, 0);
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SI_ENUM_BASE_DEFAULT, 0);
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brcmf_chip_sb_corerev(ci, core);
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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BCM4329_CORE_BUS_BASE, 0);
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@ -1090,7 +1097,7 @@ static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
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return ret;
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}
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struct brcmf_chip *brcmf_chip_attach(void *ctx,
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struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
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const struct brcmf_buscore_ops *ops)
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{
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struct brcmf_chip_priv *chip;
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@ -1115,6 +1122,7 @@ struct brcmf_chip *brcmf_chip_attach(void *ctx,
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chip->num_cores = 0;
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chip->ops = ops;
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chip->ctx = ctx;
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chip->pub.enum_base = brcmf_chip_enum_base(devid);
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err = ops->prepare(ctx);
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if (err < 0)
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@ -15,6 +15,7 @@
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*
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* @chip: chip identifier.
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* @chiprev: chip revision.
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* @enum_base: base address of core enumeration space.
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* @cc_caps: chipcommon core capabilities.
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* @cc_caps_ext: chipcommon core extended capabilities.
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* @pmucaps: PMU capabilities.
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@ -27,6 +28,7 @@
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struct brcmf_chip {
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u32 chip;
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u32 chiprev;
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u32 enum_base;
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u32 cc_caps;
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u32 cc_caps_ext;
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u32 pmucaps;
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@ -70,7 +72,7 @@ struct brcmf_buscore_ops {
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};
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int brcmf_chip_get_raminfo(struct brcmf_chip *pub);
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struct brcmf_chip *brcmf_chip_attach(void *ctx,
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struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
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const struct brcmf_buscore_ops *ops);
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void brcmf_chip_detach(struct brcmf_chip *chip);
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struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid);
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@ -85,5 +87,6 @@ void brcmf_chip_set_passive(struct brcmf_chip *ci);
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bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec);
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bool brcmf_chip_sr_capable(struct brcmf_chip *pub);
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char *brcmf_chip_name(u32 chipid, u32 chiprev, char *buf, uint len);
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u32 brcmf_chip_enum_base(u16 devid);
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#endif /* BRCMF_AXIDMP_H */
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@ -1886,7 +1886,8 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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devinfo->pdev = pdev;
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pcie_bus_dev = NULL;
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devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
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devinfo->ci = brcmf_chip_attach(devinfo, pdev->device,
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&brcmf_pcie_buscore_ops);
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if (IS_ERR(devinfo->ci)) {
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ret = PTR_ERR(devinfo->ci);
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devinfo->ci = NULL;
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@ -3910,7 +3910,7 @@ static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
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* It can be identified as 4339 by looking at the chip revision. It
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* is corrected here so the chip.c module has the right info.
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*/
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if (addr == CORE_CC_REG(SI_ENUM_BASE, chipid) &&
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if (addr == CORE_CC_REG(SI_ENUM_BASE_DEFAULT, chipid) &&
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(sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 ||
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sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) {
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rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
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@ -3946,12 +3946,15 @@ brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
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int reg_addr;
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u32 reg_val;
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u32 drivestrength;
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u32 enum_base;
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sdiodev = bus->sdiodev;
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sdio_claim_host(sdiodev->func1);
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pr_debug("F1 signature read @0x18000000=0x%4x\n",
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brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL));
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enum_base = brcmf_chip_enum_base(sdiodev->func1->device);
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pr_debug("F1 signature read @0x%08x=0x%4x\n", enum_base,
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brcmf_sdiod_readl(sdiodev, enum_base, NULL));
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/*
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* Force PLL off until brcmf_chip_attach()
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@ -3970,7 +3973,8 @@ brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
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goto fail;
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}
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bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
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bus->ci = brcmf_chip_attach(sdiodev, sdiodev->func1->device,
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&brcmf_sdio_buscore_ops);
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if (IS_ERR(bus->ci)) {
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brcmf_err("brcmf_chip_attach failed!\n");
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bus->ci = NULL;
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@ -6,7 +6,7 @@
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#ifndef _BRCM_SOC_H
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#define _BRCM_SOC_H
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#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
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#define SI_ENUM_BASE_DEFAULT 0x18000000
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/* Common core control flags */
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#define SICF_BIST_EN 0x8000
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