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PCI: aardvark: Update comment about disabling link training
According to PCI Express Base Specifications (rev 4.0, 6.6.1 "Conventional reset"), after fundamental reset a 100ms delay is needed prior to enabling link training. Update comment in code to reflect this requirement. Link: https://lore.kernel.org/r/20201202184659.3795-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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@ -259,7 +259,14 @@ static void advk_pcie_issue_perst(struct advk_pcie *pcie)
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if (!pcie->reset_gpio)
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return;
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/* PERST does not work for some cards when link training is enabled */
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/*
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* As required by PCI Express spec (PCI Express Base Specification, REV.
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* 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset) a delay
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* for at least 100ms after de-asserting PERST# signal is needed before
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* link training is enabled. So ensure that link training is disabled
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* prior de-asserting PERST# signal to fulfill that PCI Express spec
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* requirement.
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*/
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reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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reg &= ~LINK_TRAINING_EN;
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advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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