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drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
Driver had discrepancy in how cdclk squash and crawl support were checked. Like crawl, add squash as a 1 bit feature flag to the display section of DG2. Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221025223042.138810-2-anusha.srivatsa@intel.com
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c74b644f26
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4 changed files with 8 additions and 10 deletions
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@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
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skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
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}
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static bool has_cdclk_squash(struct drm_i915_private *i915)
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{
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return IS_DG2(i915);
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}
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struct intel_cdclk_vals {
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u32 cdclk;
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u16 refclk;
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@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
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return;
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}
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if (has_cdclk_squash(dev_priv))
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if (HAS_CDCLK_SQUASH(dev_priv))
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squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
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if (squash_ctl & CDCLK_SQUASH_ENABLE) {
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@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
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else
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clock = cdclk;
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if (has_cdclk_squash(dev_priv)) {
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if (HAS_CDCLK_SQUASH(dev_priv)) {
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u32 squash_ctl = 0;
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if (waveform)
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@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
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expected = skl_cdclk_decimal(cdclk);
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/* Figure out what CD2X divider we should be using for this cdclk */
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if (has_cdclk_squash(dev_priv))
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if (HAS_CDCLK_SQUASH(dev_priv))
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clock = dev_priv->display.cdclk.hw.vco / 2;
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else
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clock = dev_priv->display.cdclk.hw.cdclk;
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@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
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* the moment all platforms with squasher use a fixed cd2x
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* divider.
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*/
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if (!has_cdclk_squash(dev_priv))
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if (!HAS_CDCLK_SQUASH(dev_priv))
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return false;
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return a->cdclk != b->cdclk &&
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@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
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* the moment all platforms with squasher use a fixed cd2x
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* divider.
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*/
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if (has_cdclk_squash(dev_priv))
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if (HAS_CDCLK_SQUASH(dev_priv))
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return false;
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return a->cdclk != b->cdclk &&
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@ -865,6 +865,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
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#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
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#define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
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#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
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#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
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#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
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@ -1063,6 +1063,7 @@ static const struct intel_device_info xehpsdv_info = {
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.has_heci_pxp = 1, \
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.needs_compact_pt = 1, \
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.has_media_ratio_mode = 1, \
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.display.has_cdclk_squash = 1, \
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.__runtime.platform_engine_mask = \
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BIT(RCS0) | BIT(BCS0) | \
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BIT(VECS0) | BIT(VECS1) | \
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@ -179,6 +179,7 @@ enum intel_ppgtt_type {
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/* Keep in alphabetical order */ \
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func(cursor_needs_physical); \
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func(has_cdclk_crawl); \
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func(has_cdclk_squash); \
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func(has_ddi); \
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func(has_dp_mst); \
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func(has_dsb); \
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