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coresight: etm4x: Cleanup secure exception level masks 

We rely on the ETM architecture version to decide whether
Secure EL2 is available on the CPU for excluding the level
for address comparators and viewinst main control register.
We must instead use the TRCDIDR3.EXLEVEL_S field to detect
the supported levels.

Link: https://lore.kernel.org/r/20210110224850.1880240-16-suzuki.poulose@arm.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-18-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Suzuki K Poulose 2021-02-01 11:13:37 -07:00 committed by Greg Kroah-Hartman
parent 33d5573a15
commit 1d3eead7e9
2 changed files with 7 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/hwtracing/coresight/coresight-etm4x-core.c
View File

@ -840,7 +840,6 @@ static void etm4_init_arch_data(void *info)
* TRCARCHMAJ, bits[11:8] architecture major versin number
*/
drvdata->arch = BMVAL(etmidr1, 4, 11);
drvdata->config.arch = drvdata->arch;
/* maximum size of resources */
etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
@ -856,6 +855,7 @@ static void etm4_init_arch_data(void *info)
drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
drvdata->config.s_ex_level = drvdata->s_ex_level;
/* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
@ -1027,16 +1027,9 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
static u64 etm4_get_access_type(struct etmv4_config *config)
{
u64 access_type = etm4_get_ns_access_type(config);
u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
/*
* EXLEVEL_S, bits[11:8], don't trace anything happening
* in secure state.
*/
access_type |= (ETM_EXLEVEL_S_APP |
ETM_EXLEVEL_S_OS |
s_hyp |
ETM_EXLEVEL_S_MON);
/* All supported secure ELs are excluded */
access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT;
return access_type;
}

6
drivers/hwtracing/coresight/coresight-etm4x.h
View File

@ -557,6 +557,8 @@
/* PowerDown Control Register bits */
#define TRCPDCR_PU BIT(3)
#define TRCACATR_EXLEVEL_SHIFT 8
/* secure state access levels - TRCACATRn */
#define ETM_EXLEVEL_S_APP BIT(8)
#define ETM_EXLEVEL_S_OS BIT(9)
@ -631,7 +633,7 @@ enum etm_impdef_type {
* @vmid_mask0: VM ID comparator mask for comparator 0-3.
* @vmid_mask1: VM ID comparator mask for comparator 4-7.
* @ext_inp: External input selection.
* @arch: ETM architecture version (for arch dependent config).
* @s_ex_level: Secure ELs where tracing is supported.
*/
struct etmv4_config {
u32 mode;
@ -675,7 +677,7 @@ struct etmv4_config {
u32 vmid_mask0;
u32 vmid_mask1;
u32 ext_inp;
u8 arch;
u8 s_ex_level;
};
/**