mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-30 08:02:30 +00:00
tty: serial: fsl_lpuart: Use appropriate lpuart32_* I/O funcs
When dealing with 32-bit variant of LPUART IP block appropriate I/O
helpers have to be used to properly deal with endianness
differences. Change all of the offending code to do that.
Fixes: a5fa2660d7
("tty/serial/fsl_lpuart: Add CONSOLE_POLL support
for lpuart32.")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.com>
Cc: linux-imx@nxp.com
Cc: linux-serial@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/20190729195226.8862-14-andrew.smirnov@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
76e3f2ac4a
commit
1da17d7cf8
1 changed files with 14 additions and 14 deletions
|
@ -617,26 +617,26 @@ static int lpuart32_poll_init(struct uart_port *port)
|
|||
spin_lock_irqsave(&sport->port.lock, flags);
|
||||
|
||||
/* Disable Rx & Tx */
|
||||
writel(0, sport->port.membase + UARTCTRL);
|
||||
lpuart32_write(&sport->port, UARTCTRL, 0);
|
||||
|
||||
temp = readl(sport->port.membase + UARTFIFO);
|
||||
temp = lpuart32_read(&sport->port, UARTFIFO);
|
||||
|
||||
/* Enable Rx and Tx FIFO */
|
||||
writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE,
|
||||
sport->port.membase + UARTFIFO);
|
||||
lpuart32_write(&sport->port, UARTFIFO,
|
||||
temp | UARTFIFO_RXFE | UARTFIFO_TXFE);
|
||||
|
||||
/* flush Tx and Rx FIFO */
|
||||
writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH,
|
||||
sport->port.membase + UARTFIFO);
|
||||
lpuart32_write(&sport->port, UARTFIFO,
|
||||
UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH);
|
||||
|
||||
/* explicitly clear RDRF */
|
||||
if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) {
|
||||
readl(sport->port.membase + UARTDATA);
|
||||
writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO);
|
||||
if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
|
||||
lpuart32_read(&sport->port, UARTDATA);
|
||||
lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF);
|
||||
}
|
||||
|
||||
/* Enable Rx and Tx */
|
||||
writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL);
|
||||
lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE);
|
||||
spin_unlock_irqrestore(&sport->port.lock, flags);
|
||||
|
||||
return 0;
|
||||
|
@ -644,18 +644,18 @@ static int lpuart32_poll_init(struct uart_port *port)
|
|||
|
||||
static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
|
||||
{
|
||||
while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE))
|
||||
while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
|
||||
barrier();
|
||||
|
||||
writel(c, port->membase + UARTDATA);
|
||||
lpuart32_write(port, UARTDATA, c);
|
||||
}
|
||||
|
||||
static int lpuart32_poll_get_char(struct uart_port *port)
|
||||
{
|
||||
if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF))
|
||||
if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF))
|
||||
return NO_POLL_CHAR;
|
||||
|
||||
return readl(port->membase + UARTDATA);
|
||||
return lpuart32_read(port, UARTDATA);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
Loading…
Reference in a new issue