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arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings
[ Upstream commit242d8ee911
] BIT3 and BIT0 are reserved bits, should not touch. Fixes:88f7f6bcca
("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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parent
021eeb2e20
commit
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1 changed files with 8 additions and 8 deletions
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@ -136,21 +136,21 @@ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
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>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
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MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
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MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
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MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
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>;
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};
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@ -175,7 +175,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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};
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@ -187,7 +187,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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};
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@ -199,7 +199,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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};
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};
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