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ARM: DRA7: hwmod: Fixup SATA hwmod
Get rid of optional clock as that is now managed by the AHCI platform driver. Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..) is passed as the second memory resource in the device tree. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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0cd8d4052a
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1ea0999e08
1 changed files with 1 additions and 5 deletions
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@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
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};
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/* sata */
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static struct omap_hwmod_opt_clk sata_opt_clks[] = {
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{ .role = "ref_clk", .clk = "sata_ref_clk" },
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};
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static struct omap_hwmod dra7xx_sata_hwmod = {
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.name = "sata",
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@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
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.clkdm_name = "l3init_clkdm",
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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.main_clk = "func_48m_fclk",
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.mpu_rt_idx = 1,
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
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@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = sata_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
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};
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/*
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