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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-19 09:04:57 +00:00
iwlwifi: remove flags argument for nic_access
Since we no longer save interrupts, we no longer need the flags argument here, remove it throughout. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20210210142629.8de8fe6f9fff.If040b056d0e8c771c65ac5c29230f939354a142b@changeid Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Johannes Berg
Luca Coelho
parent
c52b251d1c
commit
1ed08f6fb5
8 changed files with 66 additions and 101 deletions
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@ -406,7 +406,6 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
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u32 i;
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u32 ptr; /* SRAM byte address of log data */
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u32 ev, time, data; /* event log data */
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unsigned long reg_flags;
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if (mode == 0)
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ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
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@ -414,7 +413,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
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ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
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/* Make sure device is powered up for SRAM reads */
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if (!iwl_trans_grab_nic_access(priv->trans, ®_flags))
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if (!iwl_trans_grab_nic_access(priv->trans))
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return;
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/* Set starting address; reads will auto-increment */
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@ -446,7 +445,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
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}
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}
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/* Allow device to power down */
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iwl_trans_release_nic_access(priv->trans, ®_flags);
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iwl_trans_release_nic_access(priv->trans);
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}
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static void iwl_continuous_event_trace(struct iwl_priv *priv)
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@ -1694,7 +1693,6 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
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u32 ptr; /* SRAM byte address of log data */
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u32 ev, time, data; /* event log data */
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unsigned long reg_flags;
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struct iwl_trans *trans = priv->trans;
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@ -1718,7 +1716,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
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/* Make sure device is powered up for SRAM reads */
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if (!iwl_trans_grab_nic_access(trans, ®_flags))
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if (!iwl_trans_grab_nic_access(trans))
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return pos;
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/* Set starting address; reads will auto-increment */
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@ -1757,7 +1755,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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}
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/* Allow device to power down */
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iwl_trans_release_nic_access(trans, ®_flags);
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iwl_trans_release_nic_access(trans);
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return pos;
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}
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@ -2,7 +2,7 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
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* Copyright (C) 2018 Intel Corporation
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* Copyright (C) 2018, 2020 Intel Corporation
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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@ -155,7 +155,6 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list *t)
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struct iwl_priv *priv = from_timer(priv, t,
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thermal_throttle.ct_kill_exit_tm);
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struct iwl_tt_mgmt *tt = &priv->thermal_throttle;
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unsigned long flags;
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if (test_bit(STATUS_EXIT_PENDING, &priv->status))
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return;
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@ -171,8 +170,8 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list *t)
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priv->thermal_throttle.ct_kill_toggle = true;
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}
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iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
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if (iwl_trans_grab_nic_access(priv->trans, &flags))
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iwl_trans_release_nic_access(priv->trans, &flags);
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if (iwl_trans_grab_nic_access(priv->trans))
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iwl_trans_release_nic_access(priv->trans);
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/* Reschedule the ct_kill timer to occur in
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* CT_KILL_EXIT_DURATION seconds to ensure we get a
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@ -33,12 +33,11 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
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struct iwl_fw_error_dump_data **dump_data)
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{
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u8 *pos = (void *)(*dump_data)->data;
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unsigned long flags;
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int i;
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IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
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if (!iwl_trans_grab_nic_access(fwrt->trans))
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return;
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(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
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@ -56,7 +55,7 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
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*dump_data = iwl_fw_error_next_data(*dump_data);
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iwl_trans_release_nic_access(fwrt->trans, &flags);
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iwl_trans_release_nic_access(fwrt->trans);
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}
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static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
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@ -172,11 +171,10 @@ static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
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struct iwl_fw_error_dump_data **dump_data)
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{
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struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
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unsigned long flags;
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IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
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if (!iwl_trans_grab_nic_access(fwrt->trans))
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return;
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if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
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@ -194,7 +192,7 @@ static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
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LMAC2_PRPH_OFFSET, 2);
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}
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iwl_trans_release_nic_access(fwrt->trans, &flags);
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iwl_trans_release_nic_access(fwrt->trans);
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}
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static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
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@ -204,12 +202,11 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
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struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
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u32 *fifo_data;
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u32 fifo_len;
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unsigned long flags;
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int i, j;
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IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
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if (!iwl_trans_grab_nic_access(fwrt->trans))
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return;
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if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
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@ -299,7 +296,7 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
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}
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}
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iwl_trans_release_nic_access(fwrt->trans, &flags);
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iwl_trans_release_nic_access(fwrt->trans);
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}
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#define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
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@ -527,7 +524,6 @@ static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
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struct iwl_trans *trans = fwrt->trans;
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struct iwl_fw_error_dump_data **data =
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(struct iwl_fw_error_dump_data **)ptr;
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unsigned long flags;
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u32 i;
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if (!data)
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@ -535,7 +531,7 @@ static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
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IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
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if (!iwl_trans_grab_nic_access(trans, &flags))
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if (!iwl_trans_grab_nic_access(trans))
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return;
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for (i = 0; i < range_len; i++) {
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@ -558,7 +554,7 @@ static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
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*data = iwl_fw_error_next_data(*data);
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}
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iwl_trans_release_nic_access(trans, &flags);
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iwl_trans_release_nic_access(trans);
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}
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/*
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@ -1048,7 +1044,6 @@ iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
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u32 addr = le32_to_cpu(reg->addrs[idx]);
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u32 dphy_state;
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u32 dphy_addr;
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unsigned long flags;
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int i;
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range->internal_base_addr = cpu_to_le32(addr);
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@ -1060,7 +1055,7 @@ iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
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indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset);
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indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset);
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
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if (!iwl_trans_grab_nic_access(fwrt->trans))
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return -EBUSY;
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dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW :
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@ -1082,7 +1077,7 @@ iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
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*val++ = cpu_to_le32(prph_val);
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}
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iwl_trans_release_nic_access(fwrt->trans, &flags);
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iwl_trans_release_nic_access(fwrt->trans);
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return sizeof(*range) + le32_to_cpu(range->range_data_size);
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}
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@ -1297,13 +1292,12 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
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u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
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u32 registers_size = registers_num * sizeof(*reg_dump);
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__le32 *data;
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unsigned long flags;
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int i;
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if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
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return -EIO;
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
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if (!iwl_trans_grab_nic_access(fwrt->trans))
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return -EBUSY;
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range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
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@ -1345,7 +1339,7 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
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*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
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out:
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iwl_trans_release_nic_access(fwrt->trans, &flags);
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iwl_trans_release_nic_access(fwrt->trans);
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return sizeof(*range) + le32_to_cpu(range->range_data_size);
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}
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@ -1429,14 +1423,13 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
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u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
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u32 registers_size = registers_num * sizeof(*reg_dump);
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__le32 *data;
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unsigned long flags;
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int i;
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iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
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if (!rxf_data.size)
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return -EIO;
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
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if (!iwl_trans_grab_nic_access(fwrt->trans))
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return -EBUSY;
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range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
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@ -1479,7 +1472,7 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
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*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
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out:
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iwl_trans_release_nic_access(fwrt->trans, &flags);
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iwl_trans_release_nic_access(fwrt->trans);
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return sizeof(*range) + le32_to_cpu(range->range_data_size);
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}
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@ -1596,9 +1589,8 @@ iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
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{
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struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
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u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
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unsigned long flags;
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) {
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if (!iwl_trans_grab_nic_access(fwrt->trans)) {
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IWL_ERR(fwrt, "Failed to get monitor header\n");
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return NULL;
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}
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@ -1615,7 +1607,7 @@ iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
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data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
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&addrs->cur_frag);
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iwl_trans_release_nic_access(fwrt->trans, &flags);
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iwl_trans_release_nic_access(fwrt->trans);
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data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
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@ -2762,7 +2754,6 @@ IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
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void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
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{
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struct iwl_trans *trans = fwrt->trans;
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unsigned long flags;
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int i;
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struct {
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u32 addr;
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@ -2782,7 +2773,7 @@ void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
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FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR),
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};
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if (!iwl_trans_grab_nic_access(trans, &flags))
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if (!iwl_trans_grab_nic_access(trans))
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return;
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IWL_ERR(fwrt, "Fseq Registers:\n");
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@ -2792,7 +2783,7 @@ void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
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iwl_read_prph_no_grab(trans, fseq_regs[i].addr),
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fseq_regs[i].str);
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iwl_trans_release_nic_access(trans, &flags);
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iwl_trans_release_nic_access(trans);
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}
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IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs);
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@ -66,10 +66,10 @@ IWL_EXPORT_SYMBOL(iwl_poll_bit);
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u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
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{
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u32 value = 0x5a5a5a5a;
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unsigned long flags;
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if (iwl_trans_grab_nic_access(trans, &flags)) {
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if (iwl_trans_grab_nic_access(trans)) {
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value = iwl_read32(trans, reg);
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iwl_trans_release_nic_access(trans, &flags);
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iwl_trans_release_nic_access(trans);
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}
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return value;
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@ -78,22 +78,18 @@ IWL_EXPORT_SYMBOL(iwl_read_direct32);
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void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
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{
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unsigned long flags;
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if (iwl_trans_grab_nic_access(trans, &flags)) {
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if (iwl_trans_grab_nic_access(trans)) {
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iwl_write32(trans, reg, value);
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iwl_trans_release_nic_access(trans, &flags);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_write_direct32);
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void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
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{
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unsigned long flags;
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if (iwl_trans_grab_nic_access(trans, &flags)) {
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if (iwl_trans_grab_nic_access(trans)) {
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iwl_write64(trans, reg, value);
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iwl_trans_release_nic_access(trans, &flags);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_write_direct64);
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@ -139,12 +135,11 @@ IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab);
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u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
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{
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unsigned long flags;
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u32 val = 0x5a5a5a5a;
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if (iwl_trans_grab_nic_access(trans, &flags)) {
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if (iwl_trans_grab_nic_access(trans)) {
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val = iwl_read_prph_no_grab(trans, ofs);
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iwl_trans_release_nic_access(trans, &flags);
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iwl_trans_release_nic_access(trans);
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}
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return val;
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}
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@ -152,12 +147,10 @@ IWL_EXPORT_SYMBOL(iwl_read_prph);
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void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms)
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{
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unsigned long flags;
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if (iwl_trans_grab_nic_access(trans, &flags)) {
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if (iwl_trans_grab_nic_access(trans)) {
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mdelay(delay_ms);
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iwl_write_prph_no_grab(trans, ofs, val);
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iwl_trans_release_nic_access(trans, &flags);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_write_prph_delay);
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@ -179,13 +172,11 @@ int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
|
|||
|
||||
void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write_prph_no_grab(trans, ofs,
|
||||
iwl_read_prph_no_grab(trans, ofs) |
|
||||
mask);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
|
||||
|
|
@ -193,26 +184,23 @@ IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
|
|||
void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
|
||||
u32 bits, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write_prph_no_grab(trans, ofs,
|
||||
(iwl_read_prph_no_grab(trans, ofs) &
|
||||
mask) | bits);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
|
||||
|
||||
void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
val = iwl_read_prph_no_grab(trans, ofs);
|
||||
iwl_write_prph_no_grab(trans, ofs, (val & ~mask));
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
}
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
|
||||
|
|
|
|||
|
|
@ -579,9 +579,8 @@ struct iwl_trans_ops {
|
|||
const struct iwl_trans_config *trans_cfg);
|
||||
void (*set_pmi)(struct iwl_trans *trans, bool state);
|
||||
void (*sw_reset)(struct iwl_trans *trans);
|
||||
bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags);
|
||||
void (*release_nic_access)(struct iwl_trans *trans,
|
||||
unsigned long *flags);
|
||||
bool (*grab_nic_access)(struct iwl_trans *trans);
|
||||
void (*release_nic_access)(struct iwl_trans *trans);
|
||||
void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
|
||||
u32 value);
|
||||
|
||||
|
|
@ -1368,14 +1367,14 @@ iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
|
|||
trans->ops->set_bits_mask(trans, reg, mask, value);
|
||||
}
|
||||
|
||||
#define iwl_trans_grab_nic_access(trans, flags) \
|
||||
#define iwl_trans_grab_nic_access(trans) \
|
||||
__cond_lock(nic_access, \
|
||||
likely((trans)->ops->grab_nic_access(trans, flags)))
|
||||
likely((trans)->ops->grab_nic_access(trans)))
|
||||
|
||||
static inline void __releases(nic_access)
|
||||
iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
|
||||
iwl_trans_release_nic_access(struct iwl_trans *trans)
|
||||
{
|
||||
trans->ops->release_nic_access(trans, flags);
|
||||
trans->ops->release_nic_access(trans);
|
||||
__release(nic_access);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -847,7 +847,6 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
|
|||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 rb_size;
|
||||
unsigned long flags;
|
||||
const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
|
||||
|
||||
switch (trans_pcie->rx_buf_size) {
|
||||
|
|
@ -865,7 +864,7 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
|
|||
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
|
||||
}
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return;
|
||||
|
||||
/* Stop Rx DMA */
|
||||
|
|
@ -902,7 +901,7 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
|
|||
(RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
|
||||
(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
/* Set interrupt coalescing timer to default (2048 usecs) */
|
||||
iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
|
||||
|
|
@ -916,7 +915,6 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
|
|||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 rb_size, enabled = 0;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
switch (trans_pcie->rx_buf_size) {
|
||||
|
|
@ -937,7 +935,7 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
|
|||
rb_size = RFH_RXF_DMA_RB_SIZE_4K;
|
||||
}
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return;
|
||||
|
||||
/* Stop Rx DMA */
|
||||
|
|
@ -995,7 +993,7 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
|
|||
/* Enable the relevant rx queues */
|
||||
iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
/* Set interrupt coalescing timer to default (2048 usecs) */
|
||||
iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
|
||||
|
|
|
|||
|
|
@ -640,17 +640,16 @@ static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
|
|||
u32 byte_cnt)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
trans_pcie->ucode_write_complete = false;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return -EIO;
|
||||
|
||||
iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
|
||||
byte_cnt);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
|
||||
trans_pcie->ucode_write_complete, 5 * HZ);
|
||||
|
|
@ -1974,8 +1973,7 @@ static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
|
|||
module_put(THIS_MODULE);
|
||||
}
|
||||
|
||||
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
|
||||
unsigned long *flags)
|
||||
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
|
||||
{
|
||||
int ret;
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
|
@ -2078,8 +2076,7 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
|
|||
return true;
|
||||
}
|
||||
|
||||
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
|
||||
unsigned long *flags)
|
||||
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
|
|
@ -2109,7 +2106,6 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
|
|||
static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
||||
void *buf, int dwords)
|
||||
{
|
||||
unsigned long flags;
|
||||
int offs = 0;
|
||||
u32 *vals = buf;
|
||||
|
||||
|
|
@ -2118,7 +2114,7 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
|||
unsigned long end = jiffies + HZ / 2;
|
||||
bool resched = false;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write32(trans, HBUS_TARG_MEM_RADDR,
|
||||
addr + 4 * offs);
|
||||
|
||||
|
|
@ -2132,7 +2128,7 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
|||
break;
|
||||
}
|
||||
}
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
if (resched)
|
||||
cond_resched();
|
||||
|
|
@ -2147,16 +2143,15 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
|
|||
static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
|
||||
const void *buf, int dwords)
|
||||
{
|
||||
unsigned long flags;
|
||||
int offs, ret = 0;
|
||||
const u32 *vals = buf;
|
||||
|
||||
if (iwl_trans_grab_nic_access(trans, &flags)) {
|
||||
if (iwl_trans_grab_nic_access(trans)) {
|
||||
iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
|
||||
for (offs = 0; offs < dwords; offs++)
|
||||
iwl_write32(trans, HBUS_TARG_MEM_WDAT,
|
||||
vals ? vals[offs] : 0);
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
} else {
|
||||
ret = -EBUSY;
|
||||
}
|
||||
|
|
@ -2952,11 +2947,10 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
|
|||
struct iwl_fw_error_dump_data **data)
|
||||
{
|
||||
u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
|
||||
unsigned long flags;
|
||||
__le32 *val;
|
||||
int i;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return 0;
|
||||
|
||||
(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
|
||||
|
|
@ -2974,7 +2968,7 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
|
|||
*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
|
||||
i));
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
*data = iwl_fw_error_next_data(*data);
|
||||
|
||||
|
|
@ -2988,10 +2982,9 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
|
|||
{
|
||||
u32 buf_size_in_dwords = (monitor_len >> 2);
|
||||
u32 *buffer = (u32 *)fw_mon_data->data;
|
||||
unsigned long flags;
|
||||
u32 i;
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
return 0;
|
||||
|
||||
iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
|
||||
|
|
@ -3000,7 +2993,7 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
|
|||
MON_DMARB_RD_DATA_ADDR);
|
||||
iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
return monitor_len;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -392,13 +392,12 @@ void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
|
|||
static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
int ch, ret;
|
||||
u32 mask = 0;
|
||||
|
||||
spin_lock_bh(&trans_pcie->irq_lock);
|
||||
|
||||
if (!iwl_trans_grab_nic_access(trans, &flags))
|
||||
if (!iwl_trans_grab_nic_access(trans))
|
||||
goto out;
|
||||
|
||||
/* Stop each Tx DMA channel */
|
||||
|
|
@ -414,7 +413,7 @@ static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
|
|||
"Failing on timeout while stopping DMA channel %d [0x%08x]\n",
|
||||
ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
|
||||
|
||||
iwl_trans_release_nic_access(trans, &flags);
|
||||
iwl_trans_release_nic_access(trans);
|
||||
|
||||
out:
|
||||
spin_unlock_bh(&trans_pcie->irq_lock);
|
||||
|
|
|
|||
Loading…
Reference in a new issue