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powerpc/powernv: Add TCE SW invalidation support
This is used for newer IO Hubs such as p7IOC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
48c2ce97fa
commit
1f1616e864
3 changed files with 78 additions and 16 deletions
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@ -31,7 +31,9 @@
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*/
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*/
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#define TCE_VB 0
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#define TCE_VB 0
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#define TCE_PCI 1
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#define TCE_PCI 1
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#define TCE_PCI_SW_INVAL 2
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#define TCE_PCI_SWINV_CREATE 2
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#define TCE_PCI_SWINV_FREE 4
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#define TCE_PCI_SWINV_PAIR 8
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/* TCE page size is 4096 bytes (1 << 12) */
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/* TCE page size is 4096 bytes (1 << 12) */
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@ -257,12 +257,54 @@ struct pci_ops pnv_pci_ops = {
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.write = pnv_pci_write_config,
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.write = pnv_pci_write_config,
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};
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};
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static void pnv_tce_invalidate(struct iommu_table *tbl,
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u64 *startp, u64 *endp)
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{
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u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
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unsigned long start, end, inc;
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start = __pa(startp);
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end = __pa(endp);
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/* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
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if (tbl->it_busno) {
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start <<= 12;
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end <<= 12;
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inc = 128 << 12;
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start |= tbl->it_busno;
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end |= tbl->it_busno;
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}
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/* p7ioc-style invalidation, 2 TCEs per write */
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else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
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start |= (1ull << 63);
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end |= (1ull << 63);
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inc = 16;
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}
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/* Default (older HW) */
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else
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inc = 128;
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end |= inc - 1; /* round up end to be different than start */
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mb(); /* Ensure above stores are visible */
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while (start <= end) {
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__raw_writeq(start, invalidate);
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start += inc;
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}
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/* The iommu layer will do another mb() for us on build() and
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* we don't care on free()
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*/
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}
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static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction,
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unsigned long uaddr, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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struct dma_attrs *attrs)
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{
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{
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u64 proto_tce;
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u64 proto_tce;
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u64 *tcep;
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u64 *tcep, *tces;
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u64 rpn;
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u64 rpn;
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proto_tce = TCE_PCI_READ; // Read allowed
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proto_tce = TCE_PCI_READ; // Read allowed
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@ -270,25 +312,33 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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if (direction != DMA_TO_DEVICE)
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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proto_tce |= TCE_PCI_WRITE;
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tcep = ((u64 *)tbl->it_base) + index;
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tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
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rpn = __pa(uaddr) >> TCE_SHIFT;
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while (npages--) {
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while (npages--)
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/* can't move this out since we might cross LMB boundary */
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*(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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*tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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/* Some implementations won't cache invalid TCEs and thus may not
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* need that flush. We'll probably turn it_type into a bit mask
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* of flags if that becomes the case
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*/
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if (tbl->it_type & TCE_PCI_SWINV_CREATE)
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pnv_tce_invalidate(tbl, tces, tcep - 1);
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uaddr += TCE_PAGE_SIZE;
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tcep++;
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}
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return 0;
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return 0;
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}
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}
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static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
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static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
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{
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{
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u64 *tcep = ((u64 *)tbl->it_base) + index;
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u64 *tcep, *tces;
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tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
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while (npages--)
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while (npages--)
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*(tcep++) = 0;
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*(tcep++) = 0;
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if (tbl->it_type & TCE_PCI_SWINV_FREE)
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pnv_tce_invalidate(tbl, tces, tcep - 1);
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}
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}
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void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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@ -308,13 +358,14 @@ static struct iommu_table * __devinit
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pnv_pci_setup_bml_iommu(struct pci_controller *hose)
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pnv_pci_setup_bml_iommu(struct pci_controller *hose)
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{
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{
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struct iommu_table *tbl;
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struct iommu_table *tbl;
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const __be64 *basep;
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const __be64 *basep, *swinvp;
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const __be32 *sizep;
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const __be32 *sizep;
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basep = of_get_property(hose->dn, "linux,tce-base", NULL);
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basep = of_get_property(hose->dn, "linux,tce-base", NULL);
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sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
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sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
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if (basep == NULL || sizep == NULL) {
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if (basep == NULL || sizep == NULL) {
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pr_err("PCI: %s has missing tce entries !\n", hose->dn->full_name);
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pr_err("PCI: %s has missing tce entries !\n",
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hose->dn->full_name);
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return NULL;
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return NULL;
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}
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}
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tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
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tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
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@ -323,6 +374,15 @@ pnv_pci_setup_bml_iommu(struct pci_controller *hose)
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pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
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pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
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be32_to_cpup(sizep), 0);
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be32_to_cpup(sizep), 0);
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iommu_init_table(tbl, hose->node);
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iommu_init_table(tbl, hose->node);
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/* Deal with SW invalidated TCEs when needed (BML way) */
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swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
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NULL);
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if (swinvp) {
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tbl->it_busno = swinvp[1];
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tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
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tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
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}
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return tbl;
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return tbl;
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}
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}
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@ -106,7 +106,7 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
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tcep++;
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tcep++;
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}
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}
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if (tbl->it_type == TCE_PCI_SW_INVAL)
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if (tbl->it_type == TCE_PCI_SWINV_CREATE)
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tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
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tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
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return 0;
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return 0;
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}
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}
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@ -121,7 +121,7 @@ static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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while (npages--)
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while (npages--)
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*(tcep++) = 0;
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*(tcep++) = 0;
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if (tbl->it_type == TCE_PCI_SW_INVAL)
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if (tbl->it_type == TCE_PCI_SWINV_FREE)
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tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
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tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
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}
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}
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@ -511,7 +511,7 @@ static void iommu_table_setparms(struct pci_controller *phb,
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*/
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*/
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tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
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tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
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tbl->it_busno = sw_inval[1]; /* overload this with magic */
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tbl->it_busno = sw_inval[1]; /* overload this with magic */
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tbl->it_type = TCE_PCI_SW_INVAL;
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tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
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}
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}
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}
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}
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